DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/18/2024 were filed after filling the instant application on 06/30/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant's arguments filed 01/22/2026 have been fully considered but they are not persuasive. The reasons are set forth below:
Applicant’s arguments: Applicant’s arguments, page 7, stated “The Office Action notes that Shi does not teach or suggest the physical coding sublayer circuitry set forth in claim I (see, Office Action, page 4). The Office Action identifies description in Shi of adjusting timestamps, but as noted in the Office Action, Shi does not describe a physical coding sublayer circuitry and thus, cannot teach or suggest determine a first delay introduced by a physical coding sublayer circuitry at a first time and cannot adjust a first timestamp associated with a first transmission based on the first delay that is introduced by the
physical coding sublayer circuitry. Similarly, Shi cannot teach or suggest to determine a second
delay introduced by a physical coding sublayer circuitry at a second time and cannot adjust a
second timestamp associated with a second transmission based on the second delay.
Furthermore, while claim I sets forth that the adjustment for the delay introduced by the physical
coding sublayer circuitry is performed so that the timestamp is transmitted "with the first
transmission", Shi is directed to adjusting for delays from the transmission from the first network
device to the second network device (see, for example, Para. [0009]). Thus, the delays that Shi is
adjusting are based on the transmission, not performed to include the timestamp in the
transmission. The Office Action cites Bordogna in an effort to cure the deficiencies of Shi. In
particular, the Office Action alleges that Bordogna describes the physical coding sublayer
circuitry. While Bordogna describes a PCS layer 202 and a scheme for compensating for start-of frame
delimiter detection delay and delay variations, there is no teaching or suggestion in Bordogna that would lead one to determine first delays and second delays and perform first adjustments and second adjustments as set forth in claim 1. Nor any teaching or suggestion of how multiple delays and adjustments would be utilized. Thus, it is respectfully submitted that the Shi/Bordogna combination fails to teach or
suggest all of the elements of claim 1. Accordingly, reconsideration of the rejection of claim 1 and all claims depending therefrom is requested.”
Examiner’s Response: The examiner respectfully disagrees. The examiner’s rejection is based on the applicant’s claims recitation and the examiner must interpret every claim limitations under the broadest reasonable interpretation (BRI). In reference to the applicant’s argument, She teaches first delay, , fig 2-3, para [0011] and fig 7-8, para [0152]-[0158], where, adjust the second virtual clock based on the delay information. Shi teaches, in fig 2-3, para [0158], that the Master device sent the timestamps to the Slave device, however, Shi does not explicitly teach: a physical coding sublayer, however Bordogna in the same field of endeavored teaches, see (fig 3, module 202, para [0029], where, “The PCS layer 202 can be broken down into four major functions), Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the invention to use “physical coding sublayer circuitry” as taught by Bordogna into Shi in order to remove the delay variation of the Ethernet PCS layer (Bordogna: para [0014]). Therefore, Shi in view of Bordogna teach all the limitations in full. Hence the arguments are traversed.
All the remaining arguments are based on the arguments above and are responded to in full.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may rth be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 8-10, 13-20 are rejected under 35 U.S.C. 103 as being unpatentable Shi et al (US 2023/0050042 A1), hereinafter, “Shi” in view of Bordogna et al (US 2015/0055644 A1), hereinafter, “Bordogna”.
Regarding claim 1, Shi disclose: An apparatus (fig 1, GNSS apparatus 113, para [0061]) comprising: network interface circuitry (fig 9, para [0173], where, “the obtaining unit 901 may be a communication interface in the network device”);
logic circuitry configured to execute instructions to cause the logic circuitry (para [0178], where, “provides a system on chip, where the system on chip includes a logic circuit”) to: determine a first delay introduced by a physical coding sublayer circuitry at a first time (fig 6-7, at step 701, para [0011] and para [0158], where, “determining a first delay based on the forward delay”);
adjust a first timestamp associated with a first transmission based on the first delay (fig 3 and fig 7, at step 702, para [0158], where, “adjusting a phase of the …. clock based on the first delay”), the first timestamp transmitted with the first transmission (fig 2, time t1 and t4, para [0067]-[0070], where, the first timestamp t1 is transmitted in first time);
determine a second delay introduced by the physical coding sublayer circuitry at a second time (fig 3 and fig 6, step 602, para [0117], where, “the timestamp T2, and determine a second delay based on a reverse delay),
the second delay different than the first delay (fig 3, para [0014]-[0015], where, second delay based on the reverse delay, hence first delay is different than second delay); and
adjust a second timestamp associated with a second transmission based on the second delay (fig 7, step 702, para [0128]-[0129], where, “Step 702: Adjust the timestamps T2 and T3 based on the frequency information to obtain a timestamp T2′ and a timestamp T3”), the second timestamp transmitted with the second transmission (fig 2, time t1 and t4, para [0067]-[0070], where, the first timestamp t2 is transmitted in first time);
Shi does not explicitly teach: physical coding sublayer circuitry.
However, Bordogna teaches: physical coding sublayer circuitry (fig 3, module 202, para [0029], where, “The PCS layer 202 can be broken down into four major functions: a synchronization process (performed by the block 210), a transmit process (performed by the block 212), a receive process (performed by the block 214), and an auto-negotiation process (performed by the block 216). Services provided to the GMII include: encoding/decoding of GMII data octets to/from ten-bit code groups (8 B/10 B) for communication within the underlying PMA; Carrier Sense (CRS) and Collision Detect (COL) indications; and managing the auto-negotiation process by informing the auto-negotiation process when the PCS has lost synchronization of the received code groups”).
Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the invention to use “physical coding sublayer circuitry” as taught by Bordogna into Shi in order to remove the delay variation of the Ethernet PCS layer (Bordogna: para [0014]).
Regarding claim 13, the claim includes features identical to the subject matter mentioned in the rejection to claim 1 above. The claims are mere reformulation of claim 1 in order to define the corresponding information processing apparatus, and the rejection to claim 1 is applied hereto. Additionally, the claim includes clock circuitry. However, Shi discloses clock circuitry (para [0004]).
Regarding claim 2, Shi modified by Bordogna disclose: The apparatus of claim 1 (fig 1, GNSS apparatus 113, para [0061]), wherein the instructions cause the logic circuitry (Shi: para [0021], execute instructions) to determine the first delay at a start of transmission of a first signal and to determine the second delay at the start of transmission of a second signal (fig 2, para [0010], where, determined first delay, para [0067]).
Regarding claim 3, Shi modified by Bordogna disclose: The apparatus of claim 1 (fig 1, GNSS apparatus 113, para [0061]), wherein the instructions cause the logic circuitry to insert the first timestamp in a time synchronization message (fig 2, para [0004] and para [0067], where, the master device sends the Synchronization message to a server in first timestamp).
Regarding claim 4, Shi modified by Bordogna disclose: The apparatus of claim 1 (fig 1, GNSS apparatus 113, para [0061]), wherein the instructions cause the logic circuitry to determine the first delay based on a state of the physical coding sublayer circuitry (fig 2, para [0004] and para [0067], where, the master device equivalent to “physical coding sublayer circuitry”).
Regarding claim 5, Shi modified by Bordogna disclose: The apparatus of claim 4, wherein the state of the physical coding sublayer circuitry includes an alignment between a first clock signal and a second clock signal (para [0005], where, describe pluralities of clocks).
Regarding claim 8, Shi modified by Bordogna disclose: The apparatus of claim 1 (fig 1, GNSS apparatus 113, para [0061]), wherein the physical coding sublayer circuitry includes encoder circuitry and the instructions cause the logic circuitry to determine the first delay of the encoder circuitry (Bordogna: para [0021], where, “for Ethernet forward error correction (FEC) encoded links, a 2112 bit FEC frame is viewed as 64 equal instances of 33 bits”).
Regarding claim 9, Shi modified by Bordogna disclose: The apparatus of claim 8 (fig 1, GNSS apparatus 113, para [0061]), wherein the encoder circuitry is error correction circuitry (Bordogna: para [0021], where, “for Ethernet forward error correction (FEC) encoded links, a 2112 bit FEC frame is viewed as 64 equal instances of 33 bits”).
Regarding claim 12, Shi modified by Bordogna disclose: The apparatus of claim 9 (fig 1, GNSS apparatus 113, para [0061]), wherein the first delay is associated with a first frame of data (Shi: para [0011]) and the instructions cause the logic circuitry to determine the second delay for a second frame of the data as a number of cycles less than the first delay (Shi: fig 2 and 3, para [0158]).
Regarding claim 14, Shi modified by Bordogna disclose: The apparatus of claim 13 (fig 1, GNSS apparatus 113, para [0061]), wherein the instructions cause the logic circuitry to determine the first delay based on a state of the physical coding sublayer circuitry (Bordogna: fig 3, para [0028], where, “The PCS layer 202 comprises a synchronization block 210, a transmit state machine 212, a receive state machine 214, an auto-negotiation block 216, and a delay measurement block 218”).
Regarding claim 15, Shi modified by Bordogna disclose: The apparatus of claim 13 (fig 1, GNSS apparatus 113, para [0061]), wherein the instructions cause the logic circuitry to determine the first delay based on a first variable delay of a first bit level conversion (Bordogna: para [0024], where, the PMA performs functions including bit level conversion).
Regarding claim 16, Shi modified by Bordogna disclose: The apparatus of claim 15 (fig 1, GNSS apparatus 113, para [0061]), wherein the instructions cause the logic circuitry to determine the first delay further based on a second variable delay of a second bit level conversion (Bordogna: para [0024], where, “The PMA performs functions including, but not limited to, (i) bit level multiplexing from M lanes to N lanes in the transmit direction, (ii) bit level demultiplexing from one lane (or N lanes) to M lanes in the receive direction, followed by shifting from the arbitrary boundary to the bus boundary or octet boundary, (iii) clock and data recovery ….”).
Regarding claim 17, Shi modified by Bordogna disclose: The apparatus of claim 13 (fig 1, GNSS apparatus 113, para [0061]), wherein the instructions cause the logic circuitry to determine the first delay based on a variable delay of an error correction process (Shi: para [0143], where, evaluate and perform the error correction).
Regarding claim 18, Shi disclose: A method (fig 2, para [0009]) comprising: adjusting a first timestamp based on a first delay of a first physical coding sublayer associated with receiving a first time synchronization message (fig 2, para [0067], where, “a master device sends a synchronization message (Sync message) to a slave device at a moment t1. The synchronization message carries a timestamp t1”);
adjusting a second timestamp based on a second delay of a second physical coding sublayer associated with transmission of a second time synchronization message (fig 8, para [0157]-[0158], where, second time stamp is adjusted based on second delay); and
adjust a clock time based on at least the first timestamp and the second timestamp (fig 4, para [0085], where, in step 402, “T-TSC adjusts a virtual clock T-TSC in the T-TSC based on the collected delay information”);
Shi does not explicitly teach: physical coding sublayer circuitry.
However, Bordogna teaches: physical coding sublayer circuitry (fig 3, module 202, para [0029], where, “The PCS layer 202 can be broken down into four major functions: a synchronization process (performed by the block 210), a transmit process (performed by the block 212), a receive process (performed by the block 214), and an auto-negotiation process (performed by the block 216). Services provided to the GMII include: encoding/decoding of GMII data octets to/from ten-bit code groups (8 B/10 B) for communication within the underlying PMA; Carrier Sense (CRS) and Collision Detect (COL) indications; and managing the auto-negotiation process by informing the auto-negotiation process when the PCS has lost synchronization of the received code groups”).
Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the invention to use “physical coding sublayer circuitry” as taught by Bordogna into Shi in order to remove the delay variation of the Ethernet PCS layer (Bordogna: para [0014]).
Regarding claim 19, Shi modified by Bordogna disclose: The method of claim 18 (fig 1, GNSS apparatus 113, para [0061]), further comprising transmitting the second time synchronization message to a time server (fig 2, para [0004] and para [0067], where, the master device sends the Synchronization message to a server).
Regarding claim 20, Shi modified by Bordogna disclose: The method of claim 18 (fig 1, GNSS apparatus 113, para [0061]), further comprising inserting the second timestamp into the second time synchronization message (fig 2, para [0004] and para [0067], where, the master device sends the Synchronization message to a server).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable Shi et al (US 2023/0050042 A1), hereinafter, “Shi” in view of Bordogna et al (US 2015/0055644 A1), hereinafter, “Bordogna” further in view of Chapman et al (US 2018/0107579 A1), hereinafter, “Chapman”.
Regarding claim 6, Shi modified by Bordogna disclose: The apparatus of claim 5 (Shi: fig 1, GNSS apparatus 113, para [0061]), wherein the instructions cause the logic circuitry (Shi: para [0022], where, “where the logic circuit is configured to couple to an input/output interface, and transmit data through the input/output interface, to perform the method”)
However, neither Shi nor Bordogna explicitly teach: to determine the first delay based on a difference between a first edge of the first clock signal and a second edge of the second clock signal.
Chapman teaches: to determine the first delay based on a difference between a first edge of the first clock signal and a second edge of the second clock signal (Chapman: para [0018], where, “the phase difference is determined by the comparator circuit determining a time difference between a rising edge of the first reference clock signal and a rising edge of the second reference clock signal”).
Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the invention to use “wherein the encoder circuitry is Reed-Solomon error correction circuitry” as taught by Chapman into Shi in order to improve the accuracy of the time stamp (Chapman: para [0047]).
Regarding claim 7, Shi modified by Bordogna further modified by Chapman disclose: The apparatus of claim 6 (Shi: fig 1, GNSS apparatus 113, para [0061]), wherein the instructions cause the logic circuitry to determine the first delay based on a difference between a first rising edge of the first clock signal and a second rising edge of the second clock signal (Chapman: para [0018], where, “the phase difference is determined by the comparator circuit determining a time difference between a rising edge of the first reference clock signal and a rising edge of the second reference clock signal”).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable Shi et al (US 2023/0050042 A1), hereinafter, “Shi” in view of Bordogna et al (US 2015/0055644 A1), hereinafter, “Bordogna” further in view of Rabenko et al (US 2005/0031097 A1), hereinafter, “Rabenko”.
Regarding claim 10, Shi modified by Bordogna disclose: The apparatus of claim 9 (Shi: fig 1, GNSS apparatus 113, para [0061]), neither Shi nor Bordogna explicitly teach: wherein the encoder circuitry is Reed-Solomon error correction circuitry.
Rabenko teaches: wherein the encoder circuitry is Reed-Solomon error correction circuitry (Rabenko: para [0127], where, “A/C decoder consists of four major functions, frame synchronization, convolution de-interleaving, Reed-Solomon error correction and de-randomization”).
Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the invention to use “wherein the encoder circuitry is Reed-Solomon error correction circuitry” as taught by Rabenko into Shi in order to accomplish TDMA for upstream communication (Rabenko: para [0084]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable Shi et al (US 2023/0050042 A1), hereinafter, “Shi” in view of Bordogna et al (US 2015/0055644 A1), hereinafter, “Bordogna” further in view of Kuo et al (US 2018/0169472 A1), hereinafter, “Kuo”.
Regarding claim 11, Shi modified by Bordogna disclose: The apparatus of claim 9 (Shi: fig 1, GNSS apparatus 113, para [0061]), neither Shi nor Bordogna explicitly teach: wherein the instructions cause the logic circuitry to determine the first delay based on a relative position of a start of a packet in a frame of the encoder circuitry.
Kuo teaches: wherein the instructions cause the logic circuitry to determine the first delay based on a relative position of a start of a packet in a frame of the encoder circuitry (Kuo: para [0023], where, “the server calculates and determines the position and the motion trail of the intelligent ball and the wearing device”).
Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the invention to use “wherein the encoder circuitry is Reed-Solomon error correction circuitry” as taught by Kuo into Shi in order to improve the accuracy of the synchronization signalling (Kuo: para [0023]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIZAM U AHMED whose telephone number is (571)272-9561. The examiner can normally be reached Mon-Fry, 7:00 AM-6:00 PM PST.
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/NIZAM U AHMED/Primary Examiner, Art Unit 2461
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