Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 11, it is unclear why the fifth set of ECC bits and fourth set of ECC bits would be compared, considering there is no explicit relationship between the two- it is further unclear why both would be read from memory to be compared, when the rest of the invention seems directed at loading one set of data bits and on set of ECC bits from memory, generating a second set of ECC bits based on the loaded data bits and the tag, and comparing the generated ECC bits and the read ECC bits to verify no errors are present. Upon consultation of the specification, no further description could be located regarding this situation. Examiner’s best guess is that the limitation “the fifth set of ECC bits to be read from the memory” is erroneous and the claim is intended to highlight a situation where an error has occurred, and the fourth set of ECC bits is read and compared instead of a set of ECC bits corresponding to the third tag and fifth set of data bits. For the 102/103 rejection portion of this action, this interpretation is applied. However, appropriate correction and/or clarification is still required. Additionally, examiner would like to note that if the limitation “the fifth set of ECC bits to be read from memory” is written as intended, there is a missing step of storing the fifth set of ECC bits to memory.
Claim 13 is similarly found to be unclear as it also references the comparison between the fourth and fifth sets of ECC bits. Appropriate correction and/or clarification is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 7-9, 14, and 17-20 are rejected under 35 U.S.C. 102a1 as being anticipated by Loewenstein (US Patent No. 8812935 B2).
Regarding claim 1, Loewenstein teaches:
An apparatus comprising:
a processor to provide a first set of data bits and a first tag in connection with a store operation; (see fig. 1, processor 102. Also see col. 1, lines 44-45: During operation, the memory system writes a data block to an address.) It is well known in the art that it is the processor of a memory system that performs read and write operations, therefore the write described here is considered to be performed by a processor. Further, address information is considered to be (or at least contain) a tag.
and an error correcting code (ECC) generation circuit to generate a first set of ECC bits based on a first set of data bits and a first tag. (see col. 1, lines 44-48: During operation, the memory system writes a data block to an address. In doing so, the system first calculates a hash of the address and uses the calculated hash and the data bits to compute error correcting code (ECC) check bits for the data block.)
Regarding claim 2, Loewenstein teaches the apparatus of claim 1. Loewenstein further teaches:
further comprising a memory to store the first set of data bits and the first set of ECC bits. (see col. 6, lines 29-34: the system computes ECC check bits 316 based on the data bits 310, the address hash 308 and the not-data indicator 254 (step 404). The system then stores a data block containing the data bits 310 and ECC check bits 316 at a memory location specified by the address 302 (step 406).)
Regarding claim 7, Loewenstein teaches the apparatus of claim 2. Loewenstein further teaches:
wherein the ECC generation circuit is also to generate a second set of ECC bits based on a second set of data bits and a second tag, wherein the second set of data bits is read from the memory. (see fig. 6, operation 602: during a memory operation, use an address to retrieve a data block containing data bits and ECC check bits. -> Operation 604: calculate a hash of address. -> Operation 606: use the data bits and the hash to compute ECC check bits.)
Regarding claim 8, Loewenstein teaches the apparatus of claim 7. Loewenstein further teaches:
wherein the processor is to provide the second tag in connection with a load operation. (see col. 1, lines 60-63: ) The memory system can also read the data block. This involves using the address to retrieve the data block containing the data bits and associated ECC check bits.) It is well known in the art that it is the processor of a memory system that performs read and write operations, therefore the read here described here is considered to be performed by a processor. Further, address information is considered to be (or at least contain) a tag.
Regarding claim 9, Loewenstein teaches the apparatus of claim 8. Loewenstein further teaches:
further comprising a comparator to compare the second set of ECC bits and a third set of ECC bits, the third set of ECC bits to be read from the memory. (see fig. 6, operation 602: during a memory operation, use an address to retrieve a data block containing data bits and ECC check bits. -> Operation 604: calculate a hash of address. -> Operation 606: use the data bits and the hash to compute ECC check bits. -> Operation 608: compare the computed ECC check bits with the retrieved ECC check bits to determine whether there exists an error in the address or data bits).
Regarding claim 14, Loewenstein teaches the apparatus of claim 8. Loewenstein further teaches:
wherein the processor includes a register to store the second tag (see col. 1, lines 31-34: For example, Such address errors can be caused by noisy communication channels, or timing problems that occur when latching an address in a temporary register while the address is in transit to the memory.) As discussed above, the processor is well known to be the element that generally performs read/write operations in a memory system. Therefore, the temporary register used while transferring an address to memory (e.g., for a read/write operation) is considered to be used by, and therefore included in the processor. Additionally, as discussed previously, address information is considered to be (or at least contain) a tag.
Claims 17 and 19 correspond to claim 1, and are rejected accordingly.
Claims 18 and 20 correspond to the combination of claims 7, 8, and 9, and are rejected accordingly, but for the added limitation, which is also taught by Loewenstein:
and comparing the second set of ECC bits and the third set of ECC bits to determine whether the second tag matches the first tag. (see fig. 6, operation 602: during a memory operation, use an address to retrieve a data block containing data bits and ECC check bits. -> Operation 604: calculate a hash of address. -> Operation 606: use the data bits and the hash to compute ECC check bits. -> Operation 608: compare the computed ECC check bits with the retrieved ECC check bits to determine whether there exists an error in the address or data bits).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3-6 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Loewenstein in view of Deutsch (US Publication No. 2022/0114112).
Regarding claim 3, Loewenstein teaches the apparatus of claim 1. Lowenstein further teaches:
wherein the ECC generation circuit is to generate the first set of ECC bits from… input symbols based on the first set of data bits and the first tag. (see col. 1, lines 44-48: During operation, the memory system writes a data block to an address. In doing so, the system first calculates a hash of the address and uses the calculated hash and the data bits to compute error correcting code (ECC) check bits for the data block.)
However, Loewenstein does not explicitly teach:
[implementing ECC using] Reed-Solomon
In the analogous art of error correction codes in memory, Deutsch teaches:
[implementing ECC using] Reed-Solomon (see para. 17: In some examples described herein, a certain type of metadata may be embedded into memory authentication and correction single device data correction capability (e.g., using Reed-Solomon codes).)
It would be obvious to one of ordinary skill in the art, having the teachings of Loewenstein and Deutsch before them, before the effective filing date of the claimed invention, to implement Reed Solomon as the error correction algorithm (Deutsch), into Loewenstein’s system for calculating ECC based on data bits and a hash of the address, because Reed Solomon codes are extremely well known in the art and one of ordinary skill in the art would consider them obvious alternative way to implement ECC codes. Further, Reed Solomon codes are well known in the art to provide benefits such as flexibility, protection against burst errors, and the ability to correct both errors and erasures. Regarding claim 4, Loewenstein teaches the apparatus of claim 1. However, Loewenstein does not explicitly teach:
Wherein the first set of data bits are encrypted.
Deutsch teaches:
Wherein the first set of data bits are encrypted. (see para. 34: When used in conjunction with memory integrity , a tweakable block cipher may be used to encrypt Reed Solomon symbols and inputs to the error correction codes . The size of correction symbol is determined by the encryption block size . Encrypting the data inputs and symbols is an effective solution to row hammer style attacks on DRAM, while maintaining error correction capabilities.)
It would be obvious to one of ordinary skill in the art, having the teachings of Loewenstein and Deutsch before them, before the effective filing date of the claimed invention, to implement encrypting data bits input to ECC (Deutsch), into Loewenstein’s system for calculating ECC based on data bits and a hash of the address, to allow for benefits such as protection against row hammer style attacks while maintaining error correction capabilities (Deutsch, para. 34).
Regarding claim 5, Loewenstein teaches the apparatus of claim 1. However, Loewenstein does not explicitly teach:
wherein the first set of ECC bits are encrypted.
Deutsch teaches:
wherein the first set of ECC bits are encrypted. (see para. 34: When used in conjunction with memory integrity, a tweakable block cipher may be used to encrypt Reed Solomon symbols and inputs to the error correction codes . The size of correction symbol is determined by the encryption block size . Encrypting the data inputs and symbols is an effective solution to row hammer style attacks on DRAM, while maintaining error correction capabilities.) The Reed Solomon symbols are considered to be the ECC bits, following the same reasoning applied in the rejection of claim 3.
It would be obvious to one of ordinary skill in the art, having the teachings of Loewenstein and Deutsch before them, before the effective filing date of the claimed invention, to implement encrypting ECC bits (Deutsch), into Loewenstein’s system for calculating ECC based on data bits and a hash of the address, to allow for benefits such as protection against row hammer style attacks while maintaining error correction capabilities (Deutsch, para. 34).
Regarding claim 6, Loewenstein teaches the apparatus of claim 1. Loewenstein further teaches:
[inputs to ECC generation include an address] (see col. 1, lines 44-48: During operation, the memory system writes a data block to an address. In doing so, the system first calculates a hash of the address and uses the calculated hash and the data bits to compute error correcting code (ECC) check bits for the data block.)
However, Loewenstein does not explicitly teach:
wherein the first tag is encrypted
Deutsch teaches:
Wherein [inputs to ECC generation are] encrypted (see para. 34: When used in conjunction with memory integrity, a tweakable block cipher may be used to encrypt Reed Solomon symbols and inputs to the error correction codes.)
It would be obvious to one of ordinary skill in the art, having the teachings of Loewenstein and Deutsch before them, before the effective filing date of the claimed invention, to implement encrypting inputs to ECC (Deutsch), into Loewenstein’s system where inputs to ECC include an address (considered to be or at least include a tag), to allow for benefits such as protection against row hammer style attacks while maintaining error correction capabilities (Deutsch, para. 34).
Regarding claim 15, Loewenstein teaches the apparatus of claim 1. Deutsch further teaches:
further comprising: a first plurality of bijective diffusion function circuits to diffuse the first set of data bits into a first set of diffused data bits; a second plurality of bijective diffusion function circuits to diffuse the first set of ECC bits into of first set of diffused ECC bits; and a memory to store the first set of diffused data bits and the first set of diffused ECC bits. (see para. 34: When used in conjunction with memory integrity, a tweakable block cipher may be used to encrypt Reed Solomon symbols and inputs to the error correction codes.) One of ordinary skill in the art would readily recognize that applying a tweakable block cipher to the ECC symbols would be effectively implemented by a first plurality of bijective diffusion function circuits, and applying a tweakable block cipher to the data bits would be effectively implemented by a second plurality of bijective diffusion function circuits. The encrypted ECC bits and data bits are considered to be equivalent to a set of diffused ECC bits.
It would be obvious to one of ordinary skill in the art, having the teachings of Loewenstein and Deutsch before them, before the effective filing date of the claimed invention, to implement encrypting ECC bits (Deutsch), into Loewenstein’s system for calculating ECC based on data bits and a hash of the address, to allow for benefits such as protection against row hammer style attacks while maintaining error correction capabilities (Deutsch, para. 34).
Regarding claim 16, the combination of Loewenstein and Deutsch teaches the apparatus of claim 15. Deutsch further teaches:
further comprising: a first plurality of inverse bijective diffusion function circuits to generate a second set of data bits from the first set of diffused data bits stored in the memory; and a second plurality of inverse bijective diffusion function circuits to generate a second set of ECC bits from the first set of diffused ECC bits stored in the memory. (Deutsch, para. 34: When used in conjunction with memory integrity, a tweakable block cipher may be used to encrypt Reed Solomon symbols and inputs to the error correction codes… decrypting the symbol cipher text using a secret key is required to determine the corresponding symbol used for error correction.). Loewenstein teaches: (Loewenstein, see fig. 6, operation 602: during a memory operation, use an address to retrieve a data block containing data bits and ECC check bits. -> Operation 604: calculate a hash of address. -> Operation 606: use the data bits and the hash to compute ECC check bits. -> Operation 608: compare the computed ECC check bits with the retrieved ECC check bits to determine whether there exists an error in the address or data bits).) Lowenstein teaches retrieving the stored ECC and data bits (to determine the symbols used for error correction), according to Deutsch (and as would be readily recognized by one of ordinary skill in the art), to determine the symbols used for error correction (ECC and data bits), the ECC and data bits would need to be decrypted first. One of ordinary skill in the art would further recognize that decrypting a tweakable block cipher applied to the ECC symbols would be effectively implemented by a first plurality of inverse bijective diffusion function circuits, and decrypting a tweakable block cipher applied to the data bits would be effectively implemented by a second plurality of inverse bijective diffusion function circuits. The decrypted ECC bits and data bits are considered to be the second ECC bits and second data bits.
Claims 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Loewenstein in view of Barroso (US Patent No. 6725343)
Regarding claim 10, Loewenstein teaches the apparatus of claim 9. Lowenstein further teaches:
further comprising a cache, (see fig. 1, cache 104)
wherein: the first set of data bits corresponds to a… cache line; (col. 5, lines 52-53: In an exemplary embodiment, data block 200 comprises a cache line which has a total of 72 bytes.)
and the ECC generation circuit is also to generate a fourth set of ECC bits based on a third set of data bits and… [a memory address (tag)], … and the fourth set of ECC bits is to be stored in the memory. (see col. 6, lines 29-34: the system computes ECC check bits 316 based on the data bits 310, the address hash 308 and the not-data indicator 254 (step 404). The system then stores a data block containing the data bits 310 and ECC check bits 316 at a memory location specified by the address 302 (step 406).)
In the analogous art of error correction for cache/memory, Barroso teaches:
The first set of data bits corresponds to a first portion of a cache line; … wherein the third set of data bits corresponds to a second portion of the cache line; … (see col. 8, lines 23-30: A “memory line” is the unit of memory that fits into one cache line of the L1 cache modules 108, 110 and L2 caches 114. In a preferred embodiment, a memory line is 512 bits (64 bytes, or eight 64-bit words) of data; however, the size of the memory line will vary from one implementation to another. Each memory line 184 also includes two 10-bit ECC (error correction code) codes (one for each half memory line).
[two sets of data bits corresponding to the same cache line have the same memory address (or at least a field/tag in common)] (see col. 12, lines 1-14: In a preferred embodiment, the top M (e.g., 10) bits of the memory line address identify the home node 102,104 of the memory line of information 184, while the remainder of the address bits identify the memory line 184 within the identified node. In a preferred embodiment, the memory line address for a memory line does not include any of the address bits used to identify Sub-portions of the memory line, Such as individual 64-bit words or individual bytes within the memory line of information 184. However, in other embodiments that Support transactions on Sub-portions of memory lines, the memory line addresses used may include bits for identifying Such memory line Sub-portions.) It would be obvious to one of ordinary skill in the art that the Loewenstein’s address is analogous to the memory line address here. Even in the alternate implementation described where the memory line addresses include bits for identifying sub-portions, the memory line address would still include the top M (10) bit field identifying the home node, which can be considered a tag and would be the same for both data sets in a same cache line. Further, because this tag is part of the address, both sets of ECC bits would be generated at least in part based on it.
It would have been obvious to one of ordinary skill in the art, having the teachings of Loewenstein and Barroso before them before the effective filing date of the claimed invention, to incorporate a split cache line architecture with each half independently protected by ECC (Barroso), into Loewenstein’s system where ECC bits are generated based on the data bits they protect and an address, to allow for benefits such as efficient sub-block access (Barroso, col. 23, lines 30-34: For instance, if only half of the directory entry for a memory line requires updating, and the directory State remains unchanged, then only one of the memory line's Sub-blocks needs to be updated.) and ECC storage efficiency (Barroso, col. 17, lines 36-50: AS FIG. 4 illustrates, if a Separate ECC is calculated for each half memory line, the two ECC's for each 64-byte memory line occupy only 20 bits, rather than the 64 bits that would be required if a separate ECC were calculated for each 64 bits of data. As a result, 44 bits of the 64 Supplemental bits per memory line are available for use as a memory directory entry. In a preferred embodiment the 44 bits for the directory entry are allocated between a 40-bit sharer information field 188 and a state field 186 comprising two repeated 2-bit State fields. Combining the data and directory in the DRAM banks through a coarser granularity ECC effectively results in Zero Storage overhead for the memory directory, and it also avoids the need for a Separate Set of pins and controller logic to access the memory directory.).
Regarding claim 11, the combination of Loewenstein and Barroso teaches the method of claim 10. As discussed in the 112B rejection, it is assumed that the fifth set of ECC bits is not read from the memory. Loewenstein further teaches:
wherein: the ECC generation circuit is also to generate a fifth set of ECC bits based on a fifth set of data bits and a third tag, (see col. 1, lines 61-67: This involves using the address to retrieve the data block containing the data bits and associated ECC check bits. Next, the system calculates a hash of the address and uses the calculated hash and the data bits to compute ECC check bits. Finally, the system compares the computed ECC check bits with the retrieved ECC check bits to determine whether an error exists in the address or data bits.) Here, the fifth set of ECC bits would be the computed ECC check bits, the fifth set of data bits and fourth set of ECC bits would be the retrieved data bits and ECC check bits, and the third tag corresponds to the address. Notably, this situation would arise due a read/address error that caused the fourth set of ECC bits to be retrieved (instead of ECC bits corresponding to the third tag and fifth data bits), or a previous write error that caused the fourth set of ECC bits to be stored with the fifth set of data bits.
Regarding claim 12, the combination of Loewenstein and Barroso teaches the method of claim 11. Loewenstein further teaches:
wherein the processor is to provide the third tag in connection with the load operation. (see col. 1, lines 60-63: ) The memory system can also read the data block. This involves using the address to retrieve the data block containing the data bits and associated ECC check bits.) It is well known in the art that it is the processor of a memory system that performs read and write operations, therefore the read here described here is considered to be performed by a processor. Further, address information is considered to be (or at least contain) a tag.
Regarding claim 13, the combination of Loewenstein and Barroso teaches the apparatus of claim 11. Loewenstein further teaches:
wherein: the cache line includes a first valid bit… [for each set of ECC check bits]; (see col. 2, lines 1-5: In some embodiments, computing the ECC check bits involves using a “not-data indicator” (possibly along with the hash of the address bits) to compute the ECC check bits, wherein the not-data indicator indicates whether an uncorrectable error has previously been detected in the data block.) This clearly shows that for each set of data bits and corresponding ECC check bits, a not-data indicator would be provided.
the first valid bit is to be marked invalid in response to the comparator detecting a mismatch between the second set of ECC bits and the third set of ECC bits; and the second valid bit is to be marked invalid in response to the comparator detecting a mismatch between the fifth set of ECC bits and the fourth set of ECC bits. (First, if the data has been corrupted, for example if a previous comparison between computed ECC check bits and retrieved ECC check bits indicated an uncorrectable error exists in a retrieved data block [i.e., a mismatch between the two sets of ECC bits is detected], the system sets the not-data indicator 254 (step 402).)
Barroso teaches:
[one cache line includes two or more sub-blocks, each individually protected by ECC bits] (see col. 8, lines 23-30: A “memory line” is the unit of memory that fits into one cache line of the L1 cache modules 108, 110 and L2 caches 114. In a preferred embodiment, a memory line is 512 bits (64 bytes, or eight 64-bit words) of data; however, the size of the memory line will vary from one implementation to another. Each memory line 184 also includes two 10-bit ECC (error correction code) codes (one for each half memory line).
It would have been obvious to one of ordinary skill in the art, having the teachings of Loewenstein and Barroso before them before the effective filing date of the claimed invention, to incorporate a split cache line architecture with each half independently protected by ECC (Barroso), into Loewenstein’s system where a not-data (valid) indicator is provided for each section of data protected by ECC, to allow for benefits such as efficient sub-block access (Barroso, col. 23, lines 30-34: For instance, if only half of the directory entry for a memory line requires updating, and the directory State remains unchanged, then only one of the memory line's Sub-blocks needs to be updated.) and ECC storage efficiency (Barroso, col. 17, lines 36-50: AS FIG. 4 illustrates, if a Separate ECC is calculated for each half memory line, the two ECC's for each 64-byte memory line occupy only 20 bits, rather than the 64 bits that would be required if a separate ECC were calculated for each 64 bits of data. As a result, 44 bits of the 64 Supplemental bits per memory line are available for use as a memory directory entry. In a preferred embodiment the 44 bits for the directory entry are allocated between a 40-bit sharer information field 188 and a state field 186 comprising two repeated 2-bit State fields. Combining the data and directory in the DRAM banks through a coarser granularity ECC effectively results in Zero Storage overhead for the memory directory, and it also avoids the need for a Separate Set of pins and controller logic to access the memory directory.).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK K BARNETT whose telephone number is (571)270-0431. The examiner can normally be reached M-Th 8-5, F 8-4 EST.
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/JACK KENSINGTON BARNETT/ Examiner, Art Unit 2111
/MARK D FEATHERSTONE/ Supervisory Patent Examiner, Art Unit 2111
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