DETAILED ACTION
This action is responsive to the following: the amendment to claims and the arguments made in amendment filed on February 27, 2026 and the request for continued examination filed on April 1, 2026.
Claims 1-24 are pending. Claims 1, 8, 12 and 21 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on February 27, 2026 has been entered. Claims 1-24 remain pending. The amendments to claims overcome the objections set forth in the previous office action.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 1, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 20240055051) in view of Park et al (US 20080007999) and Futatsuyama (US 20070025152 A1).
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Regarding Independent Claim 1, Yang teaches a memory device (Fig. 2: 200), comprising:
a memory block (Fig. 2A: 202) to which first (Fig. 4D: Upper sub-block) and second (Fig. 4D: Lower Sub-Block) word line groups are coupled, and to which a first dummy line group (Fig. 4D: WL_RC1-4; para 136) disposed between the first (Fig. 4D: Upper sub-block) and second (Fig. 4D: Lower Sub-Block) word line groups is coupled; and
a peripheral circuit (Fig. 2A: 220, 210) configured to program memory cells coupled to a selected word line of the first or second word line group,
wherein the peripheral circuit is configured to:
when the selected word line (Fig. 12: Selected WL, WL0) is included in the second word line group (Fig. 4D: Lower Sub-Block), when a program voltage (Fig. 12: Selected WL, WL0, VPGM) is applied to the selected word line (Fig. 12: Selected WL, WL0), apply a first pass voltage (Fig. Selected WL, WL0, Vpass2) to unselected word lines included in the first (Fig. 12: WL1-WL_133) and second (Fig. 12: WL134-WL_267) word line groups and to dummy lines (Fig. 12: WL_RC1-WL_RC4, para 136) included in the first dummy line group, and
Yang further teaches when the selected word line is included in the first word line group (Fig. 4D: Upper sub-block), when the program voltage is applied to the selected word line (Fig. 12: Selected WL, WL134, VPGM), applying a first pass voltage (Fig. 12: Vpass2) to the unselected WL of the second group (Fig. 12: WL134-WL_267) and multiple pass voltages (Fig. 12: Vpass1-Vpass3), which can be applied to the dummy word lines (Fig. 12: WL_RC1-WL_RC4, para 136).
However, Yang does not teach allowing first unselected word lines disposed between the selected word line and the first dummy line group to float, and applying the same pass voltage to the first unselected word lines among word lines included in the first word line group as the unselected word lines in the second group.
Park teaches applying the same voltage (Fig. 10: Program, Vpass) to the unselected word lines in the first word line group (Fig. 9: BLK2) as the world lines in the second word line group (Fig. 9: BLK2).
Futatsuyama teaches floating unselected word lines during a program operation (Fig. 8: WL3-WL5) of a non-volatile memory with two sub blocks.
Futatsuyama discloses that floating adjacent word lines is a method that can help reduce GIDL during programming and improve functionality without implementing structural changes to a NAND flash memory. It would therefore be useful to implement floating of adjacent word lines in the function of a NAND flash memory.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to apply the teachings of Futatsuyama and Park to the teachings of Yang to produce a memory with two word line groups and a dummy word line group between them. In which in during a program operation where a WL is selected in the first word line group, the unselected WL between the selected word line and dummy word line group are floated and the other unselected word lines are set to a first pass voltage. And the dummy word line group is set to second pass voltage. In addition to the other limitations taught by Yang.
Regarding Claim 2, Yang, Park, and Futatsuyama teach the limitations of Claim 1.
Park further teaches the first word line group (Fig. 9: BLK1) is adjacent to a source line (Fig. 9: CSL), and the second word line group (Fig. 9: BLK2) is adjacent to bit lines (Fig. 9: BL).
Regarding Claim 3, Yang, Park, and Futatsuyama teach the limitations of Claim 2.
Park further teaches a second dummy line group (Fig. 9: WLd3) disposed between the first word line group (Fig. 9: BLK1) and the source line (Fig. 9: CSL); and
a third dummy line group (Fig. 9: WLd4) disposed between the second word line group (Fig. 9: BLK2) and the bit lines (Fig. 9: BL).
Regarding Claim 4, Yang, Park, and Futatsuyama teach the limitations of Claim 3.
Yang further teaches wherein the peripheral circuit (Fig. 2A: 220, 210) is configured to, when the program voltage is applied to the selected word line included in the first word line group, apply a third pass voltage (Fig. 12: Vpass3) lower than the first pass voltage to the second (Fig. 12: DD) and third (Fig. 12: DDS) dummy line groups.
Regarding Independent Claim 8, Yang, Park, and Futatsuyama teach the limitations of this claim. Independent Claim 8 is rejected for the same reasons as independent claim 1.
Claims 5-6, 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 20240055051), Park et al (US 20080007999), and Futatsuyama et al (US 20070025152 A1) in view of Zhang (US 9887002).
Regarding Claim 5, Yang, Park, and Futatsuyama teach the limitations of claim 4.
However, they fail to teach applying a pass voltage to the second and third dummy word line groups.
Zhang teaches the peripheral circuit (Fig. 2A: 110, 124, 132, 128) is configured to, before (Fig. 1C: T2) the program voltage (Fig. 1C: Vpgm, T5) is applied to the selected word line (Fig. 1C: WLsel) included in the first word line group, apply the third pass voltage (Fig. 1C: Vd1, Vd0) to the second (Fig. 5A: WLD3, WLD4) and third (Fig. 5A: WLD2, WLD1) dummy line groups.
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Zhang to the teachings of Yang, Park and Futatsuyama to produce a memory device where a third pass voltage is applied to the second and third dummy word line groups before the program voltage is applied to the selected word line.
Regarding Claim 6, Yang, Park, and Futatsuyama teach the limitations of claim 1.
However, they fail to teach applying a pass voltage to unselected word lines before the program voltage is applied.
Zhang teaches the peripheral circuit (Fig. 2A: 110, 124, 132, 128) is configured to, before (Fig. 1C: T2) the program voltage (Fig. 1C: Vpgm, T5) is applied to the selected word line (Fig. 1C: WLsel) included in the first word line group, apply the first pass voltage (Fig. 1C: Vpass) to unselected word lines (Fig.1C: WLunsel) and to the selected word line (Fig. 1C: WLsel, T3, T4).
Regarding Claim 10, Yang, Park, and Futatsuyama teach the limitations of Claim 8. Claim 10 is rejected for the same reasons as claim 6.
Regarding Claim 11, Yang, Park, and Futatsuyama teach the limitations of Claim 8. Claim 10 is rejected for the same reasons as claim 5.
Claims 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 20240055051), Park et al (US 20080007999), and Futatsuyama et al (US 20070025152 A1) in view of Kang et al (US 20090180317).
Regarding Claim 7, Yang, Park, and Futatsuyama teach the limitations of Claim 1.
However, they fail to teach decreasing the voltage of an unselected word line adjacent to a first dummy word line group during the program operation.
Kang teaches decreasing the voltage (Fig. 13: VSS) of an unselected word line (Fig. 13: WL<N+1>) adjacent to a dummy word line (Fig. 13: DWL) group located between two word line groups (Fig. 13: ch1, ch2) during a program operation (Fig. 13: PGM).
If would have been obvious to one of ordinary skill in the art before the filing date of the claimed invention to apply the teachings of Kang to the teachings of Yang, Park, and Futatsuyama to produce a memory array where when a word line is selected from a first word line group, the voltage on a word line in a second word line group adjacent to a dummy word line group is reduced below the pass voltage.
Regarding Claim 9, Yang, Park, and Futatsuyama teach the limitations of Claim 8. Claim 9 is rejected for the same reasons as claim 7.
Claims 12-17, 21, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 20240055051) in view of Gangasani et al (US 20170117054).
Regarding Independent Claim 12, Yang teaches a memory device (Fig. 2: 200), comprising:
a memory block (Fig. 2A: 202) to which first (Fig. 4D: Upper sub-block) and second (Fig. 4D: Lower Sub-Block) word line groups are coupled, and to which a first dummy line group (Fig. 4D: WL_RC1-4; para 136) disposed between the first (Fig. 4D: Upper sub-block) and second (Fig. 4D: Lower Sub-Block) word line groups is coupled; and
a peripheral circuit (Fig. 2A: 220, 210) configured to program memory cells coupled to a selected word line of the first or second word line group,
wherein the peripheral circuit is configured to:
when the selected word line (Fig. 12: Selected WL, WL0) is included in the second word line group (Fig. 4D: Lower Sub-Block), during a program period in which a program voltage is applied (Fig. 12: Selected WL, WL0, VPGM), apply a first pass voltage (Fig. Selected WL, WL0, Vpass2) to unselected word lines included in the first (Fig. 12: WL1-WL_133) and second (Fig. 12: WL134-WL_267) word line groups and to dummy lines (Fig. 12: WL_RC1-WL_RC4, para 136) included in the first dummy line group, and
Yang further teaches when the selected word line is included in the first word line group (Fig. 4D: Upper sub-block), during the program period in which a program voltage is applied (Fig. 12: Selected WL, WL134, VPGM), applying a first pass voltage (Fig. 12: Vpass2) to the unselected WL of the second group (Fig. 12: WL134-WL_267) and multiple pass voltages (Fig. 12: Vpass1-Vpass3), which can be applied to the dummy word lines (Fig. 12: WL_RC1-WL_RC4, para 136).
However, Yang does not teach applying apply compensation voltages higher than the first pass voltage to first unselected word lines disposed between the selected word line and the first dummy line group, when a word line in the first group of word lines is selected.
Gangasani teaches a method of applying linearly increasing or decreasing voltages (Fig. 18: 137, Linear voltages) to word lines along a string of non-volatile memory cells for the purposes of programming (para 6).
It would therefore have been obvious to one of ordinary skill in the art before the filing date of the claimed invention to apply the teachings of Gangasani to the teachings of Yang to produce a non-volatile memory devices. Where stings of memory cells are divided into a first and second group of word lines with a third group of dummy word lines between. And that when a word line in the first group is selected, the unselected word lines between the selected word line and the dummy cell array have compensation voltages applied to them higher than the first pass voltage, which is applied to the other unselected word lines.
Regarding Claim 13, Yang and Gangasani teach the limitations of claim 12.
Gangasani further teaches wherein the peripheral circuit (Fig. 18: 137) is configured to control levels of the compensation voltages (Fig. 18: Linear Voltages) depending on distances between the selected word line and the first unselected word lines (para 111).
Regarding Claim 14, Yang and Gangasani teach the limitations of claim 12.
Gangasani further teaches wherein the peripheral circuit (Fig. 18: 137) is configured to set the compensation voltages (Fig. 18: Linear Voltages) to higher voltages as distances between the selected word line and the first unselected word lines become shorter (para 111).
Regarding Claim 15, Yang and Gangasani teach the limitations of claim 12.
Gangasani further teaches wherein the peripheral circuit (Fig. 18: 136 137) is configured to set levels of the compensation voltages to levels (Fig. 18: Linear Voltages) lower than that of the program voltage (para 111).
Regarding Claim 16, Yang and Gangasani teach the limitations of claim 12.
Yang further teaches a second dummy line group (Fig. 4D: DDS) disposed between the first word line group (Fig. 4D: Lower Sub-Block) and the source line (Fig. 4D: SL); and a third dummy line group (Fig. 4D: Upper Sub-Block) disposed between the second word line group and the bit lines (Fig. 4D: BL).
Regarding Claim 17, Yang and Gangasani teach the limitations of claim 16.
Yang teaches wherein the peripheral circuit (Fig. 2A: 220, 210) is configured to, when the program voltage (Fig. 12: Vpgm) is applied to the selected word line included in the first word line group (WL0-WL_133), apply a third pass voltage (Fig. 12: VSG_P) lower than the first pass voltage to the second (Fig. 12: DD) and third (Fig. 12: DDS) dummy line groups
Regarding Independent Claim 21, Yang and Gangasani teach the limitations of this claim. Independent Claim 21 is rejected for the same reasons as independent claim 12.
Regarding Claim 24, Yang and Gangasani teach the limitations of claim 16.
Claim 24 is rejected for the same reasons as Claim 17.
Claims 18-19 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 20240055051) and Gangasani et al (US 20170117054) in view of Zhang (US 9887002).
Regarding Claim 18, Yang and Gangasani teach the limitations of claim 17.
Zhang teaches the peripheral circuit (Fig. 2A: 110, 124, 132, 128) is configured to, before (Fig. 1C: T2) the program voltage (Fig. 1C: Vpgm, T5) is applied to the selected word line (Fig. 1C: WLsel) included in the first word line group, apply the third pass voltage (Fig. 1C: Vd1, Vd0) to the second (Fig. 5A: WLD3, WLD4) and third (Fig. 5A: WLD2, WLD1) dummy line groups.
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Zhang to the teachings of Yang and Gangasani to produce a memory device where a third pass voltage is applied to the second and third dummy word line groups before the program voltage is applied to the selected word line.
Regarding Claim 19, Yang and Gangasani teach the limitations of claim 12.
Zhang teaches the peripheral circuit (Fig. 2A: 110, 124, 132, 128) is configured to, before (Fig. 1C: T2) the program voltage (Fig. 1C: Vpgm, T5) is applied to the selected word line (Fig. 1C: WLsel) included in the first word line group, apply the first pass voltage (Fig. 1C: Vpass) to unselected word lines (Fig.1C: WLunsel) and to the selected word line (Fig. 1C: WLsel, T3, T4).
Regarding Claim 23, Yang and Gangasani teach the limitations of claim 21. Claim 23 is rejected for the same reasons as claim 19.
Claims 20 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 20240055051) and Gangasani et al (US 20170117054) in view of Kang et al (US 20090180317).
Regarding Claim 20, Yang and Gangasani teach the limitations of Claim 12.
However, they fail to teach decreasing the voltage of an unselected word line adjacent to a first dummy word line group during the program operation.
Kang teaches decreasing the voltage (Fig. 13: VSS) of an unselected word line (Fig. 13: WL<N+1>) adjacent to a dummy word line (Fig. 13: DWL) group located between two word line groups (Fig. 13: ch1, ch2) during a program operation (Fig. 13: PGM).
If would have been obvious to one of ordinary skill in the art before the filing date of the claimed invention to apply the teachings of Kang to the teachings of Yang and Park to produce a memory array where when a word line is selected from a first word line group, the voltage on a word line in a second word line group adjacent to a dummy word line group is reduced below the pass voltage.
Regarding Claim 22, Yang and Gangasani teach the limitations of Claim 21. Claim 22 is rejected for the same reasons as claim 20.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 8 has been considered but are moot because the new grounds of rejection.
Applicant’s arguments with respect to independent Claims 12 and 21 seem to have primarily to do with Yang and Gangassani failing to disclose every feature of the claims. However, In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Further both Yang and Gangassani disclose applying voltages to word lines during program periods.
Conclusion
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/JOSEPH FIDELIS STORMES/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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