DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-9, 11-16, and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Number 7,937,563 to Naffziger et al. (“Naffziger”).
In reference to Claim 1, Naffziger discloses an apparatus comprising: circuitry configured to: generate two or more estimated power-consumption values based on a plurality of instructions that have not yet issued (See Figure 4 Numbers 402, 406, and 408, Column 5 Lines 47-49, Column 6 Line 29 – Column 8 Line 43, and Column 9 Lines 12-35 [instructions are picked prior to issue; power consumption values are generated prior to scheduling and issuance, and throttling based on the values is done by throttling issuance]); and store the estimated power-consumption values (See Figure 3B Number 340, Figure 4 Number 410, and Column 8 Lines 9-30); and change a rate at which the instructions are executed by instruction execution resources (See Figure 4 Number 418 and Column 8 Lines 44-63) in response to occurrence of either one of the following conditions: an increase in the estimated power-consumption values that satisfies a first threshold condition corresponding to an undershoot condition (See Figure 4 Numbers 414 and 416 and Column 8 Lines 31-43 [undershoot caused by voltage droop due to increased power-consumption values]); or a decrease in the estimated power-consumption values that satisfies a second threshold condition corresponding to an overshoot condition. For the purposes of evaluating prior art with respect to patentability, the Examiner has interpreted an “overshoot condition” in accordance with Applicant’s explicit definition (See Paragraph 3) and arguments filed 5 June 2026 (See Page 8 Paragraph 4); an “undershoot condition” in accordance with Applicant’s explicit definition (See Paragraph 2) and arguments filed 5 June 2026 (See Page 8 Paragraph 4); and has interpreted an “overshoot condition” as occurring when there is negative voltage droop and an “undershoot condition” as occurring when there is positive voltage droop (See Paragraph 3).
In reference to Claim 2, Naffziger discloses the limitations as applied to Claim 1 above. Naffziger further discloses that the circuitry is further configured to generate control information that indicates when to begin the change in the rate of execution (See Column 7 Lines 52-61 and Column 8 Lines 44-63 [control information indicates that the change occurs in a corresponding clock cycle]).
In reference to Claim 4, Naffziger discloses the limitations as applied to Claim 1 above. Naffziger further discloses that the estimated power-consumption values corresponds to a first stage of a plurality of execution pipelines, and the change in rate of execution corresponds to a second stage later than the first stage (See Column 9 Lines 41-49).
In reference to Claim 5, Naffziger discloses the limitations as applied to Claim 2 above. Naffziger further discloses that the circuitry is further configured to insert in the control information an identification of instructions classified as corresponding to a given type (See Column 7 Lines 52-61 and Column 9 Lines 12-30).
In reference to Claim 6, Naffziger discloses the limitations as applied to Claim 2 above. Naffziger further discloses that the circuitry is further configured to classify a given instruction of the one or more instructions as corresponding to a given type, prior to issuance of the given instruction, the given type corresponding to a power category used to generate the estimated power-consumption values (See Column 5 Lines 47-49, Column 7 Lines 52-61, and Column 9 Lines 12-30).
In reference to Claim 7, Naffziger discloses the limitations as applied to Claim 2 above. Naffziger further discloses that the circuitry is further configured to insert, in the control information, an identification of one or more of a plurality of power bins that the given instruction was assigned to during the generation of the estimated power-consumption values (See Column 7 Lines 52-61 and Column 9 Lines 12-30).
In reference to Claim 8, Naffziger discloses a method comprising: generating, by circuitry, two or more estimated power-consumption values based on a plurality of instructions that have not yet issued (See Figure 4 Numbers 402, 406, and 408, Column 5 Lines 47-49, Column 6 Line 29 – Column 8 Line 43, and Column 9 Lines 12-35 [instructions are picked prior to issue; power consumption values are generated prior to scheduling and issuance, and throttling based on the values is done by throttling issuance]); storing the estimated power-consumption values (See Figure 3B Number 340, Figure 4 Number 410, and Column 8 Lines 9-30); and changing, by the circuitry, a rate at which the instructions are executed by instruction execution resources (See Figure 4 Number 418 and Column 8 Lines 44-63) in response to occurrence of either one of the following conditions: an increase in the estimated power-consumption values that satisfies a first threshold condition corresponding to an undershoot condition (See Figure 4 Numbers 414 and 416 and Column 8 Lines 31-43 [undershoot caused by voltage droop due to increased power-consumption values]); or a decrease in the estimated power-consumption values that satisfies a second threshold condition corresponding to an overshoot condition. For the purposes of evaluating prior art with respect to patentability, the Examiner has interpreted an “overshoot condition” in accordance with Applicant’s explicit definition (See Paragraph 3) and arguments filed 5 June 2026 (See Page 8 Paragraph 4); an “undershoot condition” in accordance with Applicant’s explicit definition (See Paragraph 2) and arguments filed 5 June 2026 (See Page 8 Paragraph 4); and has interpreted an “overshoot condition” as occurring when there is negative voltage droop and an “undershoot condition” as occurring when there is positive voltage droop (See Paragraph 3).
In reference to Claim 9, Naffziger discloses the limitations as applied to Claim 8 above. Naffziger further discloses generating control information that indicates when to begin the change in the rate of execution (See Column 7 Lines 52-61 and Column 8 Lines 44-63 [control information indicates that the change occurs in a corresponding clock cycle])
In reference to Claim 11, Naffziger discloses the limitations as applied to Claim 9 above. Naffziger further discloses that the estimated power-consumption values corresponds to a first stage of a plurality of execution pipelines, and the change in rate of execution corresponds to a second stage later than the first stage (See Column 9 Lines 41-49).
In reference to Claim 12, Naffziger discloses the limitations as applied to Claim 9 above. Naffziger further discloses inserting, in the control information, an identification of instructions classified as corresponding to a given type (See Column 7 Lines 52-61 and Column 9 Lines 12-30).
In reference to Claim 13, Naffziger discloses the limitations as applied to Claim 9 above. Naffziger further discloses classifying a given instruction of the one or more instructions as corresponding to a given type, prior to issuance of the given instruction, the given type corresponding to a power category used to generate the estimated power-consumption values (See Column 5 Lines 47-49, Column 7 Lines 52-61, and Column 9 Lines 12-30).
In reference to Claim 14, Naffziger discloses the limitations as applied to Claim 13 above. Naffziger further discloses that the circuitry is further configured to inserting, in the control information, an identification of one or more of a plurality of power bins that the given instruction was assigned to during the generation of the estimated power-consumption values (See Column 7 Lines 52-61 and Column 9 Lines 12-30).
In reference to Claim 15, Naffziger discloses a computing system comprising: a plurality of chiplets (See Column 1 Lines 13-18, Column 8 Line 64 – Column 9 Line 11, and Column 9 Lines 39-41 [processor cores]); each comprising a plurality of execution pipelines (See Column 1 Lines 13-18); and a processor configured to assign workloads to the plurality of chiplets (See Column 1 Lines 13-18, Column 8 Line 64 – Column 9 Line 11, and Column 9 Lines 39-41 [multi-core processors necessarily require some sort of processing element to coordinate operations and assign workloads to a particular core]); and wherein circuitry of a given chiplet of the plurality of chiplets is configured to: generate, prior to issuance, predicted power-consumption information for a plurality of upcoming instructions, the predicted power-consumption information comprising estimated power-consumption values representing power consumption of the upcoming instructions (See Figure 4 Numbers 402, 406, and 408 and Column 6 Line 29 – Column 8 Line 30) at a first stage of each of the plurality of execution pipelines (See Column 9 Lines 41-49); store the estimated power-consumption values (See Figure 3B Number 340, Figure 4 Number 410, and Column 8 Lines 9-30); and change a rate of instruction execution of at least one execution pipeline of the plurality of execution pipelines at a second stage of the at least one execution pipeline later than the first stage (See Figure 4 Number 418, Column 8 Lines 44-63, and Column 9 Lines 41-49) in response to a difference between at least two of the estimated power consumption values exceeding a threshold (See Figure 4 Numbers 414 and 416 and Column 8 Lines 31-43).
In reference to Claim 16, Naffziger discloses the limitations as applied to Claim 15 above. Naffziger further discloses that the circuitry is further configured to generate control information that indicates when to begin the change in the rate of execution (See Column 7 Lines 52-61 and Column 8 Lines 44-63 [control information indicates that the change occurs in a corresponding clock cycle]).
In reference to Claim 18, Naffziger discloses the limitations as applied to Claim 16 above. Naffziger further discloses that the circuitry is further configured to determine a rate of instruction execution to insert in the control information based on operating parameters of the plurality of chiplets (See Column 8 Lines 44-63).
In reference to Claim 19, Naffziger discloses the limitations as applied to Claim 16 above. Naffziger further discloses that the circuitry is further configured to insert in the control information an identification of instructions classified as corresponding to a given type (See Column 7 Lines 52-61 and Column 9 Lines 12-30).
In reference to Claim 20, Naffziger discloses the limitations as applied to Claim 2 above. Naffziger further discloses that the circuitry is further configured to classify a given instruction as corresponding to a power bin of a plurality of power bins, wherein the power bin indicates an amount of power consumed by the plurality of chiplets when the plurality of execution pipelines executes the given instruction (See Column 7 Lines 52-61 and Column 9 Lines 12-30).
Allowable Subject Matter
Claim(s) 3, 10, and 17 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to disclose, either alone or in combination, all of the claimed limitations in the combinations as claimed. The most relevant prior art reference is Naffziger as applied in the above rejections. Naffziger further discloses that the circuitry is configured to generate control information that indicates when to begin the change in the rate of execution (See Column 8 Lines 44-63). However, Naffziger discloses that the rate of instruction execution is changed only for a corresponding clock cycle (See Colum 8 Lines 35-39). Naffziger further discloses that the control information is a simple output from a comparator having either an asserted or deasserted value (See Column 8 Lines 44-63) as well as a signal containing various identifiers and weights for the instructions (See Column 7 Lines 52-61). However, Naffziger does not explicitly disclose that the circuitry is further configured to: determine a duration of time for changing the rate of instruction execution of the instruction execution resources; and insert the duration of time in the control information. As the rate change of Naffziger is only for a corresponding clock cycle, the apparatus is already aware of the start, stop, and duration of the rate change. Furthermore, the control information has no capability on its own of carrying further information such as duration. Thus, one of ordinary skill in the art would not have been motivated to insert a determined duration of time for changing the rate of instruction execution of the instruction execution resources in the control information of Naffziger, as doing so would involve considerable additional complexity to utilize a more complex control information to provide information that is already known, and thus provides no enhancement or improvement to the Naffziger.
Response to Arguments
Applicant's arguments filed 5 June 2026 have been fully considered but they are not persuasive.
Applicant has argued that Naffziger does not disclose a rate change response to an estimated decrease in predicted power consumption, from at least two estimated power consumption values, satisfying a threshold condition corresponding to an overshoot condition (See Page 8). In response, the Examiner notes that the claims recite the rate change responses in the alternative. Specifically, Claim recites “change a rate at which the instructions are executed by instruction execution resources in response to occurrence of either one of the following conditions: an increase in the estimated power-consumption values that satisfies a first threshold condition corresponding to an undershoot condition; or a decrease in the estimated power-consumption values that satisfies a second threshold condition corresponding to an overshoot condition” [emphasis added]. Claim 8 recites substantially equivalent language. Thus, the prior art only needs to disclose one of the alternatives in order to reject the claim. As indicated in the above rejections, Naffziger discloses changing a rate at which the instructions are executed by instruction execution resources (See Figure 4 Number 418 and Column 8 Lines 44-63) in response to occurrence of an increase in the estimated power-consumption values that satisfies a first threshold condition corresponding to an undershoot condition (See Figure 4 Numbers 414 and 416 and Column 8 Lines 31-43 [undershoot caused by voltage droop due to increased power-consumption values]). The Examiner notes that Applicant has admitted that Naffziger discloses throttling based on activity or current-consumption behavior associated with voltage droop (See Page 8 Paragraph 2).
Applicant has argued that Naffziger does not disclose a plurality of chiplets (See Page 9 Paragraph 2). In response, the Examiner notes that Naffziger discloses that each processor core may be “any IC” or “an ASIC or other semiconductor chip” (See Column 9 Lines 8-11). Applicant has disclosed that a "chiplet" is a semiconductor die (or die) fabricated separately from other dies, and then interconnected with these other dies in a single integrated circuit (See Paragraph 80), and thus the separate ASIC processor cores of Naffziger are chiplets in accordance with Applicant’s definition.
Applicant has argued that Naffziger does not disclose a processor configured to assign workloads to a plurality of chiplets (See Page 9 Paragraph 2). In response, the Examiner notes that, as indicated in the above rejections, multi-core processors necessarily require some sort of element to coordinate operations and assign workloads to a particular core. As such an element is performing processing, it is a processor in accordance with the broadest reasonable interpretation of the term.
Applicant has argued that Naffziger does not disclose generating a total power consumption estimate at a first stage of each of a plurality of execution pipelines of a given chiplet and changing the rate of instruction execution at a second stage later than the first stage (See Page 9 Paragraph 3). In response, the Examiner notes that Naffziger discloses that the power consumption estimate is for an instruction at an earlier pipeline stage than the pipeline stage in which the rate of execution is changed (See Column 9 Lines 41-46).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS J CLEARY whose telephone number is (571)272-3624. The examiner can normally be reached Monday-Friday 8AM-5PM.
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/THOMAS J. CLEARY/Primary Examiner, Art Unit 2175
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