DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12 December 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 4 and 11 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation "the estimate" in Line 1. There is insufficient antecedent basis for this limitation in the claim. For the purposes of evaluating prior art with respect to patentability, the Examiner has interpreted “the estimate” as referring to the “estimated power consumption values representing power consumption of the upcoming instructions” of Claim 1.
Claim 11 recites the limitation "the estimate" in Line 1. There is insufficient antecedent basis for this limitation in the claim. For the purposes of evaluating prior art with respect to patentability, the Examiner has interpreted “the estimate” as referring to the “estimated power consumption values representing power consumption of the upcoming instructions” of Claim 8.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 8, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Number 7,937,563 to Naffziger et al. (“Naffziger”).
In reference to Claim 1, Naffziger discloses an apparatus comprising: circuitry configured to: generate, prior to issuance, predicted power-consumption information for a plurality of upcoming instructions, the predicted power-consumption information comprising estimated power-consumption values representing power consumption of the upcoming instructions (See Figure 4 Numbers 402, 406, and 408 and Column 6 Line 29 – Column 8 Line 30); and store the estimated power-consumption values (See Figure 3B Number 340, Figure 4 Number 410, and Column 8 Lines 9-30); and change a rate at which the instructions are executed by instruction execution resources (See Figure 4 Number 418 and Column 8 Lines 44-63) in response to a difference between at least two of the estimated power consumption values exceeding a threshold (See Figure 4 Numbers 414 and 416 and Column 8 Lines 31-43).
In reference to Claim 4, Naffziger discloses the limitations as applied to Claim 1 above. Naffziger further discloses that the estimate corresponds to a first stage of a plurality of execution pipelines, and the change in rate of execution corresponds to a second stage later than the first stage (See Column 9 Lines 41-49).
In reference to Claim 8, Naffziger discloses a method comprising: circuitry generating, prior to issuance, predicted power-consumption information for a plurality of upcoming instructions, the predicted power-consumption information comprising estimated power-consumption values representing power consumption of the upcoming instructions (See Figure 4 Numbers 402, 406, and 408 and Column 6 Line 29 – Column 8 Line 30); and storing the estimated power-consumption values (See Figure 3B Number 340, Figure 4 Number 410, and Column 8 Lines 9-30); and changing a rate at which the instructions are executed by instruction execution resources (See Figure 4 Number 418 and Column 8 Lines 44-63) in response to a difference between at least two of the estimated power consumption values exceeding a threshold (See Figure 4 Numbers 414 and 416 and Column 8 Lines 31-43).
In reference to Claim 15, Naffziger discloses a computing system comprising: a plurality of chiplets (See Column 1 Lines 13-18, Column 8 Line 64 – Column 9 Line 11, and Column 9 Lines 39-41 [processor cores]); each comprising a plurality of execution pipelines (See Column 1 Lines 13-18); and a processor configured to assign workloads to the plurality of chiplets (See Column 1 Lines 13-18, Column 8 Line 64 – Column 9 Line 11, and Column 9 Lines 39-41 [multi-core processors necessarily require some sort of processing element to coordinate operations and assign workloads to a particular core]); and wherein circuitry of a given chiplet of the plurality of chiplets is configured to: generate, prior to issuance, predicted power-consumption information for a plurality of upcoming instructions, the predicted power-consumption information comprising estimated power-consumption values representing power consumption of the upcoming instructions (See Figure 4 Numbers 402, 406, and 408 and Column 6 Line 29 – Column 8 Line 30); and store the estimated power-consumption values (See Figure 3B Number 340, Figure 4 Number 410, and Column 8 Lines 9-30); and change a rate at which the instructions are executed by instruction execution resources (See Figure 4 Number 418 and Column 8 Lines 44-63) in response to a difference between at least two of the estimated power consumption values exceeding a threshold (See Figure 4 Numbers 414 and 416 and Column 8 Lines 31-43).
Allowable Subject Matter
Claim(s) 2-3, 5-7, 9-10, and 12-20 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim(s) 4 and 11 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to disclose, either alone or in combination, all of the claimed limitations in the combinations as claimed. The most relevant prior art reference is Naffziger as applied in the above rejections. Naffziger further discloses that the circuitry is configured to generate control information, based at least in part on the difference, to direct the rate of instruction execution of the instruction execution resources (See Column 8 Lines 44-63). However, Naffziger discloses that the rate of instruction execution is changed only for a corresponding clock cycle (See ). Naffziger further discloses that the control information is a simple output from a comparator having either an asserted or deasserted value (See). However, Naffziger does not explicitly disclose that the control information comprises a start time that indicates when to begin the change in the rate of execution. As the rate change of Naffziger is only for a corresponding clock cycle, the apparatus is already aware of the start, stop, and duration of the rate change. Furthermore, as the control information is a simple asserted/deasserted value, it has no capability on its own of carrying further information. Thus one of ordinary skill in the art would not have been motivated to include start information in the control information of Naffziger, as doing so would involve considerable additional complexity to utilize a more complex control information to provide information that is already known, and thus provides no enhancement to the apparatus.
Response to Arguments
Applicant’s arguments with respect to Claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS J CLEARY whose telephone number is (571)272-3624. The examiner can normally be reached Monday-Friday 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THOMAS J. CLEARY/Primary Examiner, Art Unit 2175