DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2 and 8 – 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kumagai et al. (US 2015/0108611).
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( Claim 1) Kumagai et al. teach an apparatus comprising:
an integrated circuit device, the integrated circuit device comprising:
a first layer (M4/M5) with an area comprising metallization (shaded) and metal-free slits (non-shaded between shaded); and
a fiducial (3, alignment marker, paragraph 107) in a second layer (La) above the first layer (M5),
the fiducial (3) formed over the area comprising the metallization and metal-free slits.
(Claim 2) Kumagai et al. teach wherein the metal-free slits are parallel to each other (fig. 3).
(Claim 8) Kumagai et al. teach wherein the fiducial (fig. 5 #3) has an annular shape.
(Claim 9) Kumagai et al. teach wherein a width of the fiducial (fig. 5 #3) is greater than a width of a strip (fig. 5 #5) of the metallization.
(Claim 10) Kumagai et al. teach wherein the first layer is a bonding layer of the integrated circuit device (#27, paragraph 119).
(Claim 11) Kumagai et al. teach wherein the second layer is a metal interconnect layer of the integrated circuit device (#La, paragraph 112).
Claims 1, 3, 12 – 14 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Niazi et al. (US 2024/0063136).
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( Claim 1) Niazi et al. teach an apparatus (figs. 1, 2) comprising:
an integrated circuit device, the integrated circuit device comprising:
a first layer (fig.2 #212) with an area comprising metallization and metal-free slits (112); and
a fiducial (108) in a second layer above the first layer,
the fiducial (fig. 1 #108) formed over the area comprising the metallization (104) and metal-free slits (112).
(Claim 3) Niazi et al. teach wherein the metal-free slits have a common pitch between adjacent metal-free slits (paragraph 53).
(Claim 12) Niazi et al. teach the apparatus, further comprising a printed circuit board (fig. 16 #1604, paragraph 37) attached to the first integrated circuit device (1602).
(Claim 13) Niazi et al. teach the apparatus, further comprising a second integrated circuit device (1603) coupled to the printed circuit board (1604).
(Claim 14) Niazi et al. teach a system (fig. 15) comprising:
a printed circuit board (1504, paragraph 37); and
a package (1902) coupled to the printed circuit board, the package comprising a first integrated circuit device comprising:
dummy metallization (1924 paragraph 155, analogous to fig. 1 #104) on a first layer and metal-free slits (fig. 1 #112) between segments of the dummy metallization; and
a fiducial (1514, 1512, figs. 1, 2 #108) on a second layer (fig. 2 #212), wherein the fiducial is within a footprint of the metal- free slits (figs. 1, 2, #112).
(Claim 18) Niazi et al. teach an apparatus comprising:
a plurality of metal lines (fig. 1 #104) defining a plurality of metal-free slits (112) on a layer of an integrated circuit device; and
a fiducial (figs. 1, 2 #108) formed within a footprint of the plurality of metal-free slits (112) on a second layer (fig. 2 #212) of the integrated circuit device.
Allowable Subject Matter
Claims 4 – 7, 15 – 17 and 19 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
(Claim 4) a second fiducial formed in a fourth layer different from the third layer, the second fiducial formed within a footprint of the second metallization and second metal-free slits.
(Claim 15) a second fiducial on a fourth layer, wherein the second fiducial is within a footprint of the second metal-free slits.
(Claim 19) a second fiducial formed within a footprint of the second plurality of metal-free slits on a fourth layer of the second integrated circuit device,
wherein the second plurality of metal-free slits are orthogonal to the plurality of metal-free slits.
Conclusion
Prior art made of record and not relied upon, considered pertinent to applicant's disclosure are listed in PTO – 892 Form.
Contact Information
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/IGWE U ANYA/Primary Examiner, Art Unit 2891
August 8, 2026
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