Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/01/2024 and 07/27/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-5 and 11-14 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
In regards to claims 2 and 11, the limitation “the second instruction having a pointer tag value based on the relative enumeration in the pointer” renders the claim indefinite due to its ambiguity. Specifically it is unclear what is required by the second instruction “having” the pointer tag value as the language permits two different interpretations 1) the pointer tag value is encoded in or otherwise associated with the second instruction (e.g. the value must be present in or associated with the instruction) or 2) execution of the second instruction generates an output pointer having a pointer tag value based on the relative enumeration in an input pointer (e.g. the value is generated through execution of the instruction and resides in a resulting pointer) and the specification fails to resolve the ambiguity. Accordingly, it cannot be determine with reasonable certainty whether an instruction falls within the scope of the claim because it contains or is associated with a pointer tag value, execution of the instruction generates a pointer tag value or if the instruction operates on a pointer already containing the value. For the purpose of examination the examiner interprets the limitation to mean execution of the second instruction generates or provides a resulting pointer having the pointer tag value.
Dependent claims depending from a rejected base claim are rejected for failing to overcome the rejection from which they depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 9-11 and 18 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US 20210026772 A1 to Shen et al. (hereinafter “Shen”)
Claim 1
Shen teaches a processor device [e.g. Shen; Para. 0029 – Shen disclose data processing apparatus.] comprising:
an instruction decoder to decode a first instruction having an instruction tag value; [e.g. Shen; Para. 0039, 0076, 0077 – Shen discloses recognizing and executing an ADDG or SUBG instruction (e.g. first instruction), determining the operation, source register field destination register field, address offset field and tag offset 26 (e.g. instruction tag value) specified by the instruction. As ADDG and SUBG are two different instructions, the processing device necessarily includes instruction decoding logic (e.g. instruction decoder) that the decodes the instructions before execution).] and
execution circuitry coupled to the instruction decoder, the execution circuitry to perform one or more operations corresponding to the first instruction, [e.g. Shen; Para. 0076-0079 – Shen disclose add or subtract operation 23 and tag selection logic 28 (e.g. execution circuitry) receiving the source address, address offset and tag offset specified by the decoded ADDG or SUB instruction (e.g. coupled to the instruction decoder) and performing the corresponding address arithmetic and tag selection operation (e.g. one or more operations corresponding to the first instruction).]
including generating a first data tag value based on the instruction tag value and a relative enumeration in a pointer to data. [e.g. Shen; Para. 0041, 0045, 0076-0078 – Shen discloses tag selection logic 28 obtains start tag 25 from start address 21 (e.g. relative enumeration in a pointer to data) receives instruction specified tag offset 26 (e.g. instruction tag value) and generates modified tag rtag 29 (e.g. first data tag value) using ChooseNonExcludedTag(start tag, tag offset, GCR_EL1.Exclude) (e.g. based on the instruction tag value and the relative enumeration).]
Claim 2
Shen teaches the processor device of claim 1, wherein the instruction decoder is also to decode a second instruction, the second instruction having a pointer tag value based on the relative enumeration in the pointer. [e.g. Shen; Para. 0039, 0076-0078– Shen the processing device recognizing, decoding and executing a further ADDG or SUBG instruction (e.g. second instruction) including obtaining the operation and operand fields specified by the further instruction. Shen further discloses obtaining start tag from source address (e.g. relative enumeration in the pointer) generating rtag from start tag and tag offset and inserting rtag into resulting address 24 using AddressWithAllocationTag(result, rtag) (e.g. pointer tag value based on the relative enumeration in the pointer).]
Claim 9
Shen teaches the processor device of claim 1, wherein the first data tag value is derived from a sum of the instruction tag value and the relative enumeration. [e.g. Shen; Para. 0077, 0078 – Shen disclose ChooseNonExcludedTag increments start tag (e.g. relative enumeration) according to the instruction specified tag offset (e.g. instruction tag value) to generate rtag (e.g. first data tag value derived from a sum of the instruction tag value and the relative enumeration) with further increments used to skip excluded tag values.]
Regarding claims 9-11 and 18 they are method claims essentially corresponding to the above recitations, and they are rejected, at least, for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over US 20210026772 A1 to Shen et al. (hereinafter “Shen”) in view of US 20170083255 to Chiricescu et al. (hereinafter “Chiricescu”)
Claim 3:
While Shen teaches the processor device of claim 2, Shen does not teach that the data corresponds to a member of an object.
However, Chiricescu teaches: “wherein the data corresponds to a member of an object” [e.g. Chiricescu; Para. 0017-0021, 0027-0029, 0040– Chiricescu discloses a structure or allocated memory chunk (e.g. object) contains multiple separately colored fields or subfields (e.g. members) and data is read from or written to a particular field using a pointer having the color assigned to that field (e.g. data corresponding to a member of an object.]
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to apply Chiricescu field specific tagging to Shen and in order to prevent unauthorized access beyond an individual field in order to provide field specific memory protection as disclosed in paragraphs 0017-0021 of Chiricescu..
Claim 4:
While Shen teaches the processor device of claim 3 and that the ADDG or SUBG instruction specifies tag offset 26 (e.g. instruction tag value) used to generate the resulting pointer, Shen does not teach that the instruction tag value is related to the member.
However, Chiricescu teaches: “the instruction tag value is related to the member” [e.g. Chiricescu; Para. 0020, 0021, 0040– Chiricescu discloses the compiler knows which structure field is being accessed (e.g. member) and supplies or inserts a pointer adjustment instruction having an adjustment selected according to that field (e.g. instruct tag value related to the member) to generate the correct field specific pointer color.]
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to apply Chiricescu field specific tagging to Shen and in order to prevent unauthorized access beyond an individual field in order to provide field specific memory protection as disclosed in paragraphs 0017-0021 of Chiricescu
Claim 5:
Shen and Chiricescu teaches the processor device of claim 3, wherein the pointer tag value is related to the object. [e.g. Shen; Para. 0076-0078 – Shen disclose rtag is inserted into resulting address 24 (e.g. pointer tag value).] [e.g. Chiricescu; Para. 0018, 0022– Chiricescu discloses a fresh color “c” is assigned to a new allocation (e.g. object) the pointer to the allocation is initialized with color “c” (e.g. pointer tag value related to the object) and derivative colors may identify individual fields within the allocation.]
Regarding claims 12-15 they are method claims essentially corresponding to the above recitations, and they are rejected, at least, for the same reasons.
Claims 6-8, 15-17, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 20210026772 A1 to Shen et al. (hereinafter “Shen”) in view of US 20220357875 to Bialek et al. (hereinafter “Bialek”)
Claim 6:
While Shen teaches the processor device of claim 1, including generating a tag in response to an instruction Shen does not teach one or more operations also include identifying a memory location of a second data tag value associated with the data.
However, Bialek teaches: “one or more operations also include identifying a memory location of a second data tag value associated with the data” [e.g. Bialek; Para. 0017, 0023, 0024, 0030, 0034, 0039– Bialek discloses processing circuitry 112 executes instructions implementing memory write operation 110 (e.g. operations corresponding to a memory access instruction) computing where in bitmap 116 the tag corresponding to a head address being written is stored (e.g. identifying a memory location of a second data tag value) and identifying tag value 332A corresponding to the first address affected by the memory write operation (e.g. second data tag value associated with the data).]
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to further configure Shen’s execution circuitry such that execution for the ADDG or SUBG instruction also identifies the bitmap location of the tag associated with the addressed data as taught by Bialek in order to verify memory access and provide buffer overflow protection as disclosed by Bialek in paragraphs 0020, 0023 and 0034.
Claim 7:
While Shen teaches the processor device of claim 6, including generating a tag in response to an instruction Shen does not teach the one or more operations also include comparing the second data tag value to the first data tag value.
However, Bialek teaches: “the one or more operations also include comparing the second data tag value to the first data tag value” [e.g. Bialek 0020 – Bialek discloses during a memory access that the CPU verifies the tag is encoded in the address pointer (e.g. first data tag value) matches the tag stored in the bitmap for the addressed allocation (e.g. second data tag value) thus comparing the second data tag value to the first data tag value.]
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to further configure Shen’s execution circuitry such that execution for the ADDG or SUBG instruction also compares tag values as taught by Bialek in order to verify memory access and provide buffer overflow protection as disclosed by Bialek in paragraphs 0020, 0023 and 0034.
Claim 8:
While Shen teaches the processor device of claim 1, including generating a tag in response to an instruction Shen does not teach the one or more operations also include blocking access to the data in response to detecting a mismatch between the second data tag value and the first data tag value.
However, Bialek teaches: “the one or more operations also include blocking access to the data in response to detecting a mismatch between the second data tag value and the first data tag value” [e.g. Bialek 0020, 0034, 0039 – Bialek discloses when the tag encoded in the address pointer (e.g. first data tag value) done mot match the tag stored in the bitmap for the addressed allocation (e.g. second data tag value) the process throws an exception (e.g. detecting a mismatch) and processing circuity 112 or runtime environment 104 halts, pauses or terminates execution to prevent the overflowing write operation from completing (e.g. blocking access to the data in response to detecting the mismatch)]
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to further configure Shen’s execution circuitry such that execution for the ADDG or SUBG instruction also blocks mismatched tag values as taught by Bialek in order to verify memory access and provide buffer overflow protection as disclosed by Bialek in paragraphs 0020, 0023 and 0034.
Claim 19
Shen teaches a method comprising:
decoding, by an instruction decoder of a processing device, a first instruction having an instruction tag value; [e.g. Shen; Para. 0039, 0076, 0077 – Shen discloses recognizing and executing an ADDG or SUBG instruction (e.g. first instruction), determining the operation, source register field destination register field, address offset field and tag offset 26 (e.g. instruction tag value) specified by the instruction. As ADDG and SUBG are two different instructions, the processing device necessarily includes instruction decoding logic (e.g. instruction decoder) that the decodes the instructions before execution).] and
performing, by execution circuitry coupled to the instruction decoder, one or more operations corresponding to the first instruction, , [e.g. Shen; Para. 0076-0079 – Shen disclose add or subtract operation 23 and tag selection logic 28 (e.g. execution circuitry) receiving the source address, address offset and tag offset specified by the decoded ADDG or SUB instruction (e.g. coupled to the instruction decoder) and performing the corresponding address arithmetic and tag selection operation (e.g. one or more operations corresponding to the first instruction).]
including generating a first data tag value based on the instruction tag value and a relative enumeration in a pointer to data. [e.g. Shen; Para. 0041, 0045, 0076-0078 – Shen discloses tag selection logic 28 obtains start tag 25 from start address 21 (e.g. relative enumeration in a pointer to data) receives instruction specified tag offset 26 (e.g. instruction tag value) and generates modified tag rtag 29 (e.g. first data tag value) using ChooseNonExcludedTag(start tag, tag offset, GCR_EL1.Exclude) (e.g. based on the instruction tag value and the relative enumeration).]
While Shen teaches the operations of claim 19, but fail to teach storing instructions implementing those operations on a non-transitory machine-readable medium.
However, Bialek teaches: “A non-transitory machine-readable medium storing at least a single instruction which, when executed by a machine, causes the machine to perform a method comprising” [e.g. Bialek; Para. 0043-0047, 0059, claim 19– Bialek discloses a non-transitory machine readable medium storing computer-executable instructions that when executed by processing unit 702 causes machine 700 to perform software memory tagging operations.]
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to store Shen’s tag generation operation instructions on the non-transitory machine-readable medium as taught by Bialek in order to predictably cause a machine storing instructions to execute Shen tag generation operations via an old and well known technique.
Claim 20:
While Shen teaches the non-transitory machine-readable medium of claim 19, including generating a tag in response to an instruction Shen does not teach the one or more operations also include blocking access to the data in response to detecting a mismatch between the second data tag value and the first data tag value.
However, Bialek teaches:
“identifying a memory location of a second data tag value associated with the data” [e.g. Bialek; Para. 0017, 0023, 0024, 0030, 0034, 0039– Bialek discloses processing circuitry 112 executes instructions implementing memory write operation 110 (e.g. operations corresponding to a memory access instruction) computing where in bitmap 116 the tag corresponding to a head address being written is stored (e.g. identifying a memory location of a second data tag value) and identifying tag value 332A corresponding to the first address affected by the memory write operation (e.g. second data tag value associated with the data).]
“comparing the second data tag value to the first data tag value” [e.g. Bialek 0020 – Bialek discloses during a memory access that the CPU verifies the tag is encoded in the address pointer (e.g. first data tag value) matches the tag stored in the bitmap for the addressed allocation (e.g. second data tag value) thus comparing the second data tag value to the first data tag value.]
“blocking access to the data in response to detecting a mismatch between the second data tag value and the first data tag value” [e.g. Bialek 0020, 0034, 0039 – Bialek discloses when the tag encoded in the address pointer (e.g. first data tag value) done mot match the tag stored in the bitmap for the addressed allocation (e.g. second data tag value) the process throws an exception (e.g. detecting a mismatch) and processing circuity 112 or runtime environment 104 halts, pauses or terminates execution to prevent the overflowing write operation from completing (e.g. blocking access to the data in response to detecting the mismatch)]
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to further configure Shen’s execution circuitry such that execution for the ADDG or SUBG instruction includes the operations as disclosed above as taught by Bialek in order to verify memory access and provide buffer overflow protection as disclosed by Bialek in paragraphs 0020, 0023 and 0034.
Regarding claims 15-17 they are method claims essentially corresponding to the above recitations, and they are rejected, at least, for the same reasons.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER C HARRIS whose telephone number is (571)270-7841. The examiner can normally be reached Monday through Friday between 8:00 AM to 4:00 PM CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey L Nickerson can be reached on (469) 295-9235. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER C HARRIS/Primary Examiner, Art Unit 2432
Prosecution Insights