DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/16/2024 and 10/11/2023 was filed before the mailing date of the first office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khosravi et al (US 2021/0200880) in view of Durham et al (US 2021/0150040).
Regarding claims 1, 10 and 19, Khosravi et al discloses processor device, a non-transitory machine-readable medium storing at least a single instruction which, when executed by a machine, causes the machine to perform a method, and a method comprising[0215]:
decoding, by an instruction decoder of a processing device, a first instruction including a first prefix[0082] (decode circuitry configured to decode including prefixes);
performing, by cryptography circuitry of the processing device, a cryptographic operation on data, the cryptographic operation to be based at least in part on the first prefix and a pointer to the data [0055-0056, 0161-0162] (an instruction pointer is used).
However, Khosravi et al does not expressly disclose but Durham et al discloses that the operation is relative to enumeration in a pointer [0131] (enumeration may be included in the objects).
It would have been obvious to one of ordinary skill in the art at to create the invention as claimed for the following reasons. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Khosravi et al by including enumeration relative to the pointer, for the purpose of securing access and protection to data, based upon the beneficial teachings provided by Durham et al, see for example [0131]. These modifications would result in ease of use and increased security, both of which are obvious benefits to the skilled artisan. Additionally, the cited references are in the field of computer security, as is the current application, and thus, are in analogous arts.
Regarding claims 2, 11, and 20, Khosravi et al and Durham et al disclose all the limitations of independent claims 1, 10, and 19. Khosravi et al further discloses decoding, by the instruction decoder, a second instruction including a second prefix based on the relative enumeration in the pointer [0087] (one or more instruction fields may be used).
Regarding claims 3 and 12, Khosravi et al and Durham et al disclose all the limitations of independent claims 1, 10, and 19. Khosravi et al further discloses wherein the data corresponds to a member of an object [0195, 0200] (an opcode indicates an address which links to the key).
Regarding claims 4 and 13, Khosravi et al and Durham et al disclose all the limitations of independent claims 1, 10, and 19. Khosravi et al further discloses wherein the first prefix is related to the member [0195, 0200-0201] (an opcode indicates an address which links to the key).
Regarding claims 5 and 14, Khosravi et al and Durham et al disclose all the limitations of independent claims 1, 10, and 19. Khosravi et al further discloses wherein the second prefix is related to the object [0195, 0200-0201] (an opcode indicates an address which links to the key).
Regarding claims 6 and 15, Khosravi et al and Durham et al disclose all the limitations of independent claims 1, 10, and 19. Khosravi et al does not expressly disclose but Durham et al further discloses wherein the cryptographic operation is based at least on a tweak derived from the first prefix and the relative enumeration [0024, 0028, 0131] (data input may be tweaked).
The motivation to combine is the same as disclosed in point (8) above.
Regarding claims 7 and 16, Khosravi et al and Durham et al disclose all the limitations of independent claims 1, 10, and 19. Khosravi et al does not expressly disclose but Durham et al further discloses wherein the tweak is derived from a sum of the first prefix and the relative enumeration [0129, 0316, 0028] (an opcode of ADD may be implemented depending on the data being accessed).
The motivation to combine is the same as disclosed in point (8) above.
Regarding claims 8 and 17, Khosravi et al and Durham et al disclose all the limitations of independent claims 1, 10, and 19. Khosravi et al does not expressly disclose but Durham et al further discloses performing, by execution circuitry of the processing device, one or more operations corresponding to the first instruction, including moving the data [0129, 0045, 0123, 0163] (an opcode of MOV may be implemented depending on the data being accessed).
The motivation to combine is the same as disclosed in point (8) above.
Regarding claims 9 and 18, Khosravi et al and Durham et al disclose all the limitations of independent claims 1, 10, and 19. Khosravi et al does not expressly disclose but Durham et al further discloses performing, by execution circuitry of the processing device, one or more operations corresponding to the second instruction, including calculating an effective address of the data based at least in part on the pointer [0028, 0033] (the address can be correctly decrypted based on information pulled from the tweak).
The motivation to combine is the same as disclosed in point (8) above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Eoyle et al (US 12,260,221) discloses instruction storage configured to selectively provide a group of two or more program instructions for execution in parallel; and trigger circuitry responsive to the generation of a trigger state by execution of program instructions and to a trigger condition associated with a given group of program instructions, to control the instruction storage to provide program instructions of the given group of program instructions for execution.
Adelman et al (US 12,517,728): discloses performing prefix sums in response to a single instruction. In some examples, the single instruction includes fields for an opcode, one or fields to reference a first source operand, one or fields to reference a second source operand, one or fields to reference a destination operand, wherein the opcode is to indicate that execution circuitry is, in response to a decoded instance of the single instruction, to at least: perform a prefix sum by for each non-masked data element position of the second source operand adding a data element of that data element position to each data element of preceding data element positions and adding at least one data element of a defined data element position of the first source operand, and store each prefix sum for each data element position of the second source operand into a corresponding data element position of the destination operand.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENDALL DOLLY whose telephone number is (571)270-1948. The examiner can normally be reached Monday-Friday 7am-3pm (EST).
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/KENDALL DOLLY/Primary Examiner, Art Unit 2436
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