DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Applicant’s cancellation of claims 4 and 12-13 in the reply filed on 12/23/2025 is acknowledged.
Applicant’s amendment of claims 1, 6, and 9 in the reply filed on 12/23/2025 is acknowledged.
Claims 1-3 and 5-11 are under consideration in this Office Action.
Response to Arguments
Applicant’s arguments, see Remarks, filed 12/23/2025, with respect to the rejection(s) of claim 1-11 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yamazaki’334 et al., US 2013/0320334 (corresponding to US 9,496,408).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamazaki’334 et al., US 2013/0320334 (corresponding to US 9,496,408; hereafter Yamazaki’334’334).
In re Claim 1, Yamazaki’334 discloses a semiconductor device 300 (Fig. 1) comprising: an oxide semiconductor layer 408 provided on an insulating surface ([0046]) and having a channel area (a portion of 406 between SA and DA marked as CH in Fig. A), a source area (a portion of 408 underneath 410a marked as SA inn Fig, A) and a drain area (a portion of 408 underneath 410b marked as DA inn Fig, A) sandwiching the channel area CH; a gate electrode 402 opposite the channel area CH; and a gate insulating layer 404 provided between the oxide semiconductor layer 408 and the gate electrode 402, wherein the gate electrode 402 is in contact with the gate insulating layer 404, the gate electrode 402 is an oxide conductive layer ([0053]; [0096-0097]) having the same composition as the oxide semiconductor layer 408, and the oxide conductive layer 402, the source area SA, and the drain area DA include a same impurity element ([0049-0050]) (Figs. 1 and A; [0045 -0100]).
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Fig. A. Yamazaki’334’s Fig. 1B annotated to show the details cited
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-3, 6, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki’334 as applied to claim 1 above.
In re Claim 2, Yamazaki’334 discloses all limitations of Claim 2 except for that a concentration of the impurity element in the source area SA and drain area DA is 1x1018 cm-3 or more as measured by SIMS analysis (secondary ion mass spectrometry).
The only difference between the Applicant’s Claim 2 and Yamazaki’334’s reference is in the specified concentration of the impurity element. It is known in the art that the concentration of the impurity element is a result effective variable – because specific mass density depends on it. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the concentration of the impurity element in the source area SR and drain area DR is 1 × 1018 cm-3 or more and 1 × 1021 cm-3 or less as measured by SIMS analysis, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (MPEP2144.05.I).
In re Claim 3, Yamazaki’334 discloses all limitations of Claim 3 except for that the concentration of the impurity element in the oxide conductive layer 408 is between 1 × 1018 cm-3 or more and 1 × 1021 cm-3 or less as measured by SIMS analysis (secondary ion mass spectrometry).
The only difference between the Applicant’s Claim 3 and Yamazaki’334’s reference is in the specified concentration of the impurity element. It is known in the art that the concentration of the impurity element is a result effective variable – because a specific mass density depends on it. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the concentration of the impurity element in the oxide conductive layer 408 is between 1 × 1018 cm-3 or more and 1 × 1021 cm-3 or less as measured by SIMS analysis, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (MPEP2144.05.I).
In re Claim 6, Yamazaki’334 discloses all limitations of Claim 6 except for that the thickness of the oxide semiconductor layer 408 is 50 nm or more and 150 nm or less.
The difference between the Applicant’s Claim 8 and Yamazaki’334’s reference is in the specified thickness of the oxide semiconductor layer. It is known in the art that the thickness of the oxide semiconductor layer is a result effective variable – because its volume depends on it. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the thickness of the thickness of the oxide semiconductor layer 408 is 50 nm or more and 150 nm or less, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (MPEP2144.05.I).
In re Claim 8, Yamazaki’334 discloses all limitations of Claim 6 except for that thickness of the gate insulating layer 404 is between 50 nm or more and 150 nm or less.
The difference between the Applicant’s Claim 8 and Yamazaki’334’s reference is in the specified thickness of the gate insulating layer 404 . It is known in the art that the thickness of the gate insulating layer is a result effective variable – because its volume depends on it. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the thickness of the gate insulating layer 404 is between 50 nm or more and 150 nm or less, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (MPEP2144.05.I).
Claims 5, 7, and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki’334 as applied to claim 1 above, in view of Yamazaki et al., US 2016/0193767 (corresponding to US 9,728,651 and listed in a previous Office Action; Hereafter Yamazaki’767).
In re Claim 5, Yamazaki’334 discloses all limitations of Claim 5 except for that the oxide semiconductor layer 408 has a polycrystalline structure.
Yamazaki’767 teaches a semiconductor device wherein the oxide semiconductor layer 620 has a polycrystalline structure (Figs. 12-13; [0201-0204]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the Yamazaki’334’s oxide semiconductor layer with Yamazaki’767’s oxide semiconductor layer having the polycrystalline structure, to provide a high-performance semiconductor device including a transistor capable of high-speed response and high-speed operation as taught by Yamazaki’767 ([0008]).
In re Claim 7, Yamazaki’334 discloses all limitations of Claim 7 except for that the oxide conductive layer 402 has a polycrystalline structure. It would have been obvious to one of ordinary skill in the art at the time the invention was made to use the oxide conductive layer 402 with a polycrystalline structure since it was known in the art that it is well-known and routine way to use polycrystalline oxide conductive layer. (MPEP2144.I.)
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki’334 as applied to claim 1 above, in view of Koezuka et al., US 2021/0126115 (listed in a previous Office Action).
In re Claim 9, Yamazaki’334 discloses all limitations of Claim 9 except for that a metal oxide layer, wherein the metal oxide layer includes aluminum, and the metal oxide layer is provided above the insulating surface and in contact with the lower surface of the oxide semiconductor layer.
Koezuka teaches a semiconductor device comprising an oxide semiconductor layer 108, gate electrode 112, gate insulating layer 110, wherein the gate electrode 110 is in contact with the gate insulating layer 110, a metal oxide layer (an upper portion of 103, [0091]), wherein the metal oxide layer (the upper portion of 103) includes aluminum , [0091]), and the metal oxide layer (the upper portion of 103) is provided above the insulating surface (a lower portion of 103) and in contact with the lower surface of the oxide semiconductor layer 108 (Figs. 1; [0074 – 0119]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to combine teachings of Yamazaki’334 and Koezuka, and to use the specified metal oxide layer to provide favorable electrical characteristics as taught by Koezuka ([0016).
In re Claim 10, Yamazaki’334 taken with Koezuka discloses all limitations of Clam 10 except for that the thickness of the metal oxide layer (the upper portion of 103, Koezuka’s Fig. 1) is between 1 nm or more and 20 nm or less. It is known in the art that the thickness of the metal oxide layer is a result effective variable – because its volume depends on it. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the metal oxide layer (the upper portion of 103, Koezuka’s Fig. 1) is between 1 nm or more and 20 nm or less, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (MPEP2144.05.I).
In Re Claim 11, Yamazaki’334 taken with Koezuka discloses semiconductor device according to claim 9,wherein the metal oxide layer (the upper portion of 103, Koezuka’s Fig. 1) inherently has barrier properties against oxygen and hydrogen. It is inherently because according to MPEP2112.01 [R-3] Composition, Product, and Apparatus Claims I. PRODUCT AND APPARATUS CLAIMS — WHEN THE STRUCTURE RECITED IN THE REFERENCE IS SUBSTANTIALLY IDENTICAL TO THAT OF THE CLAIMS, CLAIMED PROPERTIES OR FUNCTIONS ARE PRESUMED TO BE INHERENT. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). In the instant case the metal oxide layer (the upper portion of 103, Koezuka’s Fig. 1) being SUBSTANTIALLY IDENTICAL TO THAT OF THE CLAIMS inherently possesses the barrier properties against oxygen and hydrogen.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIKOLAY K YUSHIN whose telephone number is (571)270-7885. The examiner can normally be reached Monday-Friday (7-7 PST).
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/NIKOLAY K YUSHIN/Primary Examiner, Art Unit 2893
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