Prosecution Insights
Last updated: April 19, 2026
Application No. 18/346,309

REAL TIME INPUT/OUTPUT ADDRESS TRANSLATION FOR VIRTUALIZED SYSTEMS

Non-Final OA §112
Filed
Jul 03, 2023
Examiner
ALSIP, MICHAEL
Art Unit
2139
Tech Center
2100 — Computer Architecture & Software
Assignee
Texas Instruments Incorporated
OA Round
5 (Non-Final)
75%
Grant Probability
Favorable
5-6
OA Rounds
2y 11m
To Grant
80%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allow Rate
481 granted / 645 resolved
+19.6% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
30 currently pending
Career history
675
Total Applications
across all art units

Statute-Specific Performance

§101
2.8%
-37.2% vs TC avg
§103
39.6%
-0.4% vs TC avg
§102
37.3%
-2.7% vs TC avg
§112
15.3%
-24.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 645 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In view of the appeal brief filed on 12/01/2025, PROSECUTION IS HEREBY REOPENED. A new grounds of rejection is set forth below. To avoid abandonment of the application, appellant must exercise one of the following two options: (1) file a reply under 37 CFR 1.111 (if this Office action is non-final) or a reply under 37 CFR 1.113 (if this Office action is final); or, (2) initiate a new appeal by filing a notice of appeal under 37 CFR 41.31 followed by an appeal brief under 37 CFR 41.37. The previously paid notice of appeal fee and appeal brief fee can be applied to the new appeal. If, however, the appeal fees set forth in 37 CFR 41.20 have been increased since they were previously paid, then appellant must pay the difference between the increased fees and the amount previously paid. A Supervisory Patent Examiner (SPE) has approved of reopening prosecution by signing at the end of this Office Action. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-4, 6-13 and 16-22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 1 states: “the routing circuit is configured to cause a memory request to be provided to a first translation circuit from among the set of translation circuits based on an attribute of the memory request”, “determine based on the attribute, whether the first address is an intermediate address; the set of translation circuits includes a second translation circuit configured to, based on the attribute specifying that the first address is an intermediate address”, and “the routing circuit is configured to determine, based on the attribute of the memory request, whether to cause the second translation circuit to determine the second address”. These limitations appear to be stating that the claimed attribute causes a memory request (which includes a first address) to be provided to a first translation circuit, specifies that the first address is an intermediate address and whether to cause a second translation circuit to determine a second address. The examiner has not found one attribute that performs all three of these functions in the specification. Fig. 8 and paragraphs [0032]-[0036] of the specification describe the use of multiple attributes with one attribute in particular (type attribute) having three assigned values. But, this attribute is used to determine the translation unit to which a particular memory access request is to be routed and does not appear to specific an intermediate address or cause more than one translation unit to be selected related to a particular incoming memory access request. Claim 10 has the same issues as claim 1 above. Claims 2-4, 6-13, 15 and 16 are rejected by virtue of their dependence upon a rejected base claim. Claim 17 has a similar issue to claims 1 and 10 above. The first attribute causes a memory request (which includes a first address) to be provided to a first translation circuit and specifies that the first address is an intermediate address and then the process is performed again for a second memory request with a second attribute that causes a memory request (which includes a third address) to be provided to a first translation circuit and specifies that the third address is not an intermediate address. The examiner has not found one attribute that performs both of these functions in the specification. Fig. 8 and paragraphs [0032]-[0036] of the specification describe the use of multiple attributes with one attribute in particular (type attribute) having three assigned values. But, this attribute is used to determine the translation unit to which a particular memory access request is to be routed and does not appear to specific an intermediate address or cause more than one translation unit to be selected related to a particular incoming memory access request. Claims 18-22 are rejected by virtue of their dependence upon a rejected base claim. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-4, 6-13 and 16-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. For independent claims 1 and 10, it is unclear how one attribute causes a memory request (which includes a first address) to be provided to a first translation circuit, specifies that the first address is an intermediate address and whether to cause a second translation circuit to determine a second address. For independent claim 17, it is unclear how one attribute causes a memory request (which includes a first address) to be provided to a first translation circuit and specifies that the first address is an intermediate address and then the process is performed again for a second memory request with a second attribute that causes a memory request (which includes a third address) to be provided to a first translation circuit and specifies that the third address is not an intermediate address. The dependent claims are rejected by virtue of their dependence upon a rejected base claim. Allowable Subject Matter The independent claims describe a single attribute with multiple specific functions, in combination with the rest of the claim language, that has not been found in the prior art by the examiner, however these claims are subject to both 112 (a) and (b) rejections and therefore are not in condition for allowance. Response to Arguments/Appeal Brief After reviewing the appeal brief dated 12/1/2025, the examiner has reopened prosecution to address concerns related to the applicant’s arguments on the examiner’s interpretation of the claimed term “attribute”. After reviewing the applicants arguments related to the examiner’s interpretation of this term and the applicant’s specification, the examiner has removed the previous prior art rejections and added the 112 (a) and (b) rejections above. The applicant further argues, with respect claim 17, that Schulhauser/contingent limitations does not apply to this method claim as stated by the examiner. Section 2111.04 II. Contingent limitations states the following: “The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim.” and “[i]f the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed" (quotation omitted). Schulhauser at 10.”. Therefore the steps requiring the result of a “determining whether” limitation are not required if the option not further specified/claimed comes to pass. The previous 112 rejections have been withdrawn. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ALSIP whose telephone number is (571)270-1182. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G. Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL ALSIP/Primary Examiner, Art Unit 2139 /REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
Read full office action

Prosecution Timeline

Jul 03, 2023
Application Filed
Jan 30, 2024
Non-Final Rejection — §112
May 06, 2024
Response Filed
Jun 21, 2024
Final Rejection — §112
Oct 09, 2024
Request for Continued Examination
Oct 18, 2024
Response after Non-Final Action
Oct 21, 2024
Non-Final Rejection — §112
Feb 11, 2025
Response Filed
Mar 26, 2025
Final Rejection — §112
Aug 01, 2025
Notice of Allowance
Dec 01, 2025
Response after Non-Final Action
Dec 09, 2025
Response after Non-Final Action
Feb 13, 2026
Non-Final Rejection — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12596685
SYSTEM AND METHODS FOR BANDWIDTH-EFFICIENT DATA ENCODING
2y 5m to grant Granted Apr 07, 2026
Patent 12591518
VALIDITY MAPPING TECHNIQUES
2y 5m to grant Granted Mar 31, 2026
Patent 12591545
SYSTEM AND METHOD FOR SECURING HIGH-SPEED INTRACHIP COMMUNICATIONS
2y 5m to grant Granted Mar 31, 2026
Patent 12585950
METHOD AND ELECTRONIC DEVICE FOR PERFORMING DEEP NEURAL NETWORK OPERATION
2y 5m to grant Granted Mar 24, 2026
Patent 12578856
SYSTEM AND METHOD FOR DATA COMPACTION AND SECURITY USING MULTIPLE ENCODING ALGORITHMS WITH PRE-CODING AND COMPLEXITY ESTIMATION
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

5-6
Expected OA Rounds
75%
Grant Probability
80%
With Interview (+5.1%)
2y 11m
Median Time to Grant
High
PTA Risk
Based on 645 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month