Prosecution Insights
Last updated: October 16, 2026
Application No. 18/346,566

SYSTEMS AND METHODS FOR A LOW-PROFILE RECTIFIER FOR EV WIRELESS CHARGING USING EMBEDDED PCB

Non-Final OA §102§103
Filed
Jul 03, 2023
Examiner
CAZAN, LIVIUS RADU
Art Unit
3729
Tech Center
3700 — Mechanical Engineering & Manufacturing
Assignee
Toyota Motor Corporation
OA Round
1 (Non-Final)
63%
Grant Probability
Moderate
1-2
OA Rounds
2m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 63% of resolved cases
63%
Career Allowance Rate
608 granted / 965 resolved
-7.0% vs TC avg
Strong +25% interview lift
Without
With
+24.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
44 currently pending
Career history
1010
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
45.8%
+5.8% vs TC avg
§102
25.0%
-15.0% vs TC avg
§112
26.1%
-13.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 965 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I in the reply filed on 5/11/2026 is acknowledged. Claims 8-14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5/11/2026. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 4, 7, 15, and 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Choutov (US2011/0285312A1). Choutov discloses the claimed invention as follows (refer to Figs. 1-2F): Claim 1. A method comprising: fabricating a rectifier (see Fig. 2F), wherein fabricating the rectifier includes: fabricating (see steps of Figs. 2A to 2F) a power device area (at 302 and at 304) in a printed circuit board (the various dielectric and conductive layers of Fig. 2F); fabricating (see steps of Figs. 2A to 2F) a passive component area (at 303) in the PCB; fabricating an inductor area (together: 307, 308, 310 and 314; see Fig. 2E and [in the PCB, wherein each component of the power device area, the passive component area, and copper windings of the inductor area is entirely embedded within the PCB (see Fig. 2F); and assembling one or more ferrite blocks (309; see Figs. 2A and 2F; see [0033]) into the PCB. Claim 4. The method of claim 1, wherein the power device area (304) is located in a center portion of the PCB (see Fig. 2F). Claim 7. The method of claim 1, wherein a cold plate (316) is attached to a bottom (view Fig. 2F upside-down) copper layer (310) of the PCB. Claim 15. An apparatus comprising: a rectifier (structure of 2F), wherein the rectifier includes: a power device area (at 302; at 304; see if 2F) in a printed circuit board; a passive component area (at 303) in the PCB; an inductor area (together: 307, 308, 310 and 314) in the PCB, wherein each component of the power device area, the passive component area, and copper windings of the inductor area is entirely embedded within the PCB (see Fig. 2F); and one or more ferrite blocks (309; see [0033]) in the PCB. Claim 18. The apparatus of claim 15, wherein the power device area (304) is located in a center portion of the PCB. See Fig. 2F. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim(s) 6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Choutov. Choutov discloses the claimed invention, including the power device area (302, Fig. 2F) being located at a side of the PCB, but it is unclear whether the power device is located at a corner portion of the PCB. However, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to change the location of components, such as moving a power device 302 close to a corner of the PCB while maintaining the same connections between components (i.e., not modifying the circuit), as this still allows the device to perform the same functions. Claim 2, 3, 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Choutov in view of Zhou (US2022/0157693A1). Choutov further discloses the claimed invention as follows (limitations not disclosed are crossed out): Claim 2. The method of claim 1, wherein fabricating the rectifier further includes fabricating, under (refer to Fig. 2F but turned upside-down) an active power device area (304), a plurality of vias (315) connecting Claim 3. The method of claim 2, wherein the one or more copper layers of the PCB extend beyond the power device area and the passive component area. See 316 in Fig. 2F. Claim 16. The apparatus of claim 15 further comprising a plurality of vias (315) under (see Fig. 2F upside-down) an active power device area connecting Claim 17. The apparatus of claim 16, wherein the one or more copper layers of the PCB extend beyond the power device area and the passive component area. See 316 in Fig. 2F. Zhou teaches power device 140 being bonded to a copper substrate 134 (see Fig. 2 and [0042]; see also [0044] for a more detailed description of the bonding between 134 and 140). Thermal vias 101A connect the copper substrate 134 to a copper layer 103 (see Fig. 2 and [0042]), providing paths for thermal conductance between components and layers of the PCB. See [0042]. Taking into consideration the combined teachings of Choutov and Zhou, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to bond IAD component 304 to a copper substrate, such that thermal vias 415 improve thermal conductance from the component to the copper layer 316, thereby improving cooling of the device. Claim(s) 5 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choutov in view of Zheng (US2019/0363058A1). Choutov discloses the claimed invention, except for PCB winding inductors radially surrounding the power device area. The device of Choutov is a buck converter. It is known in the art to manufacture a multiphase interleaved buck circuit, wherein each phase of the multiphase interleaved buck circuit comprises an inductor structure (see three inductor structures in Fig. 2, each comprising a core 32 and corresponding windings within the substrate 31). Taking into consideration the combined teachings of Choutov and Zheng, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Choutov to include multiple inductor portions, and corresponding power devices, to implement a multiphase buck converter. Regarding the geometric arrangement of components on the substrate, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to arrange the components in any suitable manner, such as with the inductors radially surrounding the power devices, since changing the location of the various components does not affect the functioning of the circuit, as long as all components are still connected according to the intended circuit. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US2008/0315398A1 is a reference disclosing thermal vias (116a) connecting a conductive layer (130) within the PCB to an external conductive layer (112b), for improved thermal dissipation from the component. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LIVIUS R CAZAN whose telephone number is (571)272-8032. The examiner can normally be reached Monday - Friday noon-8:30 pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hong can be reached at 571-272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LIVIUS R. CAZAN/Primary Examiner, Art Unit 3729
Read full office action

Prosecution Timeline

Jul 03, 2023
Application Filed
Aug 18, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
63%
Grant Probability
88%
With Interview (+24.8%)
3y 5m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 965 resolved cases by this examiner. Grant probability derived from career allowance rate.

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