DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II species B (claims 1-10) in the reply filed on is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2020/0287131).
[claim 1] A semiconductor device (fig. 6A,6B, 7), comprising: a substrate (100, fig. 6B); a plurality of memory cells (MC, fig. 6B, electrodes 110A and 150A may optionally may not be included in the memory cell) positioned over the substrate, each of the plurality of memory cells having a multi-layer structure (fig. 6B) including a memory pattern (140, fig. 6B); a sealing layer pattern (160A, fig. 6B, [0053]) filling a lower portion of a space (void V, fig. 6B) between the memory cells, the lower portion being positioned below a bottom surface of the memory pattern; a liner layer pattern (160B, fig. 6B, [0054]) formed along a surface of an upper portion of the space to partially fill the upper portion; and a dielectric layer (170A, fig. 6B, [0078]) pattern filling a remaining portion of the space unfilled by the sealing layer pattern and the liner layer pattern.
[claim 2] The semiconductor device of claim 1, wherein a height of an upper surface of the sealing layer pattern at a first distance (height of 161a at the very top of 150A which is on a slanted upper surface, fig. 6B) from the memory cell is greater than a height of the upper surface of the sealing layer pattern at a second distance (height of 161a of the upper surface of 161A at the bottom of the void V, note that upper surface of the slanted portion can only have the first distance less than the thickness of layer 161A while the second distance can be measured from the middle of the upper surface at the second height at the bottom of void V) , the second distance being greater than the first distance (fig. 6b).
[claim 3] The semiconductor device of claim 1, wherein a thermal conductivity of the dielectric layer pattern is lower than a thermal conductivity of the liner layer pattern and a thermal conductivity of the sealing layer pattern [0068].
[claim 4] The semiconductor device of claim 1, wherein the liner layer pattern covers a sidewall of the memory pattern (fig. 6b).
[claim 5] The semiconductor device of claim 1, wherein the memory cell further includes a selector pattern (120A, fig. 6B, [0048]) positioned below the memory pattern, and wherein the sealing layer pattern covers a sidewall of the selector pattern (fig. 6B).
[claim 6] The semiconductor device of claim 1, further comprising: a plurality of lower conductive lines (WL1, 110A, fig. 7,6B [0086]) extending in a first direction; and a plurality of upper conductive lines (CBL, 150A fig. 7, 6B [0086]) extending in a second direction crossing the first direction, wherein the memory cells overlap with intersections between the lower conductive lines and the upper conductive lines (fig. 7).
[claim 7] The semiconductor device of claim 6, wherein the sealing layer pattern includes a first sealing layer pattern (sealing layer between two MCs in the CBL direction in fig. 7, see also fig. 6A) positioned between the memory cells neighboring in the second direction, and a second sealing layer pattern (sealing layer between two MCs in the WL direction in fig. 7, see also fig. 6A) positioned between the memory cells neighboring in the first direction, and wherein the first sealing layer pattern further fills a space between the lower conductive lines (between 110A of the conductive lines fig. 6B).
[claim 8] The semiconductor device of claim 6, wherein the liner layer pattern includes a first liner layer pattern (liner layer between two MCs in the CBL direction in fig. 7, see also fig. 6A) positioned between the memory cells neighboring in the second direction, and a second liner layer (liner layer between two MCs in the WL direction in fig. 7, see also fig. 6A) pattern positioned between the memory cells neighboring in the first direction, and wherein the second liner layer pattern is further formed on sidewalls of the upper conductive lines (fig. 6B).
[claim 9] The semiconductor device of claim 6, wherein the dielectric layer pattern includes a first dielectric layer pattern (dielectric layer between two MCs in the CBL direction in fig. 7, see also fig. 6A) positioned between the memory cells neighboring in the second direction, and a second dielectric layer pattern (dielectric layer between two MCs in the WL direction in fig. 7, see also fig. 6A) positioned between the memory cells neighboring in the first direction, and wherein the second dielectric layer pattern is further positioned between the upper conductive lines (fig. 6B).
[claim 10] The semiconductor device of claim 1, wherein the memory pattern includes a phase-change pattern [0037].
Conclusion
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/AMAR MOVVA/Primary Examiner, Art Unit 2898
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