CTNF 18/347,297 CTNF 101798 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy KR10-2022-0134029, filed on October 18, 2022, has been electronically retrieved by USPTO. Information Disclosure Statement The information disclosure statement (IDS) submitted on July 5, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. 07-30-03-h AIA Claim Interpretation 07-30-03 AIA The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. 07-30-05 The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre- AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. 07-30-06 This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: a task abstraction unit, and a resource abstraction unit in claims 6-7 and 13-14. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 8 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 8: 07-34-05 AIA Claim 8 recites the limitation " The apparatus of claim 7, wherein the task includes a neural-network-related task including a neural network task and a loader task, a system task including an idle task and an exception task, and a monitor task for monitoring a state of the task processor ." In the claim "the task" was not properly defined in any previous claim .. There is insufficient antecedent basis for this limitation in the claim. Claim 15: 07-34-05 AIA Claim 15 recites the limitation " The apparatus of claim 10, wherein the task includes a neural-network-related task including a neural network task and a loader task, a system task including an idle task and an exception task, and a monitor task for monitoring a state of the task processor ." In the claim "the task" was not properly defined in any previous claim .. There is insufficient antecedent basis for this limitation in the claim. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-17 rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Claim 1: Regarding claim 1, in step 1 of the 101-analysis set forth in MPEP 2106, the claim recites “An apparatus for distributed processing of a neural network”, and an apparatus or machine is one of the four statutory categories of invention. In step 2A prong 1 of the 101-analysis set forth in the MPEP 2106, the examiner has determined that the following limitations recite a process that, under the broadest reasonable interpretation, covers a mental process but for recitation of generic computer components: “segmenting a neural network into a predetermined number of sub-neural networks” (this is a mental process, a person could mentally segment or divide a neural network into predetermined sub-neural networks, see MPEP § 2106.04(a)(2)(III)), “abstracting the sub-neural networks into a predetermined number of tasks, performing inference” (this is a mental process, a person could mentally evaluate abstracting or assigning sub-neural networks to a predetermined number of tasks. A person can also mentally do an inference and give an inference result based on the abstracting/assigning, see MPEP § 2106.04(a)(2)(III)), If claim limitations, under the broadest reasonable interpretation, covers performance of the limitations as a mental process but for the recitation of generic computer components, then it falls within the mental process grouping of abstract ideas. Accordingly, the claim “recites” an abstract idea. In step 2A prong 2 of the 101-analysis set forth in MPEP 2106, the examiner has determined that the following additional elements do not integrate this judicial exception into a practical application: “a neural network model compiler” (Using a neural network model compiler is considered mere instructions to apply an exception using generic computer – see MPEP § 2106.05(f)), “two or more neural processing units (Using a neural processing unit is considered generic computer component being used as tool to perform functions of the judicial exception – see MPEP § 2106.05(f)), “a neural network operating system (Using a neural network operating system is considered mere instructions to apply an exception using generic computer – see MPEP § 2106.05(f)), “distributing the predetermined number of tasks abstracted to correspond to a neural network inference request of at least one application across the multiple neural processing units, and returning an inference result to the application (Distributing tasks abstracted to a neural network and returning inference to an application is considered insignificant extra-solution activity of mere data gathering – see MPEP § 2106.05(g)), Since the claim as a whole, looking at the additional elements individually and in combination, does not contain any other additional elements that are indicative of integration into a practical application, the claim is “directed” to an abstract idea. In step 2B of the 101-analysis set forth in the 2019 PEG, the examiner has determined that the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above, additional elements iii and v recites mere instructions to apply an exception using generic computer, additional element iv recites a generic computer component being used as tool to perform functions of the judicial exception, and additional element vi recites insignificant extra-solution activity of mere data gathering which is a well understood routine and conventional activity, see receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362, which are not indicative of significantly more. Considering the additional elements individually and in combination, and the claim as a whole, the additional elements do not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible. Claim 2: Regarding claim 2, it is dependent upon claim 1, and thereby incorporates the limitations of, and corresponding analysis to claim 1. Further, claim 2 recites the following additional elements: “performing inference by processing the tasks input from the broker” (this is a mental process, a person could mentally perform inferencing, see MPEP § 2106.04(a)(2)(III)), If claim limitations, under their broadest reasonable interpretation, covers performance of the limitations as a mental process but for the recitation of generic compute components, then it falls within the mental process grouping of abstract ideas. Accordingly, the claim “recites” an abstract idea. “The apparatus of claim 1, wherein the neural network operating system includes a broker for distributing the predetermined number of tasks, abstracted to correspond to the neural network inference request of the at least one neural network application” ( In step 2A, prong 2, this is considered insignificant extra-solution activity of mere data gathering – see MPEP § 2106.05(g) ). ( In step 2B, this is also considered insignificant extra-solution activity of mere data gathering, which is a well understood routine and conventional activity, see receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 ). “task processors” ( In step 2A, prong 2, this is considered generic computer component being used as tool to perform functions of the judicial exception , see MPEP § 2106.05(f)). ( In step 2B, this is also considered generic computer component being used as tool to perform functions of the judicial exception - see MPEP § 2106.05(f)). “in the neural processing units.” ( In step 2A, prong 2, this is considered generic computer component being used as tool to perform functions of the judicial exception , see MPEP § 2106.05(f)). ( In step 2B, this is also considered generic computer component being used as tool to perform functions of the judicial exception - see MPEP § 2106.05(f)). Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception , the claim is not patent eligible. Claim 3: Regarding claim 3, it is dependent upon claim 2, and thereby incorporates the limitations of, and corresponding analysis to claim 2. Further, claim 3 recites the following additional elements: “The apparatus of claim 2, wherein: the neural network application and the broker of the neural network operating system are executed on a CPU of a host, and each of the task processors of the neural network operating system is executed on a CPU of each of the multiple neural processing units.” ( In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)). ( In step 2B, this is also considered mere instructions to apply an exception using generic computer - see MPEP § 2106.05(f)). Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception , the claim is not patent eligible. Claim 4: Regarding claim 4, it is dependent upon claim 2, and thereby incorporates the limitations of, and corresponding analysis to claim 2. Further, claim 4 recites the following additional elements: “The apparatus of claim 2, wherein: the neural network application, the broker of the neural network operating system, and each of the task processors of the neural network operating system are executed on a CPU of a single neural processing unit in a form of an embedded board, and the respective task processors are executed on multiple accelerators of the single neural processing unit.” ( In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)). ( In step 2B, this is also considered mere instructions to apply an exception using generic computer - see MPEP § 2106.05(f)). Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception , the claim is not patent eligible. Claim 5: Regarding claim 5, it is dependent upon claim 2, and thereby incorporates the limitations of, and corresponding analysis to claim 2. Further, claim 5 recites the following additional elements: “The apparatus of claim 2, wherein: control messages are transmitted and received between the neural network application and the broker or between the broker and the task processor, and input/output data required for inference is transmitted and received between the neural network application and the task processor.” ( In step 2A, prong 2, this is considered insignificant extra-solution activity of mere data gathering – see MPEP § 2106.05(g) ). ( In step 2B, this is also considered insignificant extra-solution activity of mere data gathering, which is a well understood routine and conventional activity, see receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 ). Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception , the claim is not patent eligible. Claim 6: Regarding claim 6, it is dependent upon claim 2, and thereby incorporates the limitations of, and corresponding analysis to claim 2. Further, claim 6 recites the following additional elements: “generating neural network tasks by abstracting the sub-neural networks acquired by segmenting the neural network;” (this is a mental process, a person could mentally evaluate generating neural network tasks and abstracting or assigning sub-neural networks from segmenting a neural network, see MPEP § 2106.04(a)(2)(III)), If claim limitations, under their broadest reasonable interpretation, covers performance of the limitations as a mental process but for the recitation of generic compute components, then it falls within the mental process grouping of abstract ideas. Accordingly, the claim “recites” an abstract idea. “The apparatus of claim 2, wherein the broker includes a task abstraction unit” ( In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)). ( In step 2B, this is also considered mere instructions to apply an exception using generic computer - see MPEP § 2106.05(f)). “a task distributor for distributing each of the neural network tasks to one of the multiple task processors;” ( In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)). ( In step 2B, this is also considered mere instructions to apply an exception using generic computer - see MPEP § 2106.05(f)). “a broker-side loader for loading a neural network file used for the neural network application in advance into the neural processing unit;” ( In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)). ( In step 2B, this is also considered mere instructions to apply an exception using generic computer - see MPEP § 2106.05(f)). “a broker-side connector for connecting the broker with the task processor;” ( In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)). ( In step 2B, this is also considered mere instructions to apply an exception using generic computer - see MPEP § 2106.05(f)). Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception , the claim is not patent eligible. Claim 7: Regarding claim 7, it is dependent upon claim 2, and thereby incorporates the limitations of, and corresponding analysis to claim 2. Further, claim 7 recites the following additional elements: “setting an execution sequence of tasks based on priority;” (this is a mental process, a person could mentally set an execution sequence of tasks, see MPEP § 2106.04(a)(2)(III)), If claim limitations, under their broadest reasonable interpretation, covers performance of the limitations as a mental process but for the recitation of generic compute components, then it falls within the mental process grouping of abstract ideas. Accordingly, the claim “recites” an abstract idea. “The apparatus of claim 2, wherein the task processor includes a resource abstraction unit for abstracting a resource for performing neural network inference into a task processor and logically connecting the resource with the task processor;” ( In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)). ( In step 2B, this is also considered mere instructions to apply an exception using generic computer - see MPEP § 2106.05(f)). “a scheduler” ( In step 2A, prong 2, this is considered generic computer component being used as tool to perform functions of the judicial exception , see MPEP § 2106.05(f)). ( In step 2B, this is also considered generic computer component being used as tool to perform functions of the judicial exception - see MPEP § 2106.05(f)). “a task-processor-side loader for receiving a neural network file used for the neural network application and installing a neural network in a corresponding neural processing unit;” ( In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)). ( In step 2B, this is also considered mere instructions to apply an exception using generic computer - see MPEP § 2106.05(f)). “a task-processor-side connector for registering the task processor in the broker;” ( In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)). ( In step 2B, this is also considered mere instructions to apply an exception using generic computer - see MPEP § 2106.05(f)). Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception , the claim is not patent eligible. Claim 8: Regarding claim 8, it is dependent upon claim 2, and thereby incorporates the limitations of, and corresponding analysis to claim 2. Further, claim 8 recites the following additional elements: “The apparatus of claim 7, wherein the task includes a neural-network-related task including a neural network task and a loader task, a system task including an idle task and an exception task, and a monitor task for monitoring a state of the task processor.” ( In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)). ( In step 2B, this is also considered mere instructions to apply an exception using generic computer - see MPEP § 2106.05(f)). Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception , the claim is not patent eligible. Claim 9: Regarding claim 8, it is dependent upon claim 2, and thereby incorporates the limitations of, and corresponding analysis to claim 2. Further, claim 8 recites the following additional elements: “The apparatus of claim 2, wherein: a task processor includes a neural network object installed by loading a specific neural network, and the neural network object is an interface that is connected when a neural network task is executed.” ( In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)). ( In step 2B, this is also considered mere instructions to apply an exception using generic computer - see MPEP § 2106.05(f)). Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception , the claim is not patent eligible. Claim 10: Regarding claim 1, in step 1 of the 101-analysis set forth in MPEP 2106, the claim recites “An apparatus for distributed processing of a neural network”, and an apparatus or machine is one of the four statutory categories of invention. In step 2A prong 1 of the 101-analysis set forth in the MPEP 2106, the examiner has determined that the following limitations recite a process that, under the broadest reasonable interpretation, covers a mental process but for recitation of generic computer components: “abstracting sub-neural networks into a predetermined number of tasks” (this is a mental process, a person could mentally evaluate abstracting a neural network to a predetermined number of tasks, see MPEP § 2106.04(a)(2)(III)), “performing inference” (this is a mental process, a person could mentally do an inference, see MPEP § 2106.04(a)(2)(III)), If claim limitations, under the broadest reasonable interpretation, covers performance of the limitations as a mental process but for the recitation of generic computer components, then it falls within the mental process grouping of abstract ideas. Accordingly, the claim “recites” an abstract idea. In step 2A prong 2 of the 101-analysis set forth in MPEP 2106, the examiner has determined that the following additional elements do not integrate this judicial exception into a practical application: “memory in which at least one program is recorded” (Using memory is considered generic computer component being used as tool to perform functions of the judicial exception – see MPEP § 2106.05(f)), “a processor for executing the program” (Using a processor is considered generic computer component being used as tool to perform functions of the judicial exception – see MPEP § 2106.05(f)), “the program includes a neural network operating system for returning a result of distributed inference, performed through multiple neural processing units in response to a neural network inference request from at least one application, to the application” (Returning a result of distributed inference to an application is considered insignificant extra-solution activity of mere data gathering – see MPEP § 2106.05(g)), “distributing the predetermined number of tasks, abstracted to correspond to the neural network inference request of the at least one application, across the multiple neural processing units;” (Distributing tasks abstracted to a neural network inference request across multiple neural processing units is considered insignificant extra-solution activity of mere data gathering – see MPEP § 2106.05(g)), “a broker” (Using a broker is considered generic computer component being used as tool to perform functions of the judicial exception – see MPEP § 2106.05(f)), “multiple task processors” (Using task processors is considered generic computer component being used as tool to perform functions of the judicial exception – see MPEP § 2106.05(f)), “processing the tasks input from the broker in the neural processing units connected thereto.” ( processing tasks input from a broker to neural processing units is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)), Since the claim as a whole, looking at the additional elements individually and in combination, does not contain any other additional elements that are indicative of integration into a practical application, the claim is “directed” to an abstract idea. In step 2B of the 101-analysis set forth in the 2019 PEG, the examiner has determined that the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above, additional element ix recites mere instructions to apply an exception using generic computer, additional elements iii, iv, vii, and viii recites a generic computer component being used as tool to perform functions of the judicial exception, and additional elements v and vi recites insignificant extra-solution activity of mere data gathering which is a well understood routine and conventional activity, see receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362, which are not indicative of significantly more. Considering the additional elements individually and in combination, and the claim as a whole, the additional elements do not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible. Claim 11: Regarding claim 11, it is dependent upon claim 10, and thereby incorporates the limitations of, and corresponding analysis to claim 10. Further, claim 11 recites the following additional elements: “The apparatus of claim 10, wherein the neural network application and the broker of the neural network operating system are executed on a CPU of a host, and each of the task processors of the neural network operating system is executed on a CPU of each of the multiple neural processing units.” ( In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)). ( In step 2B, this is also considered mere instructions to apply an exception using generic computer - see MPEP § 2106.05(f)). Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception , the claim is not patent eligible. Claim 12: Regarding claim 12, it is dependent upon claim 10, and thereby incorporates the limitations of, and corresponding analysis to claim 10. Further, claim 12 recites the following additional elements: “The apparatus of claim 10, wherein the neural network application, the broker of the neural network operating system, and each of the task processors of the neural network operating system are executed on a CPU of a single neural processing unit in a form of an embedded board, and the respective task processors are executed on multiple accelerators of the single neural processing unit.” ( In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)). ( In step 2B, this is also considered mere instructions to apply an exception using generic computer - see MPEP § 2106.05(f)). Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception , the claim is not patent eligible. Claim 13: Regarding claim 13, it is dependent upon claim 10, and thereby incorporates the limitations of, and corresponding analysis to claim 10. Further, claim 13 recites the following additional elements: “generating neural network tasks by abstracting the sub-neural networks acquired by segmenting a neural network;” (this is a mental process, a person could mentally evaluate generating neural network tasks and abstracting or assigning sub-neural networks from segmenting a neural network, see MPEP § 2106.04(a)(2)(III)), If claim limitations, under their broadest reasonable interpretation, covers performance of the limitations as a mental process but for the recitation of generic compute components, then it falls within the mental process grouping of abstract ideas. Accordingly, the claim “recites” an abstract idea. “The apparatus of claim 10, wherein the broker includes a task abstraction unit” ( In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)). ( In step 2B, this is also considered mere instructions to apply an exception using generic computer - see MPEP § 2106.05(f)). “a task distributor for distributing each of the neural network tasks to one of the multiple task processors;” ( In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)). ( In step 2B, this is also considered mere instructions to apply an exception using generic computer - see MPEP § 2106.05(f)). “a broker-side loader for loading a neural network file used for the neural network application in advance into the neural processing unit;” ( In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)). ( In step 2B, this is also considered mere instructions to apply an exception using generic computer - see MPEP § 2106.05(f)). “a broker-side connector for connecting the broker with the task processor;” ( In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)). ( In step 2B, this is also considered mere instructions to apply an exception using generic computer - see MPEP § 2106.05(f)). Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception , the claim is not patent eligible. Claim 14: Regarding claim 14, it is dependent upon claim 10, and thereby incorporates the limitations of, and corresponding analysis to claim 10. Further, claim 14 recites the following additional elements: “setting an execution sequence of tasks based on priority;” (this is a mental process, a person could mentally set an execution sequence of tasks, see MPEP § 2106.04(a)(2)(III)), If claim limitations, under their broadest reasonable interpretation, covers performance of the limitations as a mental process but for the recitation of generic compute components, then it falls within the mental process grouping of abstract ideas. Accordingly, the claim “recites” an abstract idea. “The apparatus of claim 10, wherein the task processor includes a resource abstraction unit for abstracting a resource for performing neural network inference into a task processor and logically connecting the resource with the task processor;” ( In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)). ( In step 2B, this is also considered mere instructions to apply an exception using generic computer - see MPEP § 2106.05(f)). “a scheduler” ( In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)). ( In step 2B, this is also considered mere instructions to apply an exception using generic computer - see MPEP § 2106.05(f)). “a task-processor-side loader for receiving a neural network file used for the neural network application and installing a neural network in a corresponding neural processing unit;” ( In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)). ( In step 2B, this is also considered mere instructions to apply an exception using generic computer - see MPEP § 2106.05(f)). “a task-processor-side connector for registering the task processor in the broker;” ( In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)). ( In step 2B, this is also considered mere instructions to apply an exception using generic computer - see MPEP § 2106.05(f)). Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception , the claim is not patent eligible. Claim 15: Regarding claim 15, it is dependent upon claim 10, and thereby incorporates the limitations of, and corresponding analysis to claim 10. Further, claim 15 recites the following additional elements: “The apparatus of claim 10, wherein the task includes a neural-network-related task including a neural network task and a loader task, a system task including an idle task and an exception task, and a monitor task for monitoring a state of the task processor.” ( In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer, see MPEP § 2106.05(f)). ( In step 2B, this is also considered mere instructions to apply an exception using generic computer - see MPEP § 2106.05(f)). Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception , the claim is not patent eligible. Claim 16: Regarding claim 1, in step 1 of the 101-analysis set forth in MPEP 2106, the claim recites “A method for distributed processing of a neural network”, and a method or process is one of the four statutory categories of invention. In step 2A prong 1 of the 101-analysis set forth in the MPEP 2106, the examiner has determined that the following limitations recite a process that, under the broadest reasonable interpretation, covers a mental process but for recitation of generic computer components: “generating a predetermined number of tasks by segmenting a large-scale neural network into a predetermined number of parts” (this is a mental process, a person could mentally evaluate creating a number of predetermined tasks and then segmenting or dividing a large-scale neural network into a predetermined number of parts, see MPEP § 2106.04(a)(2)(III)), If claim limitations, under the broadest reasonable interpretation, covers performance of the limitations as a mental process but for the recitation of generic computer components, then it falls within the mental process grouping of abstract ideas. Accordingly, the claim “recites” an abstract idea. In step 2A prong 2 of the 101-analysis set forth in MPEP 2106, the examiner has determined that the following additional elements do not integrate this judicial exception into a practical application: “loading neural network partitions into task processors respectively connected to multiple neural processing units;” (loading neural network partitions into task processors connected to neural processing units is considered mere instructions to apply an exception using generic computer – see MPEP § 2106.05(f)), “delivering input data of an application, for which inference is requested, to a neural network process when the neural network process for controlling an execution sequence and input/output of tasks generated by the application is executed” (Delivering input data of an application is considered insignificant extra-solution activity of mere data gathering – see MPEP § 2106.05(g) ), “executing neural network tasks within the neural network process in the neural network processors, into which the respective neural network tasks are loaded, according to the execution sequence;” (Executing neural network tasks is considered mere instructions to apply an exception using generic computer – see MPEP § 2106.05(f)), “delivering output data of the neural network process to the application.” ( delivering output data is considered insignificant extra-solution activity of mere data gathering – see MPEP § 2106.05(g) ), ( In step 2B, this is also considered insignificant extra-solution activity of mere data gathering, which is a well understood routine and conventional activity, see receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 – see MPEP § 2106.05(f)) Since the claim as a whole, looking at the additional elements individually and in combination, does not contain any other additional elements that are indicative of integration into a practical application, the claim is “directed” to an abstract idea. In step 2B of the 101-analysis set forth in the 2019 PEG, the examiner has determined that the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above, additional elements ii and iv recites mere instructions to apply the judicial exception using generic computer components, which are not indicative of significantly more. In addition, additional element iii and v recites insignificant extra-solution activity of mere data gathering, which is a well understood routine and conventional activity, see receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 . Considering the additional elements individually and in combination, and the claim as a whole, the additional elements do not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible. Claim 17: Regarding claim 17, it is dependent upon claim 16, and thereby incorporates the limitations of, and corresponding analysis to claim 16. Further, claim 17 recites the following additional elements: “The apparatus of claim 16, wherein the neural network partition is in a form of file, and includes a descriptor for describing the neural network and a kernel.” ( In step 2A, prong 2, this is considered as mere field of use or technological environment in which to apply a judicial exception, see MPEP § 2106.05(h)). ( In step 2B, this is also considered mere field of use or technological environment in which to apply a judicial exception - see MPEP § 2106.05(h)). Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception , the claim is not patent eligible. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 10, and 14-15 are rejected under 35 U.S.C. 102( a)(1) and 102(a)(2 ) as being anticipated by Goyal A. et al, (US. Patent Application Publication 20230234233 A1) filed on January 26, 2022, (hereafter Goyal) . Claim 10: Regarding claim 10, Goyal teaches “An apparatus for distributed processing of a neural network, comprising: memory in which at least one program is recorded;” See Goyal in paragraph [0063] where it describes “In at least one embodiment, object placement logic 122 include perception logic 126 , planning logic 128 , and movement logic 130 . In at least one embodiment, logic (e.g., object placement logic 122 , perception logic 126 , planning logic 128 , and/or movement logic 130 ) refers to any combination of software logic, hardware logic, and/or firmware logic to provide functionality or operations described herein” Here, Goyal establishes a logic doing operations of the embodiment. Further, see Goyal in paragraph [0063] describing “In at least one embodiment, instructions are stored in memory 120 , which if performed by processor 118 and/or GPU 119 , are to cause processor 118 and/or GPU 119 to perform one or more aspects of object placement logic 122 .” Here, Goyal establishes instructions of the embodiment being stored in memory and a processor for performing or executing the instructions which can be seen as a memory in which a program is recorded. Further, Goyal teaches “a processor for executing the program,” See Goyal in paragraph [0063] where it describes “In at least one embodiment, object placement logic 122 include perception logic 126 , planning logic 128 , and movement logic 130 . In at least one embodiment, logic (e.g., object placement logic 122 , perception logic 126 , planning logic 128 , and/or movement logic 130 ) refers to any combination of software logic, hardware logic, and/or firmware logic to provide functionality or operations described herein” Here, Goyal establishes a logic doing operations of the embodiment. Further, see Goyal in paragraph [0063] describing “In at least one embodiment, instructions are stored in memory 120 , which if performed by processor 118 and/or GPU 119 , are to cause processor 118 and/or GPU 119 to perform one or more aspects of object placement logic 122 .” Here, Goyal establishes instructions of the embodiment being stored and a processor for performing or executing the instructions which can be seen as a processor executing said program. Further, Goyal teaches “wherein the program includes a neural network operating system for returning a result of distributed inference, performed through multiple neural processing units in response to a neural network inference request from at least one application, to the application,” See Goyal in paragraph [0545] describing “In at least one embodiment, data may undergo pre-processing as part of data processing pipeline to prepare data for processing by one or more applications. In at least one embodiment, post-processing may be performed on an output of one or more inferencing tasks or other processing tasks of a pipeline to prepare an output data for a next application and/or to prepare output data for transmission and/or use by a user (e.g., as a response to an inference request). In at least one embodiment, inferencing tasks may be performed by one or more machine learning models, such as trained or deployed neural networks, which may include output models 3916 of training system 3904 .” Here, Goyal establishes returning an inference result, which is considered the output data, of distributed inference to the application in response to an inference request of an application. Goyal then establishes that the tasks can be performed by deployed neural networks which can make the inference request be seen as a neural network inference request. The training system comprising the neural networks here can be seen as the neural network operating system. Further, see Goyal in paragraph [0109] describing “In at least one embodiment, logic 1015 is used to perform inferencing and/or training operations associated with one or more embodiments. In at least one embodiment, logic 1015 is inference and/or training logic. Details regarding logic 1015 are provided below in conjunction with FIGS. 10A and/or 10B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and/or firmware logic to provide functionality or operations described herein, wherein logic may be, collectively or individually, embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system-on-chip (SoC), or one or processors (e.g., CPU, GPU).” Here Goyal establishes the operations in relation to inference or training logic being done across multiple processing units with one or more processors. Further, Goyal teaches “the neural network operating system includes a broker for abstracting sub-neural networks into a predetermined number of tasks and distributing the predetermined number of tasks, abstracted to correspond to the neural network inference request of the at least one application, across the multiple neural processing units;” See Goyal in paragraph [0545] describing “In at least one embodiment, data may undergo pre-processing as part of data processing pipeline to prepare data for processing by one or more applications. In at least one embodiment, post-processing may be performed on an output of one or more inferencing tasks or other processing tasks of a pipeline to prepare an output data for a next application and/or to prepare output data for transmission and/or use by a user (e.g., as a response to an inference request). In at least one embodiment, inferencing tasks may be performed by one or more machine learning models, such as trained or deployed neural networks, which may include output models 3916 of training system 3904 .” Here, Goyal establishes a predetermined number of tasks with the one or more tasks being abstracted in response to an inference request of an application. Goyal then establishes that the tasks can be performed by deployed neural networks which can be seen as abstracting sub-neural networks into the predetermined number of tasks, we interpret abstracting neural networks to tasks as updating or changing a model to handle a task which is what is done here. The training system comprising the neural networks here can be seen as the neural network operating system. Further, see Goyal in paragraph [0109] describing “In at least one embodiment, logic 1015 is used to perform inferencing and/or training operations associated with one or more embodiments. In at least one embodiment, logic 1015 is inference and/or training logic. Details regarding logic 1015 are provided below in conjunction with FIGS. 10A and/or 10B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and/or firmware logic to provide functionality or operations described herein, wherein logic may be, collectively or individually, embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system-on-chip (SoC), or one or processors (e.g., CPU, GPU).” Here Goyal establishes the operations being done across multiple processing units with one or more processors. Further, see Goyal in paragraph [0551] where it describes “In at least one embodiment, hardware 3922 may include GPUs, CPUs, graphics cards, an AI/deep learning system (e.g., an AI supercomputer, such as NVIDIA's DGX supercomputer system), a cloud platform, or a combination thereof. In at least one embodiment, different types of hardware 3922 may be used to provide efficient, purpose-built support for software 3918 and services 3920 in deployment system 3906 .” Here, Goyal establishes software and services of the deployment system said to be considered a neural network operating system in previous limitations. Further, see Goyal in paragraph [0568] where it describes “In at least one embodiment, application orchestration system 4028 may distribute resources (e.g., services 3920 and/or hardware 3922 ) based on priority paths for different inferencing tasks of AI services 4018 .” Here, Goyal establishes an application orchestration system for distributing the tasks for inference. As known in the art, an orchestration system can consist of a broker or act as one. The orchestration system distributes services apart of the established neural network operating system as part of the resources. With that the orchestration system can be seen as being apart or assisting the neural network operating system. Further, Goyal teaches, “multiple task processors for performing inference by processing the tasks input from the broker in the neural processing units connected thereto.” See Goyal in paragraph [0112] where it describes “In at least one embodiment, logic 1015 may include, without limitation, a code and/or data storage 1005 to store backward and/or output weight and/or input/output data corresponding to neurons or layers of a neural network trained and/or used for inferencing in aspects of one or more embodiments.” Here Goyal establishes a logic for performing inference by accepting input corresponding to layers of the neural network which are used for inferencing which consists of an inferencing task or tasks. As mentioned in the previous limitation the orchestration system seen as a broker and the logic are linked together for performing inference. Further, see Goyal in paragraph [0118] describing, “logic 1015 illustrated in FIG. 10A may be used in conjunction with an application-specific integrated circuit (“ASIC”), such as a TensorFlow® Processing Unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp.” Here Goyal explains the logic and how this logic may be used by various different processors which can be seen as task processors as they are used for inferencing tasks . Claim 14: Regarding claim 14, Goyal teaches the limitations in claim 10. Further, Goyal teaches “The apparatus of claim 10, wherein the task processor includes a resource abstraction unit for abstracting a resource for performing neural network inference into a task processor and logically connecting the resource with the task processor;” See Goyal in paragraph [0568] where it describes “In at least one embodiment, application orchestration system 4028 may distribute resources (e.g., services 3920 and/or hardware 3922 ) based on priority paths for different inferencing tasks of AI services 4018 .” Here, Goyal establishes the orchestration system being able to distribute or abstract resources for inference, as known in the art the orchestration system can comprise a resource abstraction unit. Further, see Goyal in paragraph [0576] describing “In at least one embodiment, cloud 4026 may integrate with application orchestration system 4028 leveraging multiple GPUs to enable seamless scaling and load balancing between and among applications and services 3920 .” Here Goyal establishes connecting the orchestration system, which distributes resources, to GPUs, which in previous limitations was established to be able to be seen as a task processor. This makes the orchestration system capable of abstracting a resource into a task processor and logically connecting it with said task processor. Further, Goyal teaches, “a scheduler for setting an execution sequence of tasks based on priority;” See Goyal in paragraph [0568] describing “In at least one embodiment, two or more examples of inferencing using application orchestration system 4028 (e.g., a scheduler, sequencer, and/or asynchronous compute engine) may be available. In at least one embodiment, a first category may include a high priority/low latency path that may achieve higher service level agreements, such as for performing inference on urgent requests during an emergency, or for a radiologist during diagnosis.” Here, explicitly describes the orchestration system which can be a scheduler doing an execution sequence of task(s) based on a priority. Further, Goyal teaches, “a task-processor-side loader for receiving a neural network file used for the neural network application and installing a neural network in a corresponding neural processing unit;” See Goyal in paragraph [0136] where it describes “In at least one embodiment, framework layer 1220 may be, but is not limited to, a type of free and open-source software web application framework such as Apache Spark™ (hereinafter “Spark”) that may utilize distributed file system 1228 for large-scale data processing (e.g., “big data”).” Here Goyal establishes a framework layer utilizing a distributed file system, which as known in the art can act as a loader, to do data processing which requires receiving. Further, see Goyal in paragraph [0133] describing, “In at least one embodiment, node C.R.s 1216(1)-1216(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1218(1)-1218(N) (e.g., dynamic read-only memory, solid state storage or disk drives), network input/output (“NW I/O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc.” Here Goyal establishes nodes consisting of processing units or processors which can act as a neural processing unit . Further, see Goyal in paragraph [0138] describing, “In at least one embodiment, application(s) 1242 included in application layer 1240 may include one or more types of applications used by at least portions of node C.R.s 1216(1)-1216(N) , grouped computing resources 1214 , and/or distributed file system 1228 of framework layer 1220 .” Here Goyal establishes the nodes mentioned by the application which also includes the distributed file system of framework layer, the framework layer with the distributed file system is used to receive data which can consists of a neural network file, which then can be installed for the application into the processing unit as the application uses nodes consisting of processing unit(s) . The nodes consisting of processing units, which was established in earlier limitations, linked to the orchestration system can now have the loader mentioned earlier be seen as a task-processor-side loader. Further, Goyal teaches, “a task-processor-side connector for registering the task processor in the broker.” See Goyal in paragraph [0552] where it describes “In at least one embodiment, cloud platform may integrate an application container clustering system or orchestration system (e.g., KUBERNETES) on multiple GPUs to enable seamless scaling and load balancing.” Here Goyal establishes a cloud platform, which can act as a side connector, integrating or registering an orchestration system, which in previous limitations is established to contain task processors and be a broker, with multiple GPUs, which in previous limitations can be seen as a task processor. Claim 15: Regarding claim 15, Goyal teaches the limitations in claim 10. Further, Goyal teaches “The apparatus of claim 10, wherein the task includes a neural-network-related task including a neural network task and a loader task,” See Goyal in paragraph [0110] where it describes “In at least one embodiment, logic 1015 may include, without limitation, code and/or data storage 1001 to store forward and/or output weight and/or input/output data, and/or other parameters to configure neurons or layers of a neural network trained and/or used for inferencing in aspects of one or more embodiments. In at least one embodiment, logic 1015 may include, or be coupled to code and/or data storage 1001 to store graph code or other software to control timing and/or order, in which weight and/or other parameter information is to be loaded to configure, logic, including integer and/or floating point units (collectively, arithmetic logic units (ALUs)).” Here, Goyal establishes a task for a neural network and a task for loading. Further, Goyal teaches “a system task including an idle task and an exception task,” See Goyal in paragraph [0170] where it describes “In at least one embodiment, one or more of CPU(s) 1306 may implement power management capabilities that include, without limitation, one or more of following features: individual hardware blocks may be clock-gated automatically when idle to save dynamic power; each core clock may be gated when such core is not actively executing instructions due to execution of Wait for Interrupt (“WFI”)/Wait for Event (“WFE”) instructions” Here, Goyal establishes a system that includes an idle task. Further, see Goyal in paragraph [0688] describing “Operations of processes described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. In at least one embodiment, a process such as those processes described herein (or variations and/or combinations thereof) is performed under control of one or more computer systems configured with executable instructions and is implemented as code (e.g., executable instructions, one or more computer programs or one or more applications) executing collectively on one or more processors, by hardware or combinations thereof.” Here Goyal establishes an exception task of a system task here with all operations of the system being performed in order unless indicated implying an exception. An exception task here is being interpreted as a task that is performed differently than usual which is described here with operations being performed in any order unless indicated the case of the operation being performed in a specific order of indication is the exception. Further, Goyal teaches “and a monitor task for monitoring a state of the task processor.” See Goyal in paragraph [0339] where it describes “In at least one embodiment, graphics core 2100 stores, accesses, or loads its own hardware contexts in memory, where a hardware context is a set of data loaded from registers before a process resumes, and where a hardware context can indicate a state of hardware (e.g., state of a GPU).” Here, Goyal establishes a monitoring of a state of a GPU, which was established to be considered a task processor . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 1-2, and 5-9, 13, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Goyal A. et al, (US. Patent Application Publication 20230234233 A1) effectively filed on January 26, 2022, (hereafter Goyal), in view of Kilari V. et al, (US. Patent Application Publication 20240095542 A1) effectively filed on February 25, 2021, (hereafter Kilari) . Claim 1: Regarding claim 1, Goyal teaches “An apparatus for distributed processing of a neural network, comprising: a neural network operating system for abstracting the sub-neural networks into a predetermined number of tasks,” See Goyal in paragraph [0545] describing “In at least one embodiment, data may undergo pre-processing as part of data processing pipeline to prepare data for processing by one or more applications. In at least one embodiment, post-processing may be performed on an output of one or more inferencing tasks or other processing tasks of a pipeline to prepare an output data for a next application and/or to prepare output data for transmission and/or use by a user (e.g., as a response to an inference request). In at least one embodiment, inferencing tasks may be performed by one or more machine learning models, such as trained or deployed neural networks, which may include output models 3916 of training system 3904 .” Here, Goyal establishes a predetermined number of tasks with the one or more tasks being abstracted in response to an inference request of an application. Goyal then establishes that the tasks can be performed by deployed neural networks which can be seen as abstracting sub-neural networks into the predetermined number of tasks, we interpret abstracting neural networks to tasks as updating or changing a model to handle a task which is what is done here. The training system comprising the neural networks here can be seen as the neural network operating system. Further, Goyal teaches “performing inference by distributing the predetermined number of tasks abstracted to correspond to a neural network inference request of at least one application across the multiple neural processing units,” See Goyal in paragraph [0545] describing “In at least one embodiment, data may undergo pre-processing as part of data processing pipeline to prepare data for processing by one or more applications. In at least one embodiment, post-processing may be performed on an output of one or more inferencing tasks or other processing tasks of a pipeline to prepare an output data for a next application and/or to prepare output data for transmission and/or use by a user (e.g., as a response to an inference request). In at least one embodiment, inferencing tasks may be performed by one or more machine learning models, such as trained or deployed neural networks, which may include output models 3916 of training system 3904 .” Here, Goyal establishes performing an inference with returning an inference result, which is considered the output data, of distributed inference to the application in response to an inference request of an application. Goyal then establishes that the tasks, which can be the predetermined number of tasks, can be performed by deployed neural networks, which can make the inference request be seen as a neural network inference request and show an abstraction of the tasks corresponded to this neural network inference request. The training system comprising the neural networks here can be seen as the neural network operating system. Further, see Goyal in paragraph [0109] describing “In at least one embodiment, logic 1015 is used to perform inferencing and/or training operations associated with one or more embodiments. In at least one embodiment, logic 1015 is inference and/or training logic. Details regarding logic 1015 are provided below in conjunction with FIGS. 10A and/or 10B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and/or firmware logic to provide functionality or operations described herein, wherein logic may be, collectively or individually, embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system-on-chip (SoC), or one or processors (e.g., CPU, GPU).” Here Goyal establishes the operations in relation to inference or training logic being done across multiple processing units with one or more processors. Further, Goyal teaches “returning an inference result to the application.” See Goyal in paragraph [0545] describing “In at least one embodiment, data may undergo pre-processing as part of data processing pipeline to prepare data for processing by one or more applications. In at least one embodiment, post-processing may be performed on an output of one or more inferencing tasks or other processing tasks of a pipeline to prepare an output data for a next application and/or to prepare output data for transmission and/or use by a user (e.g., as a response to an inference request). In at least one embodiment, inferencing tasks may be performed by one or more machine learning models, such as trained or deployed neural networks, which may include output models 3916 of training system 3904 .” Here, Goyal establishes returning an inference result, which is considered the output data, of distributed inference to the application in response to an inference request of an application. However, Goyal did not explicitly teach “a neural network model compiler for segmenting a neural network into a predetermined number of sub-neural networks; two or more neural processing units” In the same field of art, Kilari teaches, “a neural network model compiler for segmenting a neural network into a predetermined number of sub-neural networks;” See Kilari in paragraph [0047] where it describes “In some aspects of the present disclosure, a neural network is split into sub-neural networks and runs on multiple AIIA devices, in which the same instances of the sub-neural networks are run on multiple AIIA devices by dynamically routing the data flow.” Here Kilari establishes the segmenting of a neural network into sub-neural networks. Further, see Kilari in paragraph [0045] describing, “Nevertheless, a scheduling policy is important for running the neural networks in a multi-device mode, in which the neural networks are split into sub-neural networks. In operation, a compiler generates sub-neural networks that run independently on the device.” Here Kilari establishes the segmenting of the sub-neural networks being done by a compiler . Further, Kilari teaches, “two or more neural processing units;” See Kilari in paragraph [0046] where it describes “In operation, power consumption of AIIA devices depends on the load of the AIIA devices. For example, massive neural networks involve co-processors to perform floating point operations as well as matrix/vector operations.” Here, the co-processors that are involved with neural networks Kilari establishes can be seen as the two or more neural processing units. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the base reference of Goyal with the teachings of Kilari by using Goyal’s teachings of abstracting neural networks into inference tasks across multiple neural processing units and returning an inference result, and incorporate with Kilari’s teachings of segmenting a neural network into sub-neural networks. One of ordinary skill in the art would be motivated to do so because by integrating Kilari’s frameworks into the methods of Goyal, which are both in relation to an apparatus or machine using a method for distributed processing of neural networks, one of ordinary skill in the art would bring “A method for accelerating machine learning on a computing device” (Kilari, paragraph [0005]) and “A method for dynamic inference routing of accelerated machine learning on a computing device” (Kilari, paragraph [0007]). Claim 2: Regarding claim 2, Goyal in view of Kilari teaches the limitations in claim 1. Further, Goyal teaches “The apparatus of claim 1, wherein the neural network operating system includes a broker for distributing the predetermined number of tasks, abstracted to correspond to the neural network inference request of the at least one neural network application, across the multiple neural processing units;” See Goyal in paragraph [0545] describing “In at least one embodiment, data may undergo pre-processing as part of data processing pipeline to prepare data for processing by one or more applications. In at least one embodiment, post-processing may be performed on an output of one or more inferencing tasks or other processing tasks of a pipeline to prepare an output data for a next application and/or to prepare output data for transmission and/or use by a user (e.g., as a response to an inference request). In at least one embodiment, inferencing tasks may be performed by one or more machine learning models, such as trained or deployed neural networks, which may include output models 3916 of training system 3904 .” Here, Goyal establishes a predetermined number of tasks with the one or more tasks being abstracted in response to an inference request of an application. Goyal then establishes that the tasks can be performed by deployed neural networks which can be seen as abstracting sub-neural networks into the predetermined number of tasks, we interpret abstracting neural networks to tasks as updating or changing a model to handle a task which is what is done here. The training system comprising the neural networks here can be seen as the neural network operating system. Further, see Goyal in paragraph [0109] describing “In at least one embodiment, logic 1015 is used to perform inferencing and/or training operations associated with one or more embodiments. In at least one embodiment, logic 1015 is inference and/or training logic. Details regarding logic 1015 are provided below in conjunction with FIGS. 10A and/or 10B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and/or firmware logic to provide functionality or operations described herein, wherein logic may be, collectively or individually, embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system-on-chip (SoC), or one or processors (e.g., CPU, GPU).” Here Goyal establishes the operations being done across multiple processing units with one or more processors. Further, see Goyal in paragraph [0551] where it describes “In at least one embodiment, hardware 3922 may include GPUs, CPUs, graphics cards, an AI/deep learning system (e.g., an AI supercomputer, such as NVIDIA's DGX supercomputer system), a cloud platform, or a combination thereof. In at least one embodiment, different types of hardware 3922 may be used to provide efficient, purpose-built support for software 3918 and services 3920 in deployment system 3906 .” Here, Goyal establishes software and services of the deployment system said to be considered a neural network operating system in previous limitations. Further, see Goyal in paragraph [0568] where it describes “In at least one embodiment, application orchestration system 4028 may distribute resources (e.g., services 3920 and/or hardware 3922 ) based on priority paths for different inferencing tasks of AI services 4018 .” Here, Goyal establishes an application orchestration system for distributing the tasks for inference. As known in the art, an orchestration system can consist of a broker or act as one. The orchestration system distributes services apart of the established neural network operating system as part of the resources. With that the orchestration system can be seen as being apart or assisting the neural network operating system. Further, Goyal teaches, “task processors for performing inference by processing the tasks input from the broker in the neural processing units” See Goyal in paragraph [0112] where it describes “In at least one embodiment, logic 1015 may include, without limitation, a code and/or data storage 1005 to store backward and/or output weight and/or input/output data corresponding to neurons or layers of a neural network trained and/or used for inferencing in aspects of one or more embodiments.” Here Goyal establishes a logic for performing inference by accepting input corresponding to layers of the neural network which are used for inferencing which consists of an inferencing task or tasks. As mentioned in the previous limitation the orchestration system seen as a broker and the logic are linked together for performing inference. Further, see Goyal in paragraph [0118] describing, “logic 1015 illustrated in FIG. 10A may be used in conjunction with an application-specific integrated circuit (“ASIC”), such as a TensorFlow® Processing Unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp.” Here Goyal explains the logic and how this logic may be used by various different processors which can be seen as task processors as they are used for inferencing tasks . Claim 5: Regarding claim 5, Goyal in view of Kilari teaches the limitations in claim 2. Further, Goyal teaches “The apparatus of claim 2, wherein: control messages are transmitted and received between the neural network application and the broker or between the broker and the task processor,” See Goyal in paragraph [0556] where it describes “In at least one embodiment, communication between facilities and components of system 4000 (e.g., for transmitting inference requests, for receiving results of inference requests, etc.) may be communicated over a data bus or data busses, wireless data protocols (Wi-Fi), wired data protocols (e.g., Ethernet), etc.” Here, Goyal establishes communication and transmission of an inference request. The communication can be seen as control messages. Further, see Goyal in paragraph [0566] describing “In at least one embodiment, communication, and cooperation between different containers or applications may be aided by pipeline manager 4012 and application orchestration system 4028 . In at least one embodiment, so long as an expected input and/or output of each container or application is known by a system (e.g., based on constructs of applications or containers), application orchestration system 4028 and/or pipeline manager 4012 may facilitate communication among and between, and sharing of resources among and between, each of applications or containers” Here Goyal establishes the communication between containers and the application with it aided by an orchestration system which can be seen as a broker as mentioned priorly. Further, Goyal teaches “input/output data required for inference is transmitted and received between the neural network application and the task processor.” See Goyal in paragraph [0566] describing “In at least one embodiment, communication, and cooperation between different containers or applications may be aided by pipeline manager 4012 and application orchestration system 4028 . In at least one embodiment, so long as an expected input and/or output of each container or application is known by a system (e.g., based on constructs of applications or containers), application orchestration system 4028 and/or pipeline manager 4012 may facilitate communication among and between, and sharing of resources among and between, each of applications or containers” Here Goyal establishes the communication between containers and the application with it aided by an orchestration system which can be seen as a broker as mentioned priorly. This also establishes the input/output data is communicated. Further, see Goyal in paragraph [0576] describing, “In at least one embodiment, cloud 4026 may include a GPU-accelerated infrastructure (e.g., NVIDIA's NGC) that may provide a GPU-optimized platform for executing processing tasks of system 4000 . In at least one embodiment, cloud 4026 may include an AI system(s) 4024 for performing one or more of AI-based tasks of system 4000 (e.g., as a hardware abstraction and scaling platform). In at least one embodiment, cloud 4026 may integrate with application orchestration system 4028 leveraging multiple GPUs to enable seamless scaling and load balancing between and among applications and services 3920 .” Here, Goyal further establishes the system for the transmission and communication, also establishing a connection of the orchestration system leveraging multiple GPUs, which established in previous limitations to be a task processor, which takes in the input/output data. Claim 6: Regarding claim 6, Goyal teaches the limitations in claim 2. Further, Goyal teaches “The apparatus of claim 2, wherein the broker includes a task abstraction unit for generating neural network tasks by…;” See Goyal in paragraph [0565] where it describes “In at least one embodiment, although illustrated as included in software 3918 , this is not intended to be limiting, and in some examples (e.g., as illustrated in FIG. 41 ) pipeline manager 4012 may be included in services 3920 . In at least one embodiment, application orchestration system 4028 (e.g., Kubernetes, DOCKER, etc.) may include a container orchestration system that may group applications into containers as logical units for coordination, management, scaling, and deployment.” Here, Goyal establishes the orchestration system, established in previous limitations to be a broker, generating various types of tasks using a unit which can be an abstraction unit. The applications into containers as logical units is being considered here as a task abstraction unit, and this unit is generating tasks such as coordination and management. Further, see Goyal in paragraph [0568] where it describes “In at least one embodiment, AI services 4018 may leverage AI system 4024 to execute machine learning model(s) (e.g., neural networks, such as CNNs) for segmentation, reconstruction, object detection, feature detection, classification, and/or other inferencing tasks.” Here, Goyal establishes AI services using neural networks for inferencing tasks which can be seen as neural network tasks. Further, see Goyal in paragraph [0568] where it describes “In at least one embodiment, application orchestration system 4028 may distribute resources (e.g., services 3920 and/or hardware 3922 ) based on priority paths for different inferencing tasks of AI services 4018 .” Here, Goyal establishes the orchestration system, further generating tasks of the AI services which can now have the broker which uses abstraction unit generating neural network tasks. Further, Goyal teaches, “a task distributor for distributing each of the neural network tasks to one of the multiple task processors;” See Goyal in paragraph [0545] describing “In at least one embodiment, inferencing tasks may be performed by one or more machine learning models, such as trained or deployed neural networks, which may include output models 3916 of training system 3904 .” Here, Goyal establishes tasks being distributed/assigned to neural networks, the task distributor can be seen as the training system here. Further, see Goyal in paragraph [0109] describing “In at least one embodiment, logic 1015 is used to perform inferencing and/or training operations associated with one or more embodiments. In at least one embodiment, logic 1015 is inference and/or training logic. Details regarding logic 1015 are provided below in conjunction with FIGS. 10A and/or 10B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and/or firmware logic to provide functionality or operations described herein, wherein logic may be, collectively or individually, embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system-on-chip (SoC), or one or processors (e.g., CPU, GPU).” Here Goyal establishes the operations being done across multiple processing units with one or more processors . Further, Goyal teaches, “a broker-side loader for loading a neural network file used for the neural network application in advance into the neural processing unit;” See Goyal in paragraph [0136] where it describes “In at least one embodiment, framework layer 1220 may be, but is not limited to, a type of free and open-source software web application framework such as Apache Spark™ (hereinafter “Spark”) that may utilize distributed file system 1228 for large-scale data processing (e.g., “big data”).” Here Goyal establishes a framework layer utilizing a distributed file system, which as known in the art can act as a broker-side loader, to do data processing or loading, and loading in advance. The distributed file system in this embodiment is being interpreted as a broker-side loader to load the neural network file in advance for use by the application, the neural network application in his case would be framework layer such as Apache Spark. Further, see Goyal in paragraph [0133] describing, “In at least one embodiment, node C.R.s 1216(1)-1216(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1218(1)-1218(N) (e.g., dynamic read-only memory, solid state storage or disk drives), network input/output (“NW I/O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc.” Here Goyal establishes nodes consisting of processing units or processors which can act as a neural processing unit . Further, see Goyal in paragraph [0138] describing, “In at least one embodiment, application(s) 1242 included in application layer 1240 may include one or more types of applications used by at least portions of node C.R.s 1216(1)-1216(N) , grouped computing resources 1214 , and/or distributed file system 1228 of framework layer 1220 .” Here Goyal establishes the nodes mentioned by the application which also includes the distributed file system of framework layer, the framework layer with the distributed file system is used to load data which can consists of a neural network file, which then can be loaded in advance for the application into the processing unit as the application uses nodes consisting of processing unit(s) . Further, Goyal teaches, “a broker-side connector for connecting the broker with the task processor” See Goyal in paragraph [0552] where it describes “In at least one embodiment, cloud platform may integrate an application container clustering system or orchestration system (e.g., KUBERNETES) on multiple GPUs to enable seamless scaling and load balancing.” Here Goyal establishes a cloud platform, which can act as a broker-side connector, integrating or connecting an orchestration system, which in previous limitations is to be seen as a broker, with multiple GPUs, which in previous limitations can be seen as a task processor. However, Goyal did not explicitly teach “abstracting the sub-neural networks acquired by segmenting the neural network;” In the same field of art, Kilari teaches, “abstracting the sub-neural networks acquired by segmenting a neural network;” See Kilari in paragraph [0047] where it describes “In some aspects of the present disclosure, a neural network is split into sub-neural networks and runs on multiple AIIA devices, in which the same instances of the sub-neural networks are run on multiple AIIA devices by dynamically routing the data flow.” Here Kilari establishes the segmenting of a neural network into sub-neural networks and abstracting it by assigning it to multiple AIIA devices . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the base reference of Goyal with the teachings of Kilari by using Goyal’s teachings of abstracting neural networks into inference tasks across multiple neural processing units and returning an inference result, and incorporate with Kilari’s teachings of segmenting a neural network into sub-neural networks. One of ordinary skill in the art would be motivated to do so because by integrating Kilari’s frameworks into the methods of Goyal, which are both in relation to an apparatus or machine using a method for distributed processing of neural networks, one of ordinary skill in the art would bring “A method for accelerating machine learning on a computing device” (Kilari, paragraph [0005]) and “A method for dynamic inference routing of accelerated machine learning on a computing device” (Kilari, paragraph [0007]). Claim 7: Regarding claim 7, Goyal teaches the limitations in claim 2. Further, Goyal teaches “The apparatus of claim 2, wherein the task processor includes a resource abstraction unit for abstracting a resource for performing neural network inference into a task processor and logically connecting the resource with the task processor;” See Goyal in paragraph [0568] where it describes “In at least one embodiment, application orchestration system 4028 may distribute resources (e.g., services 3920 and/or hardware 3922 ) based on priority paths for different inferencing tasks of AI services 4018 .” Here, Goyal establishes the orchestration system being able to distribute or abstract resources for inference, as known in the art the orchestration system can comprise a resource abstraction unit. Further, see Goyal in paragraph [0576] describing “In at least one embodiment, cloud 4026 may integrate with application orchestration system 4028 leveraging multiple GPUs to enable seamless scaling and load balancing between and among applications and services 3920 .” Here Goyal establishes connecting the orchestration system, which distributes resources, to GPUs, which in previous limitations was established to be able to be seen as a task processor. This makes the orchestration system capable of abstracting a resource into a task processor and logically connecting it with said task processor. Further, Goyal teaches, “a scheduler for setting an execution sequence of tasks based on priority;” See Goyal in paragraph [0568] describing “In at least one embodiment, two or more examples of inferencing using application orchestration system 4028 (e.g., a scheduler, sequencer, and/or asynchronous compute engine) may be available. In at least one embodiment, a first category may include a high priority/low latency path that may achieve higher service level agreements, such as for performing inference on urgent requests during an emergency, or for a radiologist during diagnosis.” Here, explicitly describes the orchestration system which can be a scheduler doing an execution sequence of task(s) based on a priority. Further, Goyal teaches, “a task-processor-side loader for receiving a neural network file used for the neural network application and installing a neural network in a corresponding neural processing unit;” See Goyal in paragraph [0136] where it describes “In at least one embodiment, framework layer 1220 may be, but is not limited to, a type of free and open-source software web application framework such as Apache Spark™ (hereinafter “Spark”) that may utilize distributed file system 1228 for large-scale data processing (e.g., “big data”).” Here Goyal establishes a framework layer utilizing a distributed file system, which as known in the art can act as a loader, to do data processing which requires receiving. Further, see Goyal in paragraph [0133] describing, “In at least one embodiment, node C.R.s 1216(1)-1216(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1218(1)-1218(N) (e.g., dynamic read-only memory, solid state storage or disk drives), network input/output (“NW I/O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc.” Here Goyal establishes nodes consisting of processing units or processors which can act as a neural processing unit . Further, see Goyal in paragraph [0138] describing, “In at least one embodiment, application(s) 1242 included in application layer 1240 may include one or more types of applications used by at least portions of node C.R.s 1216(1)-1216(N) , grouped computing resources 1214 , and/or distributed file system 1228 of framework layer 1220 .” Here Goyal establishes the nodes mentioned by the application which also includes the distributed file system of framework layer, the framework layer with the distributed file system is used to receive data which can consists of a neural network file, which then can be installed for the application into the processing unit as the application uses nodes consisting of processing unit(s) . The nodes consisting of processing units, which was established in earlier limitations, linked to the orchestration system can now have the loader mentioned earlier be seen as a task-processor-side loader. Further, Goyal teaches, “a task-processor-side connector for registering the task processor in the broker.” See Goyal in paragraph [0552] where it describes “In at least one embodiment, cloud platform may integrate an application container clustering system or orchestration system (e.g., KUBERNETES) on multiple GPUs to enable seamless scaling and load balancing.” Here Goyal establishes a cloud platform, which can act as a side connector, integrating or registering an orchestration system, which in previous limitations is established to contain task processors and be a broker, with multiple GPUs, which in previous limitations can be seen as a task processor. Claim 8: Regarding claim 8, Goyal teaches the limitations in claim 7. Further, Goyal teaches “The apparatus of claim 7, wherein the task includes a neural-network-related task including a neural network task and a loader task,” See Goyal in paragraph [0110] where it describes “In at least one embodiment, logic 1015 may include, without limitation, code and/or data storage 1001 to store forward and/or output weight and/or input/output data, and/or other parameters to configure neurons or layers of a neural network trained and/or used for inferencing in aspects of one or more embodiments. In at least one embodiment, logic 1015 may include, or be coupled to code and/or data storage 1001 to store graph code or other software to control timing and/or order, in which weight and/or other parameter information is to be loaded to configure, logic, including integer and/or floating point units (collectively, arithmetic logic units (ALUs)).” Here, Goyal establishes a task for a neural network and a task for loading. Further, Goyal teaches “a system task including an idle task and an exception task,” See Goyal in paragraph [0170] where it describes “In at least one embodiment, one or more of CPU(s) 1306 may implement power management capabilities that include, without limitation, one or more of following features: individual hardware blocks may be clock-gated automatically when idle to save dynamic power; each core clock may be gated when such core is not actively executing instructions due to execution of Wait for Interrupt (“WFI”)/Wait for Event (“WFE”) instructions” Here, Goyal establishes a system that includes an idle task. Further, see Goyal in paragraph [0688] describing “Operations of processes described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. In at least one embodiment, a process such as those processes described herein (or variations and/or combinations thereof) is performed under control of one or more computer systems configured with executable instructions and is implemented as code (e.g., executable instructions, one or more computer programs or one or more applications) executing collectively on one or more processors, by hardware or combinations thereof.” Here Goyal establishes an exception task of a system task here with all operations of the system being performed in order unless indicated implying an exception. An exception task here is being interpreted as a task that is performed differently than usual which is described here with operations being performed in any order unless indicated the case of the operation being performed in a specific order of indication is the exception. Further, Goyal teaches “and a monitor task for monitoring a state of the task processor.” See Goyal in paragraph [0339] where it describes “In at least one embodiment, graphics core 2100 stores, accesses, or loads its own hardware contexts in memory, where a hardware context is a set of data loaded from registers before a process resumes, and where a hardware context can indicate a state of hardware (e.g., state of a GPU).” Here, Goyal establishes a monitoring of a state of a GPU, which was established to be considered a task processor. Claim 9: Regarding claim 9, Goyal in view of Kilari teaches the limitations in claim 2. Further, Goyal teaches “The apparatus of claim 2, wherein: a task processor includes a neural network object installed by loading a specific neural network,” See Goyal in paragraph [0128] where it describes “In at least one embodiment, a model optimizer optimizes neural network models for execution on various devices and/or processing units, such as a GPU, CPU, PPU, GPGPU, and/or variations thereof.” Here, Goyal establishes a model optimizer which can be seen as a neural network object to optimize neural network models for execution on various devices which requires loading a neural network and installing. It should be noted the optimizer utilizes a GPGPU which can be seen as the task processor. Further, Goyal teaches “the neural network object is an interface that is connected when a neural network task is executed.” See Goyal in paragraph [0128] where it describes “In at least one embodiment, a model optimizer optimizes neural network models for execution on various devices and/or processing units, such as a GPU, CPU, PPU, GPGPU, and/or variations thereof.” Here, once again Goyal establishes a model optimizer which can be seen as a neural network object to optimize neural network models for execution on various devices, using a GPGPU. Further, see Goyal in paragraph [0344] describing “In at least one embodiment, GPGPU 1630 can be linked directly to other instances of GPGPU 1630 to create a multi-GPU cluster to improve training speed for deep neural networks. In at least one embodiment, GPGPU 1630 includes a host interface 1632 to enable a connection with a host processor.” Here Goyal establishes that the GPGPU can consist of an interface. The GPGPU already handles neural network execution and improving training speed of a neural network is an example of a task that is to be executed. Claim 13: Regarding claim 13, Goyal teaches the limitations in claim 10. Further, Goyal teaches “The apparatus of claim 10, wherein the broker includes a task abstraction unit for generating neural network tasks by…;” See Goyal in paragraph [0565] where it describes “In at least one embodiment, although illustrated as included in software 3918 , this is not intended to be limiting, and in some examples (e.g., as illustrated in FIG. 41 ) pipeline manager 4012 may be included in services 3920 . In at least one embodiment, application orchestration system 4028 (e.g., Kubernetes, DOCKER, etc.) may include a container orchestration system that may group applications into containers as logical units for coordination, management, scaling, and deployment.” Here, Goyal establishes the orchestration system, established in previous limitations to be a broker, generating various types of tasks using a unit which can be an abstraction unit. The applications into containers as logical units is being considered here as a task abstraction unit, and this unit is generating tasks such as coordination and management. Further, see Goyal in paragraph [0568] where it describes “In at least one embodiment, AI services 4018 may leverage AI system 4024 to execute machine learning model(s) (e.g., neural networks, such as CNNs) for segmentation, reconstruction, object detection, feature detection, classification, and/or other inferencing tasks.” Here, Goyal establishes AI services using neural networks for inferencing tasks which can be seen as neural network tasks. Further, see Goyal in paragraph [0568] where it describes “In at least one embodiment, application orchestration system 4028 may distribute resources (e.g., services 3920 and/or hardware 3922 ) based on priority paths for different inferencing tasks of AI services 4018 .” Here, Goyal establishes the orchestration system, further generating tasks of the AI services which can now have the broker which uses abstraction unit generating neural network tasks. Further, Goyal teaches, “a task distributor for distributing each of the neural network tasks to one of the multiple task processors;” See Goyal in paragraph [0545] describing “In at least one embodiment, inferencing tasks may be performed by one or more machine learning models, such as trained or deployed neural networks, which may include output models 3916 of training system 3904 .” Here, Goyal establishes tasks being distributed/assigned to neural networks, the task distributor can be seen as the training system here. Further, see Goyal in paragraph [0109] describing “In at least one embodiment, logic 1015 is used to perform inferencing and/or training operations associated with one or more embodiments. In at least one embodiment, logic 1015 is inference and/or training logic. Details regarding logic 1015 are provided below in conjunction with FIGS. 10A and/or 10B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and/or firmware logic to provide functionality or operations described herein, wherein logic may be, collectively or individually, embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system-on-chip (SoC), or one or processors (e.g., CPU, GPU).” Here Goyal establishes the operations being done across multiple processing units with one or more processors . Further, Goyal teaches, “a broker-side loader for loading a neural network file used for the neural network application in advance into the neural processing unit;” See Goyal in paragraph [0136] where it describes “In at least one embodiment, framework layer 1220 may be, but is not limited to, a type of free and open-source software web application framework such as Apache Spark™ (hereinafter “Spark”) that may utilize distributed file system 1228 for large-scale data processing (e.g., “big data”).” Here Goyal establishes a framework layer utilizing a distributed file system, which as known in the art can act as a broker-side loader, to do data processing or loading, and loading in advance. The distributed file system in this embodiment is being interpreted as a broker-side loader to load the neural network file in advance for use by the application, the neural network application in his case would be framework layer such as Apache Spark. Further, see Goyal in paragraph [0133] describing, “In at least one embodiment, node C.R.s 1216(1)-1216(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1218(1)- 1218(N) (e.g., dynamic read-only memory, solid state storage or disk drives), network input/output (“NW I/O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc.” Here Goyal establishes nodes consisting of processing units or processors which can act as a neural processing unit . Further, see Goyal in paragraph [0138] describing, “In at least one embodiment, application(s) 1242 included in application layer 1240 may include one or more types of applications used by at least portions of node C.R.s 1216(1)-1216(N) , grouped computing resources 1214 , and/or distributed file system 1228 of framework layer 1220 .” Here Goyal establishes the nodes mentioned by the application which also includes the distributed file system of framework layer, the framework layer with the distributed file system is used to load data which can consists of a neural network file, which then can be loaded in advance for the application into the processing unit as the application uses nodes consisting of processing unit(s) . Further, Goyal teaches, “a broker-side connector for connecting the broker with the task processor” See Goyal in paragraph [0552] where it describes “In at least one embodiment, cloud platform may integrate an application container clustering system or orchestration system (e.g., KUBERNETES) on multiple GPUs to enable seamless scaling and load balancing.” Here Goyal establishes a cloud platform, which can act as a broker-side connector, integrating or connecting an orchestration system, which in previous limitations is to be seen as a broker, with multiple GPUs, which in previous limitations can be seen as a task processor. However, Goyal did not explicitly teach “abstracting the sub-neural networks acquired by segmenting the neural network;” In the same field of art, Kilari teaches, “abstracting the sub-neural networks acquired by segmenting a neural network;” See Kilari in paragraph [0047] where it describes “In some aspects of the present disclosure, a neural network is split into sub-neural networks and runs on multiple AIIA devices, in which the same instances of the sub-neural networks are run on multiple AIIA devices by dynamically routing the data flow.” Here Kilari establishes the segmenting of a neural network into sub-neural networks and abstracting it by assigning it to multiple AIIA devices . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the base reference of Goyal with the teachings of Kilari by using Goyal’s teachings of abstracting neural networks into inference tasks across multiple neural processing units and returning an inference result, and incorporate with Kilari’s teachings of segmenting a neural network into sub-neural networks. One of ordinary skill in the art would be motivated to do so because by integrating Kilari’s frameworks into the methods of Goyal, which are both in relation to an apparatus or machine using a method for distributed processing of neural networks, one of ordinary skill in the art would bring “A method for accelerating machine learning on a computing device” (Kilari, paragraph [0005]) and “A method for dynamic inference routing of accelerated machine learning on a computing device” (Kilari, paragraph [0007]). Claim 16: Regarding claim 16, Goyal teaches “A method for distributed processing of a neural network, comprising: generating a predetermined number of tasks by…;” See Goyal in paragraph [0063] where it describes “In at least one embodiment, object placement logic 122 include perception logic 126 , planning logic 128 , and movement logic 130 . In at least one embodiment, logic (e.g., object placement logic 122 , perception logic 126 , planning logic 128 , and/or movement logic 130 ) refers to any combination of software logic, hardware logic, and/or firmware logic to provide functionality or operations described herein” Here, Goyal establishes a logic doing operations. Further, see Goyal in paragraph [0545] describing “In at least one embodiment, data may undergo pre-processing as part of data processing pipeline to prepare data for processing by one or more applications. In at least one embodiment, post-processing may be performed on an output of one or more inferencing tasks or other processing tasks of a pipeline to prepare an output data for a next application and/or to prepare output data for transmission and/or use by a user (e.g., as a response to an inference request). In at least one embodiment, inferencing tasks may be performed by one or more machine learning models, such as trained or deployed neural networks, which may include output models 3916 of training system 3904 .” Here, Goyal establishes returning an inference result of distributed inference to the application, which is a method of distributed processing of a neural network, and establishes a predetermined number of tasks with the one or more tasks being abstracted to a request of an application. Goyal then establishes that the tasks can be performed by deployed neural networks which can be seen as abstracting sub-neural networks into the predetermined number of tasks. Further, Goyal teaches, “delivering input data of an application, for which inference is requested, to a neural network process when the neural network process for controlling an execution sequence and input/output of tasks generated by the application is executed;” See Goyal in paragraph [0566] describing “In at least one embodiment, communication, and cooperation between different containers or applications may be aided by pipeline manager 4012 and application orchestration system 4028 . In at least one embodiment, so long as an expected input and/or output of each container or application is known by a system (e.g., based on constructs of applications or containers), application orchestration system 4028 and/or pipeline manager 4012 may facilitate communication among and between, and sharing of resources among and between, each of applications or containers” Here Goyal establishes the communication between containers and the application with it aided by an orchestration system. This also establishes the input/output data is communicated which can be input data of an application and input/output tasks. Further, see Goyal in paragraph [0568] describing “In at least one embodiment, two or more examples of inferencing using application orchestration system 4028 (e.g., a scheduler, sequencer, and/or asynchronous compute engine) may be available. In at least one embodiment, a first category may include a high priority/low latency path that may achieve higher service level agreements, such as for performing inference on urgent requests during an emergency, or for a radiologist during diagnosis.” Here, explicitly describes the orchestration system which can be a scheduler doing an execution sequence of task(s) which are established to be generated by application as they are known by the system at this point . In this embodiment utilizing the orchestration system for inferencing can be seen as the neural network process. Further, Goyal teaches, “executing neural network tasks within the neural network process in the neural network processors, into which the respective neural network tasks are loaded, according to the execution sequence;” See Goyal in paragraph [0568] describing “In at least one embodiment, two or more examples of inferencing using application orchestration system 4028 (e.g., a scheduler, sequencer, and/or asynchronous compute engine) may be available. In at least one embodiment, a first category may include a high priority/low latency path that may achieve higher service level agreements, such as for performing inference on urgent requests during an emergency, or for a radiologist during diagnosis.” Here, Goyal establishes executing tasks according to an execution sequence. Further, see Goyal in paragraph [0552] describing, “In at least one embodiment, cloud platform may further include GPU processing for GPU-optimized execution of deep learning tasks, machine learning tasks, or other computing tasks. In at least one embodiment, cloud platform (e.g., NVIDIA's NGC) may be executed using an AI/deep learning supercomputer(s) and/or GPU-optimized software (e.g., as provided on NVIDIA's DGX systems) as a hardware abstraction and scaling platform. In at least one embodiment, cloud platform may integrate an application container clustering system or orchestration system (e.g., KUBERNETES) on multiple GPUs to enable seamless scaling and load balancing.” Here, Goyal establishes a connection with machine learning tasks which can be seen as neural network tasks executed by a cloud associated with an orchestration system which loads. The cloud consists of processors which can be neural network processors. Further, Goyal teaches, “delivering output data of the neural network process to the application.” See Goyal in paragraph [0566] describing “In at least one embodiment, communication, and cooperation between different containers or applications may be aided by pipeline manager 4012 and application orchestration system 4028 . In at least one embodiment, so long as an expected input and/or output of each container or application is known by a system (e.g., based on constructs of applications or containers), application orchestration system 4028 and/or pipeline manager 4012 may facilitate communication among and between, and sharing of resources among and between, each of applications or containers” Here Goyal establishes the communication between containers and the application in which input/output data is communicated which can be output data to an application. In previous limitations this embodiment is established to have a neural network process. However, Goyal did not explicitly teach “segmenting a large-scale neural network into a predetermined number of parts; loading neural network partitions into task processors respectively connected to multiple neural processing units;” In the same field of art, Kilari teaches, “segmenting a large-scale neural network into a predetermined number of parts;” See Kilari in paragraph [0047] where it describes “In some aspects of the present disclosure, a neural network is split into sub-neural networks and runs on multiple AIIA devices, in which the same instances of the sub-neural networks are run on multiple AIIA devices by dynamically routing the data flow.” Here Kilari establishes the segmenting of a neural network into sub-neural networks which can be predetermined and the sub-neural networks can be parts. Further, Kilari teaches, “loading neural network partitions into task processors respectively connected to multiple neural processing units;” See Kilari in paragraph [0087] where it describes “runtime software can load the sub-neural networks to the AIIA devices.” Here, Kilari teaches loading the sub-neural networks which can be neural network partitions into the AIIA devices. Further, See Kilari in paragraph [0042] where it describes “some aspects of the present disclosure split a large neural network into multiple, separate artificial intelligence (AI) inference accelerators (AIIAs). Each of the separate AI inference accelerators may be implemented in a separate system-on-chip (SoC).” Here, Kilari establishes the AIIAs being implemented on a SoC. Further, See Kilari in paragraph [0048] where it describes “FIG. 1 illustrates an example implementation of a system-on-chip (SoC) 100 , which may include a central processing unit (CPU) 102 or multi-core CPUs” Here, Kilari teaches the SoC comprising of multiple multi-core central processing units which can be seen as neural processing units. As known I the art as well SoC’s typically contain NPUs. The task processors can be the multiple neural processing units as they are connected to task processor. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the base reference of Goyal with the teachings of Kilari by using Goyal’s teachings of abstracting neural networks into inference tasks across multiple neural processing units and returning an inference result, and incorporate with Kilari’s teachings of segmenting a neural network into sub-neural networks. One of ordinary skill in the art would be motivated to do so because by integrating Kilari’s frameworks into the methods of Goyal, which are both in relation to an apparatus or machine using a method for distributed processing of neural networks, one of ordinary skill in the art would bring “A method for accelerating machine learning on a computing device” (Kilari, paragraph [0005]) and “A method for dynamic inference routing of accelerated machine learning on a computing device” (Kilari, paragraph [0007]). Claim 17: Regarding claim 17, Goyal in view of Kilari teaches the limitations in claim 16. Goyal did not explicitly teach “The apparatus of claim 16, wherein the neural network partition is in a form of file, and includes a descriptor for describing the neural network and a kernel.” However, Kilari teaches “The apparatus of claim 16, wherein the neural network partition is in a form of file,” See Kilari in paragraph [0056] where it describes “One type of convolutional neural network is a deep convolutional network (DCN).” Here, Goyal establishes a deep convolutional network (DCN). Further, see Goyal in paragraph [0057] describing “The DCN 200 may be trained with supervised learning. During training, the DCN 200 may be presented with an image, such as the image 226 of a speed limit sign, and a forward pass may then be computed to produce an output 222 . The DCN 200 may include a feature extraction section and a classification section. Upon receiving the image 226 , a convolutional layer 232 may apply convolutional kernels (not shown) to the image 226 to generate a first set of feature maps 218 . As an example, the convolutional kernel for the convolutional layer 232 may be a 5×5 kernel that generates 28×28 feature maps. In the present example, because four different convolutional kernels were applied to the image 226 at the convolutional layer 232 , four different feature maps are generated in the first set of feature maps 218 . The convolutional kernels may also be referred to as filters or convolutional filters.” Here Goyal establishes a kernel with the image being presented to the DCN and the convolutional kernel. The neural network partition here is the image which is known to always be in the form of a file. Further, Kilari teaches “includes a descriptor for describing the neural network and a kernel.” See Kilari in paragraph [0056] where it describes “One type of convolutional neural network is a deep convolutional network (DCN).” Here, Goyal establishes a deep convolutional network (DCN). Further, see Goyal in paragraph [0057] describing “The DCN 200 may be trained with supervised learning. During training, the DCN 200 may be presented with an image, such as the image 226 of a speed limit sign, and a forward pass may then be computed to produce an output 222 . The DCN 200 may include a feature extraction section and a classification section. Upon receiving the image 226 , a convolutional layer 232 may apply convolutional kernels (not shown) to the image 226 to generate a first set of feature maps 218 . As an example, the convolutional kernel for the convolutional layer 232 may be a 5×5 kernel that generates 28×28 feature maps. In the present example, because four different convolutional kernels were applied to the image 226 at the convolutional layer 232 , four different feature maps are generated in the first set of feature maps 218 . The convolutional kernels may also be referred to as filters or convolutional filters.” Here Goyal establishes the DCN acting as a descriptor for generating or describing neural network and a kernel with the image being presented to the DCN and the convolutional kernel. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the base reference of Goyal with the teachings of Kilari by using Goyal’s teachings of abstracting neural networks into inference tasks across multiple neural processing units and returning an inference result, and incorporate with Kilari’s teachings of segmenting a neural network into sub-neural networks. One of ordinary skill in the art would be motivated to do so because by integrating Kilari’s frameworks into the methods of Goyal, which are both in relation to an apparatus or machine using a method for distributed processing of neural networks, one of ordinary skill in the art would bring “A method for accelerating machine learning on a computing device” (Kilari, paragraph [0005]) and “A method for dynamic inference routing of accelerated machine learning on a computing device” (Kilari, paragraph [0007]) . 07-21-aia AIA Claim (s) 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Goyal A. et al, (US. Patent Application Publication 20230234233 A1) effectively filed on January 26, 2022, (hereafter Goyal),), in view of Kilari V. et al, (US. Patent Application Publication 20240095542 A1) effectively filed on February 25, 2021, (hereafter Kilari), and further in view of Paramasivam V. et al, (US. Patent Application Publication 20220222513 A1) effectively filed on September 3, 2019, (hereafter Paramasivam) . Claim 3: Regarding claim 3, Goyal teaches the limitations in claim 2. Further, Goyal teaches “The apparatus of claim 2, wherein: the neural network application and the broker of the neural network operating system are executed on a CPU of a host,” See Goyal in paragraph [0109] where it describes “In at least one embodiment, logic 1015 is used to perform inferencing and/or training operations associated with one or more embodiments. In at least one embodiment, logic 1015 is inference and/or training logic. Details regarding logic 1015 are provided below in conjunction with FIGS. 10A and/or 10B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and/or firmware logic to provide functionality or operations described herein, wherein logic may be, collectively or individually, embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system-on-chip (SoC), or one or processors (e.g., CPU, GPU).” Here, Goyal establishes logic to provide functionality of all the operations being performed on an embodied circuitry which consists of a CPU integrated with other processing units. The orchestration system seen as a broker and the application are already established to be linked and performed using this logic . Further, see Goyal in paragraph [0571] describing “In at least one embodiment, during application execution, an inference request for a given application may be received, and a container (e.g., hosting an instance of an inference server) may be loaded (if not already), and a start procedure may be called. In at least one embodiment, pre-processing logic in a container may load, decode, and/or perform any additional pre-processing on incoming data (e.g., using a CPU(s) and/or GPU(s)).” Here Goyal establishes the application and its operations being executed on CPUs. Further, see Goyal in paragraph [0568] describing “In at least one embodiment, AI services 4018 may be leveraged to perform inferencing services for executing machine learning model(s) associated with applications (e.g., tasked with performing one or more processing tasks of an application). In at least one embodiment, AI services 4018 may leverage AI system 4024 to execute machine learning model(s) (e.g., neural networks, such as CNNs)”. Here Goyal further establishes an application which is tasked for performing processing tasks, being linked to neural networks, which can make the application be seen as a neural network application. Further, see Goyal in paragraph [0063] describing “In at least one embodiment, logic (e.g., object placement logic 122 , perception logic 126 , planning logic 128 , and/or movement logic 130 ) refers to any combination of software logic, hardware logic, and/or firmware logic to provide functionality or operations described herein, wherein logic may be, collectively or individually, embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system-on-chip (SoC), or one or processors (e.g., CPU, GPU). In at least one embodiment, one or more aspects of object placement logic 122 is a set of instructions and/or computer program that runs on, is performed by, and/or is executed by a processor (e.g., one or more CPUs and/or GPUs” Here Goyal establishes the different kind of logic that can be used and points out an object placement logic that is executed by a processor which can be a CPU. However, Goyal and Kilari did not explicitly teach “each of the task processors of the neural network operating system is executed on a CPU of each of the multiple neural processing units.” In the same field of art, Paramasivam teaches, “each of the task processors of the neural network operating system is executed on a CPU of each of the multiple neural processing units.” See Paramasivam in paragraph [0043] where it describes “FIG. 1 depicts a schematic drawing of a neural network processor system 100 according to various embodiments of the present invention. The neural network processor system 100 comprises: a plurality of neural processing units (NPUs) 102 , including a first neural processing unit (first NPU) 104 and a second neural processing unit (second NPU) 106 , whereby each neural processing unit comprises an array (or a set) of neural processing core blocks 108 , 110 , each neural processing core block 108 , 110 comprising a neural processing core (not shown in FIG. 1); and at least one central processing unit (CPU) 120 communicatively coupled to the plurality of neural processing units 102 and configured to coordinate the plurality of neural processing units 102 for performing neural network computations.” Here Paramasivam establishes a neural network processor system, which can be seen as a neural network operating system, comprising multiple neural processing units. There is at least one CPU associated with multiple neural processing units which is configured for execution. Each of the neural processing units comprises of a processing core or processing core block which can be seen as task processors as they are used to perform neural network computations which is a task . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the base references of Goyal and Kilari, with the teachings of Paramasivam by using Goyal’s teachings of abstracting neural networks into inference tasks across multiple neural processing units and returning an inference result, and Kilari’s teachings of segmenting a neural network into sub-neural networks, and incorporate with Paramasivam’s teachings of processors and an application being executed on a CPU, and processors being executed on multiple accelerators. One of ordinary skill in the art would be motivated to do so because by integrating Paramasivam’s frameworks into the methods of Goyal and Kilari, which are all in relation to operations of neural networks, one of ordinary skill in the art would bring “a neural network processor system and related methods, such as a method of operation the neural network processor system and a method of forming the neural network processor system described herein, that seek to overcome, or at least ameliorate, one or more of the deficiencies of conventional neural network processor systems, such as but not limited to, improving efficiency and/or effectiveness in performing neural network computations associated with one or more neural network applications” (Paramasivam, paragraph [0042]). Claim 4: Regarding claim 4, Goyal teaches the limitations in claim 2. Further, Goyal teaches “The apparatus of claim 2, wherein:…the broker of the neural network operating system,…are executed on a CPU of a single neural processing unit in a form of an embedded board,” See Goyal in paragraph [0109] where it describes “In at least one embodiment, logic 1015 is used to perform inferencing and/or training operations associated with one or more embodiments. In at least one embodiment, logic 1015 is inference and/or training logic. Details regarding logic 1015 are provided below in conjunction with FIGS. 10A and/or 10B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and/or firmware logic to provide functionality or operations described herein, wherein logic may be, collectively or individually, embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system-on-chip (SoC), or one or processors (e.g., CPU, GPU).” Here, Goyal establishes logic to provide functionality of all the operations being performed as an embodied circuitry which consists of a CPU integrated with other processing units, as known in the art, an embedded board is a printed circuit board (PCB) that integrates one or more processors, memory, and peripherals into a single unit, designed to perform specific functions within a larger system, which is exactly what is described here. This logic as an embodied circuitry is being seen as a single neural processing unit in form of an embedded board. The orchestration system seen as a broker and the training system seen as a neural network operating system are already established to be linked and performed using this logic in previous limitations . Further, see Goyal in paragraph [0063] describing “In at least one embodiment, logic (e.g., object placement logic 122 , perception logic 126 , planning logic 128 , and/or movement logic 130 ) refers to any combination of software logic, hardware logic, and/or firmware logic to provide functionality or operations described herein, wherein logic may be, collectively or individually, embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system-on-chip (SoC), or one or processors (e.g., CPU, GPU). In at least one embodiment, one or more aspects of object placement logic 122 is a set of instructions and/or computer program that runs on, is performed by, and/or is executed by a processor (e.g., one or more CPUs and/or GPUs” Here Goyal establishes the different kind of logic that can be used and points out an object placement logic that is executed by a CPU. Further, Goyal teaches “…processors are executed on…the single neural processing unit.” See Goyal in paragraph [0109] where it describes “In at least one embodiment, logic 1015 is used to perform inferencing and/or training operations associated with one or more embodiments. In at least one embodiment, logic 1015 is inference and/or training logic. Details regarding logic 1015 are provided below in conjunction with FIGS. 10A and/or 10B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and/or firmware logic to provide functionality or operations described herein, wherein logic may be, collectively or individually, embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system-on-chip (SoC), or one or processors (e.g., CPU, GPU).” Here, Goyal establishes logic to provide functionality of all the operations being performed on an embodied circuitry which consists of a CPU integrated with other processing units, as known in the art, An embedded board is a printed circuit board (PCB) that integrates one or more processors, memory, and peripherals into a single unit, designed to perform specific functions within a larger system, which is exactly what is described here. This can be seen as a single neural processing unit and it has processors that are executed on it. However, Goyal and Kilari did not explicitly teach “the neural network application,…,and each of the task processors of the neural network operating system are executed on a CPU..., and the respective task processors are executed on multiple accelerators...” In the same field of art, Paramasivam teaches, “the neural network application,…,and each of the task processors of the neural network operating system are executed on a CPU...,” See Paramasivam in paragraph [0043] where it describes “FIG. 1 depicts a schematic drawing of a neural network processor system 100 according to various embodiments of the present invention. The neural network processor system 100 comprises: a plurality of neural processing units (NPUs) 102 , including a first neural processing unit (first NPU) 104 and a second neural processing unit (second NPU) 106 , whereby each neural processing unit comprises an array (or a set) of neural processing core blocks 108 , 110 , each neural processing core block 108 , 110 comprising a neural processing core (not shown in FIG. 1); and at least one central processing unit (CPU) 120 communicatively coupled to the plurality of neural processing units 102 and configured to coordinate the plurality of neural processing units 102 for performing neural network computations.” Here Paramasivam establishes at least one CPU associated with multiple neural processing units which is configured for execution. Each of the neural processing units comprises of a processing core or processing core block which can be seen as task processors as they are used to perform neural network computations which is a task . The task processors can then be seen to be executed on a CPU. Further, see Paramasivam in paragraph [0044] where it describes “In this regard, configuring neural processing units 102 to have different structural configurations advantageously enable the CPU(s) 120 to assign neural network tasks (or neural network operations) obtained (or derived) from one or more neural network applications to the plurality of neural processing units”. Here Paramasivam establishes a CPU being enabled for execution of tasks from a neural network application. Further, Paramasivam teaches, “and the respective task processors are executed on multiple accelerators...” See Paramasivam in paragraph [0043] where it describes “FIG. 1 depicts a schematic drawing of a neural network processor system 100 according to various embodiments of the present invention. The neural network processor system 100 comprises: a plurality of neural processing units (NPUs) 102 , including a first neural processing unit (first NPU) 104 and a second neural processing unit (second NPU) 106 , whereby each neural processing unit comprises an array (or a set) of neural processing core blocks 108 , 110 , each neural processing core block 108 , 110 comprising a neural processing core (not shown in FIG. 1); and at least one central processing unit (CPU) 120 communicatively coupled to the plurality of neural processing units 102 and configured to coordinate the plurality of neural processing units 102 for performing neural network computations.” Here Paramasivam establishes at least one CPU associated with multiple neural processing units which is configured for execution. Each of the neural processing units comprises of a processing core or processing core block which can be seen as task processors as they are used to perform neural network computations which is a task . The task processors can then be seen to be executed on a CPU. Further, see Paramasivam in paragraph [0084] where it describes “the CPU may be configured to assign the suitable neural tasks to the most efficient (or more suitable) NPU(s) (e.g., accelerator(s)). The number of NPUs may vary from system to system, depending on the target application.” Here Paramasivam establishes the NPUs being accelerators, since the NPU consists of the established task processors, these task processors can be seen to be executed on multiple accelerators. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the base references of Goyal and Kilari, with the teachings of Paramasivam by using Goyal’s teachings of abstracting neural networks into inference tasks across multiple neural processing units and returning an inference result, and Kilari’s teachings of segmenting a neural network into sub-neural networks, and incorporate with Paramasivam’s teachings of processors and an application being executed on a CPU, and processors being executed on multiple accelerators. One of ordinary skill in the art would be motivated to do so because by integrating Paramasivam’s frameworks into the methods of Goyal and Kilari, which are all in relation to operations of neural networks, one of ordinary skill in the art would bring “a neural network processor system and related methods, such as a method of operation the neural network processor system and a method of forming the neural network processor system described herein, that seek to overcome, or at least ameliorate, one or more of the deficiencies of conventional neural network processor systems, such as but not limited to, improving efficiency and/or effectiveness in performing neural network computations associated with one or more neural network applications” (Paramasivam, paragraph [0042]) . 07-21-aia AIA Claim (s) 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Goyal A. et al, (US. Patent Application Publication 20230234233 A1) effectively filed on January 26, 2022, (hereafter Goyal), in view of Paramasivam V. et al, (US. Patent Application Publication 20220222513 A1) effectively filed on September 3, 2019, (hereafter Paramasivam) . Claim 11: Regarding claim 11, Goyal teaches the limitations in claim 10. Further, Goyal teaches “The apparatus of claim 10, wherein: the neural network application and the broker of the neural network operating system are executed on a CPU of a host,” See Goyal in paragraph [0109] where it describes “In at least one embodiment, logic 1015 is used to perform inferencing and/or training operations associated with one or more embodiments. In at least one embodiment, logic 1015 is inference and/or training logic. Details regarding logic 1015 are provided below in conjunction with FIGS. 10A and/or 10B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and/or firmware logic to provide functionality or operations described herein, wherein logic may be, collectively or individually, embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system-on-chip (SoC), or one or processors (e.g., CPU, GPU).” Here, Goyal establishes logic to provide functionality of all the operations being performed on an embodied circuitry which consists of a CPU integrated with other processing units. The orchestration system seen as a broker and the application are already established to be linked and performed using this logic . Further, see Goyal in paragraph [0571] describing “In at least one embodiment, during application execution, an inference request for a given application may be received, and a container (e.g., hosting an instance of an inference server) may be loaded (if not already), and a start procedure may be called. In at least one embodiment, pre-processing logic in a container may load, decode, and/or perform any additional pre-processing on incoming data (e.g., using a CPU(s) and/or GPU(s)).” Here Goyal establishes the application and its operations being executed on CPUs. Further, see Goyal in paragraph [0568] describing “In at least one embodiment, AI services 4018 may be leveraged to perform inferencing services for executing machine learning model(s) associated with applications (e.g., tasked with performing one or more processing tasks of an application). In at least one embodiment, AI services 4018 may leverage AI system 4024 to execute machine learning model(s) (e.g., neural networks, such as CNNs)”. Here Goyal further establishes an application which is tasked for performing processing tasks, being linked to neural networks, which can make the application be seen as a neural network application. Further, see Goyal in paragraph [0063] describing “In at least one embodiment, logic (e.g., object placement logic 122 , perception logic 126 , planning logic 128 , and/or movement logic 130 ) refers to any combination of software logic, hardware logic, and/or firmware logic to provide functionality or operations described herein, wherein logic may be, collectively or individually, embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system-on-chip (SoC), or one or processors (e.g., CPU, GPU). In at least one embodiment, one or more aspects of object placement logic 122 is a set of instructions and/or computer program that runs on, is performed by, and/or is executed by a processor (e.g., one or more CPUs and/or GPUs” Here Goyal establishes the different kind of logic that can be used and points out an object placement logic that is executed by a processor which can be a CPU. However, Goyal did not explicitly teach “each of the task processors of the neural network operating system is executed on a CPU of each of the multiple neural processing units.” In the same field of art, Paramasivam teaches, “each of the task processors of the neural network operating system is executed on a CPU of each of the multiple neural processing units.” See Paramasivam in paragraph [0043] where it describes “FIG. 1 depicts a schematic drawing of a neural network processor system 100 according to various embodiments of the present invention. The neural network processor system 100 comprises: a plurality of neural processing units (NPUs) 102 , including a first neural processing unit (first NPU) 104 and a second neural processing unit (second NPU) 106 , whereby each neural processing unit comprises an array (or a set) of neural processing core blocks 108 , 110 , each neural processing core block 108 , 110 comprising a neural processing core (not shown in FIG. 1); and at least one central processing unit (CPU) 120 communicatively coupled to the plurality of neural processing units 102 and configured to coordinate the plurality of neural processing units 102 for performing neural network computations.” Here Paramasivam establishes a neural network processor system, which can be seen as a neural network operating system, comprising multiple neural processing units. There is at least one CPU associated with multiple neural processing units which is configured for execution. Each of the neural processing units comprises of a processing core or processing core block which can be seen as task processors as they are used to perform neural network computations which is a task . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the base reference of Goyal with the teachings of Paramasivam by using Goyal’s teachings of abstracting neural networks into inference tasks across multiple neural processing units and returning an inference result, and incorporate with Paramasivam’s teachings of processors of a neural network operating system being executed on a CPU of multiple neural network processing units. One of ordinary skill in the art would be motivated to do so because by integrating Paramasivam’s frameworks into the methods of Goyal, which are both in relation to operations of neural networks, one of ordinary skill in the art would bring “a neural network processor system and related methods, such as a method of operation the neural network processor system and a method of forming the neural network processor system described herein, that seek to overcome, or at least ameliorate, one or more of the deficiencies of conventional neural network processor systems, such as but not limited to, improving efficiency and/or effectiveness in performing neural network computations associated with one or more neural network applications” (Paramasivam, paragraph [0042]). Claim 12: Regarding claim 12, Goyal teaches the limitations in claim 10. Further, Goyal teaches “The apparatus of claim 10, wherein:…the broker of the neural network operating system,…are executed on a CPU of a single neural processing unit in a form of an embedded board,” See Goyal in paragraph [0109] where it describes “In at least one embodiment, logic 1015 is used to perform inferencing and/or training operations associated with one or more embodiments. In at least one embodiment, logic 1015 is inference and/or training logic. Details regarding logic 1015 are provided below in conjunction with FIGS. 10A and/or 10B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and/or firmware logic to provide functionality or operations described herein, wherein logic may be, collectively or individually, embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system-on-chip (SoC), or one or processors (e.g., CPU, GPU).” Here, Goyal establishes logic to provide functionality of all the operations being performed as an embodied circuitry which consists of a CPU integrated with other processing units, as known in the art, an embedded board is a printed circuit board (PCB) that integrates one or more processors, memory, and peripherals into a single unit, designed to perform specific functions within a larger system, which is exactly what is described here. This logic as an embodied circuitry is being seen as a single neural processing unit in form of an embedded board. The orchestration system seen as a broker and the training system seen as a neural network operating system are already established to be linked and performed using this logic in previous limitations . Further, see Goyal in paragraph [0063] describing “In at least one embodiment, logic (e.g., object placement logic 122 , perception logic 126 , planning logic 128 , and/or movement logic 130 ) refers to any combination of software logic, hardware logic, and/or firmware logic to provide functionality or operations described herein, wherein logic may be, collectively or individually, embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system-on-chip (SoC), or one or processors (e.g., CPU, GPU). In at least one embodiment, one or more aspects of object placement logic 122 is a set of instructions and/or computer program that runs on, is performed by, and/or is executed by a processor (e.g., one or more CPUs and/or GPUs” Here Goyal establishes the different kind of logic that can be used and points out an object placement logic that is executed by a CPU. Further, Goyal teaches “…processors are executed on…the single neural processing unit.” See Goyal in paragraph [0109] where it describes “In at least one embodiment, logic 1015 is used to perform inferencing and/or training operations associated with one or more embodiments. In at least one embodiment, logic 1015 is inference and/or training logic. Details regarding logic 1015 are provided below in conjunction with FIGS. 10A and/or 10B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and/or firmware logic to provide functionality or operations described herein, wherein logic may be, collectively or individually, embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system-on-chip (SoC), or one or processors (e.g., CPU, GPU).” Here, Goyal establishes logic to provide functionality of all the operations being performed on an embodied circuitry which consists of a CPU integrated with other processing units, as known in the art, An embedded board is a printed circuit board (PCB) that integrates one or more processors, memory, and peripherals into a single unit, designed to perform specific functions within a larger system, which is exactly what is described here. This can be seen as a single neural processing unit and it has processors that are executed on it. However, Goyal and Kulari did not explicitly teach “the neural network application,…,and each of the task processors of the neural network operating system are executed on a CPU..., and the respective task processors are executed on multiple accelerators...” Further, Paramasivam teaches, “the neural network application,…,and each of the task processors of the neural network operating system are executed on a CPU...,” See Paramasivam in paragraph [0043] where it describes “FIG. 1 depicts a schematic drawing of a neural network processor system 100 according to various embodiments of the present invention. The neural network processor system 100 comprises: a plurality of neural processing units (NPUs) 102 , including a first neural processing unit (first NPU) 104 and a second neural processing unit (second NPU) 106 , whereby each neural processing unit comprises an array (or a set) of neural processing core blocks 108 , 110 , each neural processing core block 108 , 110 comprising a neural processing core (not shown in FIG. 1); and at least one central processing unit (CPU) 120 communicatively coupled to the plurality of neural processing units 102 and configured to coordinate the plurality of neural processing units 102 for performing neural network computations.” Here Paramasivam establishes at least one CPU associated with multiple neural processing units which is configured for execution. Each of the neural processing units comprises of a processing core or processing core block which can be seen as task processors as they are used to perform neural network computations which is a task . The task processors can then be seen to be executed on a CPU. Further, see Paramasivam in paragraph [0044] where it describes “In this regard, configuring neural processing units 102 to have different structural configurations advantageously enable the CPU(s) 120 to assign neural network tasks (or neural network operations) obtained (or derived) from one or more neural network applications to the plurality of neural processing units”. Here Paramasivam establishes a CPU being enabled for execution of tasks from a neural network application. In the same field of art, Paramasivam teaches, “and the respective task processors are executed on multiple accelerators...” See Paramasivam in paragraph [0043] where it describes “FIG. 1 depicts a schematic drawing of a neural network processor system 100 according to various embodiments of the present invention. The neural network processor system 100 comprises: a plurality of neural processing units (NPUs) 102 , including a first neural processing unit (first NPU) 104 and a second neural processing unit (second NPU) 106 , whereby each neural processing unit comprises an array (or a set) of neural processing core blocks 108 , 110 , each neural processing core block 108 , 110 comprising a neural processing core (not shown in FIG. 1); and at least one central processing unit (CPU) 120 communicatively coupled to the plurality of neural processing units 102 and configured to coordinate the plurality of neural processing units 102 for performing neural network computations.” Here Paramasivam establishes at least one CPU associated with multiple neural processing units which is configured for execution. Each of the neural processing units comprises of a processing core or processing core block which can be seen as task processors as they are used to perform neural network computations which is a task . The task processors can then be seen to be executed on a CPU. Further, see Paramasivam in paragraph [0084] where it describes “the CPU may be configured to assign the suitable neural tasks to the most efficient (or more suitable) NPU(s) (e.g., accelerator(s)). The number of NPUs may vary from system to system, depending on the target application.” Here Paramasivam establishes the NPUs being accelerators, since the NPU consists of the established task processors, these task processors can be seen to be executed on multiple accelerators. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the base reference of Goyal with the teachings of Paramasivam by using Goyal’s teachings of abstracting neural networks into inference tasks across multiple neural processing units and returning an inference result, and incorporate with Paramasivam’s teachings of processors and an application being executed on a CPU, and processors being executed on multiple accelerators. One of ordinary skill in the art would be motivated to do so because by integrating Paramasivam’s frameworks into the methods of Goyal, which are both in relation to operations of neural networks, one of ordinary skill in the art would bring “a neural network processor system and related methods, such as a method of operation the neural network processor system and a method of forming the neural network processor system described herein, that seek to overcome, or at least ameliorate, one or more of the deficiencies of conventional neural network processor systems, such as but not limited to, improving efficiency and/or effectiveness in performing neural network computations associated with one or more neural network applications” (Paramasivam, paragraph [0042]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HASSAN R SESAY whose telephone number is (571)272-8493. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HASSAN RAMADAN SESAY/Examiner, Art Unit 2146 /USMAAN SAEED/Supervisory Patent Examiner, Art Unit 2146 Application/Control Number: 18/347,297 Page 2 Art Unit: 2146 Application/Control Number: 18/347,297 Page 3 Art Unit: 2146 Application/Control Number: 18/347,297 Page 4 Art Unit: 2146 Application/Control Number: 18/347,297 Page 5 Art Unit: 2146 Application/Control Number: 18/347,297 Page 6 Art Unit: 2146 Application/Control Number: 18/347,297 Page 7 Art Unit: 2146 Application/Control Number: 18/347,297 Page 8 Art Unit: 2146 Application/Control Number: 18/347,297 Page 9 Art Unit: 2146 Application/Control Number: 18/347,297 Page 10 Art Unit: 2146 Application/Control Number: 18/347,297 Page 11 Art Unit: 2146 Application/Control Number: 18/347,297 Page 12 Art Unit: 2146 Application/Control Number: 18/347,297 Page 13 Art Unit: 2146 Application/Control Number: 18/347,297 Page 14 Art Unit: 2146 Application/Control Number: 18/347,297 Page 15 Art Unit: 2146 Application/Control Number: 18/347,297 Page 16 Art Unit: 2146 Application/Control Number: 18/347,297 Page 17 Art Unit: 2146 Application/Control Number: 18/347,297 Page 18 Art Unit: 2146 Application/Control Number: 18/347,297 Page 19 Art Unit: 2146 Application/Control Number: 18/347,297 Page 20 Art Unit: 2146 Application/Control Number: 18/347,297 Page 21 Art Unit: 2146 Application/Control Number: 18/347,297 Page 22 Art Unit: 2146 Application/Control Number: 18/347,297 Page 23 Art Unit: 2146 Application/Control Number: 18/347,297 Page 24 Art Unit: 2146 Application/Control Number: 18/347,297 Page 25 Art Unit: 2146 Application/Control Number: 18/347,297 Page 26 Art Unit: 2146 Application/Control Number: 18/347,297 Page 27 Art Unit: 2146 Application/Control Number: 18/347,297 Page 28 Art Unit: 2146 Application/Control Number: 18/347,297 Page 29 Art Unit: 2146 Application/Control Number: 18/347,297 Page 30 Art Unit: 2146 Application/Control Number: 18/347,297 Page 32 Art Unit: 2146 Application/Control Number: 18/347,297 Page 33 Art Unit: 2146 Application/Control Number: 18/347,297 Page 34 Art Unit: 2146 Application/Control Number: 18/347,297 Page 35 Art Unit: 2146 Application/Control Number: 18/347,297 Page 36 Art Unit: 2146 Application/Control Number: 18/347,297 Page 37 Art Unit: 2146 Application/Control Number: 18/347,297 Page 38 Art Unit: 2146 Application/Control Number: 18/347,297 Page 39 Art Unit: 2146 Application/Control Number: 18/347,297 Page 40 Art Unit: 2146 Application/Control Number: 18/347,297 Page 41 Art Unit: 2146 Application/Control Number: 18/347,297 Page 42 Art Unit: 2146 Application/Control Number: 18/347,297 Page 43 Art Unit: 2146 Application/Control Number: 18/347,297 Page 44 Art Unit: 2146 Application/Control Number: 18/347,297 Page 45 Art Unit: 2146 Application/Control Number: 18/347,297 Page 46 Art Unit: 2146 Application/Control Number: 18/347,297 Page 47 Art Unit: 2146 Application/Control Number: 18/347,297 Page 48 Art Unit: 2146 Application/Control Number: 18/347,297 Page 49 Art Unit: 2146 Application/Control Number: 18/347,297 Page 50 Art Unit: 2146 Application/Control Number: 18/347,297 Page 51 Art Unit: 2146 Application/Control Number: 18/347,297 Page 52 Art Unit: 2146 Application/Control Number: 18/347,297 Page 53 Art Unit: 2146 Application/Control Number: 18/347,297 Page 54 Art Unit: 2146 Application/Control Number: 18/347,297 Page 55 Art Unit: 2146 Application/Control Number: 18/347,297 Page 56 Art Unit: 2146 Application/Control Number: 18/347,297 Page 57 Art Unit: 2146 Application/Control Number: 18/347,297 Page 58 Art Unit: 2146 Application/Control Number: 18/347,297 Page 59 Art Unit: 2146 Application/Control Number: 18/347,297 Page 60 Art Unit: 2146 Application/Control Number: 18/347,297 Page 61 Art Unit: 2146 Application/Control Number: 18/347,297 Page 62 Art Unit: 2146 Application/Control Number: 18/347,297 Page 63 Art Unit: 2146 Application/Control Number: 18/347,297 Page 64 Art Unit: 2146 Application/Control Number: 18/347,297 Page 65 Art Unit: 2146 Application/Control Number: 18/347,297 Page 66 Art Unit: 2146 Application/Control Number: 18/347,297 Page 67 Art Unit: 2146 Application/Control Number: 18/347,297 Page 68 Art Unit: 2146 Application/Control Number: 18/347,297 Page 69 Art Unit: 2146 Application/Control Number: 18/347,297 Page 70 Art Unit: 2146 Application/Control Number: 18/347,297 Page 71 Art Unit: 2146 Application/Control Number: 18/347,297 Page 72 Art Unit: 2146 Application/Control Number: 18/347,297 Page 73 Art Unit: 2146 Application/Control Number: 18/347,297 Page 74 Art Unit: 2146 Application/Control Number: 18/347,297 Page 75 Art Unit: 2146 Application/Control Number: 18/347,297 Page 76 Art Unit: 2146
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