Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 5, 10, 12, 17, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 3, 10, and 17, “d-μ(u),μ(ν) represents the first matrix and the second matrix” renders the claims indefinite because it is unclear if the claimed variable is identical for both matrices or if the sub-indices indicate the first and second matrices, e.g. μ(u) for the first matrix and μ(ν) for the second.
Regarding claims 5, 12, and 19, “λw(e)” is not defined and Ec[i,j] is not defined.
Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 7-8, and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dury (Dury, Bryan, and Olivia Di Matteo. "A QUBO formulation for qubit allocation." arXiv preprint arXiv:2009.00140 (2020)) in view of Park (Park, Sunghye, et al. "A fast and scalable qubit-mapping method for noisy intermediate-scale quantum computers." Proceedings of the 59th ACM/IEEE Design Automation Conference. 2022.)
Regarding claim 1, Dury teaches a method, comprising:
obtaining a quantum circuit that includes a plurality of quantum bits (qubits), the qubits being sparsely connected to one another such that not every qubit includes a physical connection to each other qubit of the plurality (Figure 2);
generating a graph representation of the quantum circuit including nodes and edges in which individual qubits of the plurality of qubits are represented using respective nodes and in which individual physical connections between two qubits are represented using respective edges that connect two respective nodes corresponding to the two qubits (Figure 2);
modeling the weighted graph representation of the quantum circuit as a Quadratic Assignment Problem (QAP) (see Equations 2-3 and 9); and
determining an initial mapping of the qubits based on a solution to the QAP (§1, “The QUBO method coupled with simulated annealing demonstrated a number of distinct advantages compared to existing initial allocation methods).
Dury does not teach assigning weight values to the respective edges based on gate depths respectively associated with the respective edges to generate a weighted graph representation of the quantum circuit, an individual gate depth indicating how early a particular operation of the quantum circuit associated with a respective edge is scheduled to be performed by the quantum circuit.
Park teaches assigning weight values to the respective edges based on gate depths respectively associated with the respective edges to generate a weighted graph representation of the quantum circuit, an individual gate depth indicating how early a particular operation of the quantum circuit associated with a respective edge is scheduled to be performed by the quantum circuit (§3.1, “An interaction-order graph is used to consider gate constraints related to the parent node sequentially”, Figure 4(b)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Dury to include assigning weight values to the respective edges based on gate depths respectively associated with the respective edges to generate a weighted graph representation of the quantum circuit, an individual gate depth indicating how early a particular operation of the quantum circuit associated with a respective edge is scheduled to be performed by the quantum circuit in order to ensure an accurate graph is created via consideration of gate constraints.
Regarding claim 7, Dury as modified teaches all of the limitations of claim 1, wherein
assigning the weight values to the respective edges based on gate depths includes assigning a greater weight value to a first particular edge having a greater gate depth and a lower weight value to a second particular edge having a lower gate depth (see Figure 4(b) of Park).
Regarding claims 8 and 15, the implementation of Dury as modified on a computer (see §III of Dury) covers the computer-readable storage media and instructions of claim 8 and the system of claim 15.
Regarding claim 14, Dury as modified according to claim 7 when implemented on a computer covers the computer-readable storage media and instructions of claim 14.
Allowable Subject Matter
Claims 2-6, 9-13, and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 2-6 and corresponding claims 9-13 and 16-20 are not anticipated or rendered obvious by the prior art.
In particular, the prior art establishes a prima facie case of obviousness for the broadly claimed weighted graph and accompanying aspects thereof in claims 1, 8, and 15. However, each dependent claim 2-6 (and 9-13 and 16-20) recite details not found in the closest prior art of record, Dury and Park. Impermissible hindsight would be required to arrive at Applicant’s claimed invention from these disclosures.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCHYLER S SANKS whose telephone number is (571)272-6125. The examiner can normally be reached 06:30 - 15:30 Central Time, M-F.
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/SCHYLER S SANKS/Primary Examiner, Art Unit 2129