Prosecution Insights
Last updated: April 19, 2026
Application No. 18/348,536

Computational Graph Optimization Method and Apparatus

Final Rejection §101§103
Filed
Jul 07, 2023
Examiner
BUI, HANH THI MINH
Art Unit
2192
Tech Center
2100 — Computer Architecture & Software
Assignee
Huawei Technologies Co., Ltd.
OA Round
2 (Final)
80%
Grant Probability
Favorable
3-4
OA Rounds
3y 0m
To Grant
99%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allow Rate
465 granted / 582 resolved
+24.9% vs TC avg
Strong +64% interview lift
Without
With
+63.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
21 currently pending
Career history
603
Total Applications
across all art units

Statute-Specific Performance

§101
18.6%
-21.4% vs TC avg
§103
52.1%
+12.1% vs TC avg
§102
14.5%
-25.5% vs TC avg
§112
6.1%
-33.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 582 resolved cases

Office Action

§101 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Status of Claims Applicant’s Remarks dated October 29th, 2025 responding to the Office Action provided in the rejection of claims 1-7, 10-17, and 20. Claim 10 has been canceled. Claim 21 has been newly added. Claims 1, 7, 11, 17, and 20 have been amended. Claims 1-9 and 11-21 are remain pending in the application and which have been fully considered by the examiner. Claims 1, 11, and 20 are in independent form. Claims 8-9 and 18-19 are objected. Claims 1-7, 11-17, and 20-21 are finally rejected. Examiner Notes Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. REMARKS Applicant's traversal of the claim rejections, with respect to prior art, primarily consists of the following arguments, which will be addressed below: The combination of Dickie and Sui fails to render obvious claims 1-9 and 11-20 because the combination of Dickie and Sui fails to disclose: 1) obtaining a first computational graph through conversion based on the to-be-optimized code and the preset conversion rule (See Remarks, pages 13-16). The combination of Dickie and Sui fails to render obvious claims 1-9 and 11-20 because the combination of Dickie and Sui fails to disclose: 2) converting the target computational graph into target code according to a reverse conversion rule that is reverse to the preset conversion rule (See Remarks, pages 13-16). Prior Art’s Arguments - Rejections Applicants’ arguments filed on October 29th, 2025 have been fully considered but they are not persuasive. For example: Applicant contends, the prior arts or record do not teach “obtaining a first computational graph through conversion based on the to-be-optimized code and the preset conversion rule”. Examiner respectfully disagrees because Dickie further discloses “In some embodiments, a computer system process used to execute a data processing operation represented by a node in a dataflow graph may be an instance of a computer program configured to execute processor-executable instructions for encoding the data processing operation. A computer system process may be a single-threaded or a multi-threaded process. A computer system process may be associated with one or more computer system resources including, by way of example and not limitation, processor-executable instructions representing encoding the data processing operation. In some embodiments, the initial dataflow graph may be generated from a query plan at least in part by generating the initial dataflow graph to include a node for each of at least a subset (e.g., some or all) of the data processing operations identified in the query plan. Subsequently, the order of data processing operations specified in the query plan may be used to generate links connecting nodes in the initial dataflow graph. For example, when the generated query plan indicates that a first data processing operation is performed before a second data processing operation, the generated initial dataflow graph may have a first node (representing the first data processing operation) and a second node (representing the second data processing operation) and one or more links specifying a path from the first node to the second node.” (Underline added – See paras [0068] – [0069]). Applicant contends, the prior arts or record do not teach “converting the target computational graph into target code according to a reverse conversion rule that is reverse to the preset conversion rule” however, Applicant’s arguments with respect to claims 1, 11, and 20 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection. See Ma et al. (U.S. Pub. No.: US 2023/0107440 – art made of record) and paragraphs [0093] – [0094]. Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Allowable Subject Matter Claims 8 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-9 and 11-21 are rejected under 35 U.S.C. 101 because the claimed invention recites a judicial exception, is directed to that judicial exception, an abstract idea, as it has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception. Examiner has evaluated the claims under the framework provided in the 2019 Patent Eligibility Guidance published in the Federal Register 01/07/2019 and has provided such analysis below. Step 1: Claims 1-9 are directed to methods and fall within the statutory category of processes; Claims 11-19 are directed to apparatus and fall within the statutory category of machines; and Claims 20-21 are directed to computer program product and fall within the statutory category of articles of manufacture. Therefore, “Are the claims to a process, machine, manufacture or composition of matter?” Yes. In order to evaluate the Step 2A inquiry “Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?” we must determine, at Step 2A Prong 1, whether the claim recites a law of nature, a natural phenomenon or an abstract idea and further whether the claim recites additional elements that integrate the judicial exception into a practical application. Step 2A Prong 1: Claims 1, 11 and 20: recite the limitations of “ obtaining to-be-optimized code; receiving a preset conversion rule from a user; obtaining a first computational graph through conversion based on the to-be-optimized code and the preset conversion rule; performing iterative transformations on the first computational graph based on preset graph transformation manners to optimize the first computational graph in order to obtain a target computational graph; converting the target computational graph into target code according to a reverse conversion rule that is reverse to the preset conversion rule; compiling the target code into obtain machine-executable code; outputting the machine-executable code to the user” as drafted, is a mental process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitations can be done in the mind and with the aid of pen and paper. For example, limitations (a) and (b) correspond to collection of data/information; limitations (c) and (e) correspond to conversion of data. Thus, any of the aforementioned exemplary process can be performed as mental evaluations. Therefore, Yes, claims 1, 11 and 20 recite judicial exceptions. The claims have been identified to recite judicial exceptions, Step 2A Prong 2 will evaluate whether the claims are directed to the judicial exception. Step 2A Prong 2: Claims 1, 11 and 20: The judicial exception is not integrated into a practical application. In particular, the claim recites the following additional limitations (e ), (f), (g), and additional elements – “computational graph optimization apparatus,” “memory access operations,” “abstract syntax tree,” “executable code,” “apparatus,” “one or more processors,” “memory,” and “computer-readable medium,” which are merely recitations of generic computing components and functions merely applying the abstract idea using (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Therefore, “Do the claims recite additional elements that integrate the judicial exception into a practical application? No, these additional elements do not integrate the abstract idea into a practical application and they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea. After having evaluating the inquires set forth in Steps 2A Prong 1 and 2, it has been concluded that claims 1, 11 and 20 not only recites a judicial exception but that the claim is directed to the judicial exception as the judicial exception has not been integrated into practical application. Step 2B: Claims 1, 11 and 20: The claims do not include additional elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements, e.g., limitations (d) and (e) amount to no more than generic computing components merely applying the abstract idea and field of use/technological environment. Therefore, “Do the claims recite additional elements that amount to significantly more than the judicial exception? No, these additional elements, alone or in combination, do not amount to significantly more than the judicial exception. Having concluded analysis within the provided framework, claims 1, 11 and 20 do not recite patent eligible subject matter under 35 U.S.C. § 101. Regarding claims 2, 12, and 21, they recite additional element recitations of “performing, based on a performance evaluation policy, a performance evaluation on a computational graph from a transformation in at least one of the preset graph transformation manners to obtain a performance evaluation; and determining the target computational graph based on the performance evaluation result” which is merely a field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate the judicial exception into practical application. Moreover, claims 2, 12, and 21 do not recite any other additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 2, 12, and 21 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claims 2, 12, and 21 do not recite patent eligible subject matter under 35 U.S.C. § 101. Regarding claims 3 and 13, they recite additional element recitations of “selecting, based on a search policy, a to-be-optimized computational graph in a next iterative transformation from a plurality of computational graphs; and performing, based on the preset graph transformation manners, the iterative transformations on the to-be-optimized computational graph to obtain the target computational graph” which is merely a field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate the judicial exception into practical application. Moreover, claims 3 and 13 do not recite any other additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 3 and 13 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claims 3 and 13 do not recite patent eligible subject matter under 35 U.S.C. § 101. Regarding claims 4 and 14, they recite additional element recitations of “wherein performing the iterative transformations removing, based on a pruning policy, an invalid graph transformation manner from the preset graph transformation manners” which is merely a field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate the judicial exception into practical application. Moreover, claims 4 and 14 do not recite any other additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 4 and 14 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claims 4 and 14 do not recite patent eligible subject matter under 35 U.S.C. § 101. Regarding claims 5 and 15, they recite additional element recitations of “performing the performance evaluation based on a calculation operations and memory access operations that are of an abstract syntax tree (AST) corresponding to the computational graph or based on a running time of executable code corresponding to the computational graph” which is merely a field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate the judicial exception into practical application. Moreover, claims 5 and 15 do not recite any other additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 5 and 15 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claims 5 and 15 do not recite patent eligible subject matter under 35 U.S.C. § 101. Regarding claims 6 and 16, they recite additional element recitations of “wherein the search policy is based on performances of the computational graphs” which is merely a field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate the judicial exception into practical application. Moreover, claims 6 and 16 do not recite any other additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 6 and 16 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claims 6 and 16 do not recite patent eligible subject matter under 35 U.S.C. § 101. Regarding claims 7 and 17, they recite additional element recitations of “a quantity of times of loop tiling performed on a loop logic exceeding a preset threshold; or a loop interchange being performed on two pieces of loop logic for a plurality of times” which is merely a field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate the judicial exception into practical application. Moreover, claims 7 and 17 do not recite any other additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 7 and 17 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claims 7 and 17 do not recite patent eligible subject matter under 35 U.S.C. § 101. Regarding claims 8 and 18, they recite additional element recitations of “determining m candidate graph transformation manners from the preset graph transformation manners, wherein the m candidate graph transformation manners match a subgraph in the first computational graph, and wherein m is a positive integer; transforming the first computational graph based on the m candidate graph transformation manners to obtain m second computational graphs, wherein the m second computational graphs are in a one-to-one correspondence with the m candidate graph transformation manners; and determining the target computational graph based on the m second computational graphs” which is merely a field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate the judicial exception into practical application. Moreover, claims 8 and 18 do not recite any other additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 8 and 18 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claims 8 and 18 do not recite patent eligible subject matter under 35 U.S.C. § 101. Regarding claims 9 and 19, they recite additional element recitations of “determining a first candidate target computational graph in the m second computational graphs, wherein a first performance of the first candidate target computational graph is better than a second performance of a computational graph other than the first candidate target computational graph in the m second computational graphs; and determining the target computational graph based on the first candidate target computational graph” which is merely a field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate the judicial exception into practical application. Moreover, claims 9 and 19 do not recite any other additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 9 and 19 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claims 9 and 19 do not recite patent eligible subject matter under 35 U.S.C. § 101. Claim Rejections - 35 U.S.C § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-7, 11-17, and 20-21 are rejected under 35 U.S.C. § 103 as being unpatentable over Dickie (Pub. No.: US 2019/0370407 – hereinafter, Dickie) in view of Sui et al. (Pub. No.: US 2019/0303762 – hereinafter, Sui – IDS filed 12/30/2024). Regarding claim 1: Dickie discloses a method implemented by a [[computational]] graph optimization apparatus and comprising: obtaining to-be-optimized code (“In some embodiments, a computer system process used to execute a data processing operation represented by a node in a dataflow graph may be an instance of a computer program configured to execute processor-executable instructions for encoding the data processing operation. A computer system process may be a single-threaded or a multi-threaded process. A computer system process may be associated with one or more computer system resources including, by way of example and not limitation, processor-executable instructions representing encoding the data processing operation” (Underline added – See para [0068]); receiving a preset conversion rule from a user (“In some embodiments, the initial dataflow graph may be generated from a query plan at least in part by generating the initial dataflow graph to include a node for each of at least a subset (e.g., some or all) of the data processing operations identified in the query plan. Subsequently, the order of data processing operations specified in the query plan may be used to generate links connecting nodes in the initial dataflow graph. For example, when the generated query plan indicates that a first data processing operation is performed before a second data processing operation, the generated initial dataflow graph may have a first node (representing the first data processing operation) and a second node (representing the second data processing operation) and one or more links specifying a path from the first node to the second node.” (Underline added – See para [0069])); obtaining a first [[computational]] graph through conversion based on the to-be-optimized code and the preset conversion rule (“obtaining an automatically generated initial dataflow graph, the initial dataflow graph comprising a first plurality of nodes representing a first plurality of data processing operations and a first plurality of links representing flows of data among nodes in the first plurality of nodes” (See Abstract). “In some embodiments, the initial dataflow graph may be generated from a query plan at least in part by generating the initial dataflow graph to include a node for each of at least a subset (e.g., some or all) of the data processing operations identified in the query plan. Subsequently, the order of data processing operations specified in the query plan may be used to generate links connecting nodes in the initial dataflow graph. For example, when the generated query plan indicates that a first data processing operation is performed before a second data processing operation, the generated initial dataflow graph may have a first node (representing the first data processing operation) and a second node (representing the second data processing operation) and one or more links specifying a path from the first node to the second node.” (Underline added – See para [0069])); and performing iterative transformations on the first [[computational]] graph based on preset graph transformation manners to optimize the first [[computational]] graph in order to obtain a target computational graph (“generating an updated dataflow graph by iteratively applying dataflow graph optimization rules to update the initial dataflow graph, the updated dataflow graph comprising a second plurality of nodes representing a second plurality of data processing operations and a second plurality of links representing flows of data among nodes in the second plurality of nodes” (See Abstract)) But Dickie does not explicitly teach: computational graph However, Sui discloses computational graph (“A method to optimize a neural network computational graph, wherein the computational graph is used to execute neural network calculation by a computational platform” (See Abstract)). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sui into the teachings of Dickie because that would have enabled reducing computational complexity and data exchange between an off-chip memory and an on-chip buffer by adopting layer decomposition and operation fusion processes as suggested by Sui (See Abstract). But Dickie and Sui do not explicitly teach: converting the target computational graph into target code according to a reverse conversion rule that is reverse to the preset conversion rule; compiling the target code into obtain machine-executable code; and outputting the machine-executable code to the user. However, Ma discloses: converting the target computational graph into target code according to a reverse conversion rule that is reverse to the preset conversion rule (“The graph compilation optimization layer is configured to convert the computational graph of the model framework into an IR, that is, the computational graph of the deep learning framework is converted into a graph IR of the device model builder or the neural network compiler by the model builder of the access device or the neural network compiler according to the mapping of the ‘operator IR adaptation layer’. The device model builder or the neural network compiler has its own optimization strategy to optimize the IR of the computational graph and ultimately convert it into executable codes that can run on a hardware device.” (See para [0093])); compiling the target code into obtain machine-executable code (The device model builder or the neural network compiler has its own optimization strategy to optimize the IR of the computational graph and ultimately convert it into executable codes that can run on a hardware device.” (See para [0093])); and outputting the machine-executable code to the user (“The graph execution management layer is configured for access of model scheduling and execution functionality of the hardware SDK, to enable a graph execution engine of the model framework or the neural network executor to manage the lifecycle of the computational graph and obtain the final output results” (See para [0094])). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ma into the teachings of Dickie and Sui because that would have been possible to optimize the computational graph associated with the operation of the target model based on the operator representation of the target model and a situation of the access device of the target model, and the computational graph optimization and interface accessing are performed separately. Therefore, improvements on the interface can be made when accessing the interface, so that the improved interface is adaptable to more different access devices, and the difficulty of adapting to different access devices and the amount of modified data are reduced as suggested by Ma (See [0045]). Regarding claim 2: The rejection of claim 1 is incorporated, Dickie further discloses wherein performing the iterative transformations comprises: performing, based on a performance evaluation policy, a performance evaluation on a computational graph from a transformation in at least one of the preset graph transformation manners to obtain a performance evaluation (“The inventors have recognized that the performance of a data processing system would be improved if automatically generated dataflow graphs were further processed and optimized to reduce the amount computational resources used to execute the generated dataflow graphs. Some of the dataflow graph optimization techniques described in this application were developed by the inventors for this reason. The dataflow graph optimization techniques described herein improve the performance (e.g., throughput, speed, accuracy, etc.) of data processing systems by reducing the amount of computational resources (e.g., processor resources, memory resources, network resources, etc.) used for executing the dataflow graphs generated at least in part by using the dataflow graph optimization techniques.” (See para [0039])); and determining the target [[computational]] graph based on the performance evaluation result (“The inventors have recognized that the performance of a data processing system would be improved if automatically generated dataflow graphs were further processed and optimized to reduce the amount computational resources used to execute the generated dataflow graphs. Some of the dataflow graph optimization techniques described in this application were developed by the inventors for this reason. The dataflow graph optimization techniques described herein improve the performance (e.g., throughput, speed, accuracy, etc.) of data processing systems by reducing the amount of computational resources (e.g., processor resources, memory resources, network resources, etc.) used for executing the dataflow graphs generated at least in part by using the dataflow graph optimization techniques.” (See para [0039])). But Dickie does not explicitly teach: computational graph However, Sui discloses computational graph (“A method to optimize a neural network computational graph, wherein the computational graph is used to execute neural network calculation by a computational platform” (See Abstract)) It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sui into the teachings of Dickie because that would have enabled reducing computational complexity and data exchange between an off-chip memory and an on-chip buffer by adopting layer decomposition and operation fusion processes as suggested by Sui (See Abstract). Regarding claim 3: The rejection of claim 1 is incorporated, Dickie further discloses wherein of performing the iterative transformations comprises: selecting, based on a search policy, a to-be-optimized [[computational]] graph in a next iterative transformation from a plurality of [[computational]] graphs (“FIG. 10B illustrates an updated dataflow graph 1050 obtained by iteratively applying optimization rules to the initial dataflow graph shown in FIG. 10A, in accordance with some embodiments of the technology described herein. As may be seen by comparing the initial dataflow graph 1000 of FIG. 10A and updated dataflow graph 1050 of FIG. 10B, the updated dataflow graph has fewer nodes and links than does the initial dataflow graph and may be executed more efficiently than the initial dataflow graph. Detailed below are a number of the optimizations applied to the initial dataflow graph 1000 in accordance with some embodiments of the technology described herein.” (See para [0130])); and performing, based on the preset graph transformation manners, the iterative transformations on the to-be-optimized [[computational]] graph to obtain the target computational graph (“FIG. 10B illustrates an updated dataflow graph 1050 obtained by iteratively applying optimization rules to the initial dataflow graph shown in FIG. 10A, in accordance with some embodiments of the technology described herein. As may be seen by comparing the initial dataflow graph 1000 of FIG. 10A and updated dataflow graph 1050 of FIG. 10B, the updated dataflow graph has fewer nodes and links than does the initial dataflow graph and may be executed more efficiently than the initial dataflow graph. Detailed below are a number of the optimizations applied to the initial dataflow graph 1000 in accordance with some embodiments of the technology described herein.” (See para [0130])). But Dickie does not explicitly teach: computational graph However, Sui discloses computational graph (“A method to optimize a neural network computational graph, wherein the computational graph is used to execute neural network calculation by a computational platform” (See Abstract)) It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sui into the teachings of Dickie because that would have enabled reducing computational complexity and data exchange between an off-chip memory and an on-chip buffer by adopting layer decomposition and operation fusion processes as suggested by Sui (See Abstract). Regarding claim 4: The rejection of claim 1 is incorporated, Dickie further discloses wherein performing the iterative transformations removing, based on a pruning policy, an invalid graph transformation manner from the preset graph transformation manners (“Graph optimizer 110 may be configured to apply one or more of any of numerous types of optimization rules described herein to the initial dataflow graph. For example, graph optimizer 110 may be configured to update the initial dataflow graph by removing one or more redundant data processing operations, removing one or more unreferenced data processing operations, performing one or more strength reduction optimizations, performing one or more combining operations optimizations, performing one or more width reduction optimizations, and/or performing one or more deduplication optimizations” (See para [0071])). Regarding claim 5: The rejection of claim 2 is incorporated, Dickie further comprising further performing the performance evaluation [[based on a calculation operations and memory access operations that are of an abstract syntax tree (AST) corresponding to the computational graph or]] based on a running time of executable code corresponding to the [[computational]] graph (“In some embodiments, during execution of a dataflow graph, data processing operations represented by separate nodes may be executed by different processes running on one or multiple computing devices. A graph optimizer may perform a combining operations optimization by replacing the sequence of three nodes with a single node (e.g., node 508 in dataflow graph 505) so that all the operations are performed by a single process executing on a single computing device, which reduces the overhead of inter-process (and potentially inter-device) communication” (See para [0120])). But Dickie does not explicitly teach: computational graph However, Sui discloses computational graph (“A method to optimize a neural network computational graph, wherein the computational graph is used to execute neural network calculation by a computational platform” (See Abstract)) It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sui into the teachings of Dickie because that would have enabled reducing computational complexity and data exchange between an off-chip memory and an on-chip buffer by adopting layer decomposition and operation fusion processes as suggested by Sui (See Abstract). Regarding claim 6: The rejection of claim 3 is incorporated, Dickie further discloses wherein the search policy is based on performances of the [[computational]] graphs (“The inventors have recognized that the performance of a data processing system would be improved if automatically generated dataflow graphs were further processed and optimized to reduce the amount computational resources used to execute the generated dataflow graphs. Some of the dataflow graph optimization techniques described in this application were developed by the inventors for this reason. The dataflow graph optimization techniques described herein improve the performance (e.g., throughput, speed, accuracy, etc.) of data processing systems by reducing the amount of computational resources (e.g., processor resources, memory resources, network resources, etc.) used for executing the dataflow graphs generated at least in part by using the dataflow graph optimization techniques.” (See para [0039])) But Dickie does not explicitly teach: computational graph However, Sui discloses computational graph (“A method to optimize a neural network computational graph, wherein the computational graph is used to execute neural network calculation by a computational platform” (See Abstract)) It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sui into the teachings of Dickie because that would have enabled reducing computational complexity and data exchange between an off-chip memory and an on-chip buffer by adopting layer decomposition and operation fusion processes as suggested by Sui (See Abstract). Regarding claim 7: The rejection of claim 4 is incorporated, Dickie further discloses wherein the pruning policy comprises at least one of the following: [[a quantity of times of loop tiling performed on a loop logic exceeding a preset threshold;]] a loop interchange being performed on two pieces of loop logic for a plurality of times (“Graph optimizer 110 may be configured to apply one or more of any of numerous types of optimization rules described herein to the initial dataflow graph. For example, graph optimizer 110 may be configured to update the initial dataflow graph by removing one or more redundant data processing operations, removing one or more unreferenced data processing operations, performing one or more strength reduction optimizations, performing one or more combining operations optimizations, performing one or more width reduction optimizations, and/or performing one or more deduplication optimizations” (See para [0071])); Regarding claim 11: This is an apparatus version of the rejected method claim 1 above, wherein all the limitations of this claim have been noted in the rejection of claim 1 and is therefore rejected under similar rationale. Regarding claim 12: The rejection of base claim 11 is incorporated. All the limitations of this claim have been noted in the rejection of claim 2, and is therefore rejected under similar rationale. Regarding claim 13: The rejection of base claim 11 is incorporated. All the limitations of this claim have been noted in the rejection of claim 3, and is therefore rejected under similar rationale. Regarding claim 14: The rejection of base claim 11 is incorporated. All the limitations of this claim have been noted in the rejection of claim 4, and is therefore rejected under similar rationale. Regarding claim 15: The rejection of base claim 11 is incorporated. All the limitations of this claim have been noted in the rejection of claim 5, and is therefore rejected under similar rationale. Regarding claim 16: The rejection of base claim 11 is incorporated. All the limitations of this claim have been noted in the rejection of claim 6, and is therefore rejected under similar rationale. Regarding claim 17: The rejection of base claim 11 is incorporated. All the limitations of this claim have been noted in the rejection of claim 7, and is therefore rejected under similar rationale. Regarding claim 20: This is a computer program product version of the rejected method claim 1 above, wherein all the limitations of this claim have been noted in the rejection of claim 1, and is therefore rejected under similar rationale. Regarding claim 21: The rejection of base claim 20 is incorporated. All the limitations of this claim have been noted in the rejection of claim 2, and is therefore rejected under similar rationale. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HANH THI MINH BUI whose telephone number is (571)270-1976. The examiner can normally be reached Monday - Friday: 7-3. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hyung S. Sough can be reached at 571-272-6799. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HANH THI-MINH BUI/Primary Examiner, Art Unit 2192 December 4th, 2025
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Prosecution Timeline

Jul 07, 2023
Application Filed
Aug 18, 2025
Non-Final Rejection — §101, §103
Oct 29, 2025
Response Filed
Dec 04, 2025
Final Rejection — §101, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
80%
Grant Probability
99%
With Interview (+63.5%)
3y 0m
Median Time to Grant
Moderate
PTA Risk
Based on 582 resolved cases by this examiner. Grant probability derived from career allow rate.

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