DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-12 in the reply filed on 11/26/2025 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 contains the limitation “the alternating stack” in line 22. It is unclear if this is intended to refer to the “first-tier alternating stack” in line 6 or the “second-tier alternating stack” in line 11. For the purposes of examination, “the alternating stack” will be considered to refer to either the first-tier or second-tier alternating stack.
Claims 5-8 depend from claim 4 and, therefore, also contain this limitation.
Claim 4 contains the limitation “the sacrificial material layers” in line 30. It is unclear if this is intended to refer to the “first sacrificial material layers” in lines 6-7, the “second sacrificial material layers” in lines 11-12, or both. For the purposes of examination, “the sacrificial material layers” will be considered to refer to either the first or second sacrificial material layers.
Claims 5-8 depend from claim 4, and therefore, also contain this limitation.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong et al. (U.S. Patent Application Publication 2008/0241384, hereafter Jeong ‘384).
Claim 1: Jeong ‘384 teaches a deposition method (abstract) comprising:
forming a first portion of a layer over a substrate by flowing a reactant gas past the substrate in a first direction (abstract, Fig. 1A, [0010]); and
forming a second portion of the layer on the first portion by flowing the reactant gas past the substrate in a second direction different from the first direction (abstract, Fig. 1B, [0010]).
Claim 11: Jeong ‘384 teaches that the reactant gas can be a chemical vapor deposition source gas ([0024], [0042]), forming the first portion of the layer comprises depositing the first portion of the layer by CVD using the source gas flowing past the substrate in the first direction ([0010], [0042]), and forming the second portion of the layer comprises depositing the second portion of the layer by CVD using the source gas flowing past the substrate in the second direction ([0010], [0042]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. ‘384 as applied to claim 1 above.
Claim 12: Jeong ‘384 teaches the limitations of claim 1, as discussed above. Jeong ‘384 further teaches that the method can comprise providing the substrates and a plurality of additional substrates into a vacuum chamber ([0067], [0071]), forming the first portion of the layer over the substrates by flowing a reactant gas past the substrates in a first direction (abstract, Fig. 1A, [0010], [0067]), and forming the second portion of the layer on the first portion by flowing the reactant gas past the substrates in the second direction (abstract, Fig. 1B, [0010], [0067]).
With respect to claim 12, Jeong ‘384 does not explicitly teach that the substrates are arranged as a stack.
However, the claimed method differs from the method taught by Jeong ‘384 only in the arrangement of the substrates, and it has been held that rearrangement of parts is obvious in the absence of new or unexpected results. See MPEP 2144.04.VI.C.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Obu et al. (U.S. Patent Application Publication 2021/0265380, hereafter Obu ‘380) in view of Jeong et al. ‘384.
Claim 1: Obu ‘380 teaches a deposition method for semiconductor devices (abstract, [0001]) comprising forming a first portion of a layer (lower half of 51) over a substrate (112) by exposing it to an oxidizing gas (Fig. 9B, [0109], [0110]), and forming a second portion of the layer (upper half of 51) on the first portion of the layer by exposing the substrate to the oxidizing gas (Fig. 9B, [0109], [0110]).
With respect to claim 1, Obu ‘380 does not explicitly teach that the forming the first portion includes flowing the gas in a first direction and forming the second portion includes flowing the gas in a second direction different from the first direction.
Jeong ‘384 teaches a deposition method for semiconductor devices (abstract, [0005]) comprising forming a first portion of a layer over a substrate by flowing a reactant gas past the substrate in a first direction (abstract, Fig. 1A, [0010]), and forming a second portion of the layer on the first portion by flowing the reactant gas past the substrate in a second direction different from the first direction (abstract, Fig. 1B, [0010]). Jeong ‘384 teaches that flowing the gas in a first direction in the first step and a second, different direction in the second step improves thickness uniformity of the formed layer (abstract, [0024]). Both Jeong ‘384 and Obu ‘380 teach deposition methods for semiconductor devices (‘380, abstract, [0001]; ‘384, abstract, [0005]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the gas flow in a first direction in the first step and a second, different direction in the second step as taught by Jeong ‘384 in the method taught by Obu ‘380 because it improves thickness uniformity of the formed layer, as taught by Jeong ‘384.
Claim 2: Obu ‘380 teaches that the reactant gas can be an oxidant ([0109], [0110]), forming the first portion of the layer can comprise forming a first portion of a semiconductor oxide layer by oxidizing a portion of a first semiconductor layer (112) over the substrate using the oxidant ([0109], [0110]), and forming the second portion of the layer can comprise forming a second portion of the semiconductor oxide layer using the oxidant ([0109], [0110]).
Claim 3: Obu ‘380 teaches that the first semiconductor layer can be a silicon layer ([0060]), and the semiconductor oxide layer can be a silicon oxide layer ([0109], [0110]).
With respect to claim 3, the modified teachings of Obu ‘380 do not explicitly teach that the second direction is opposite to the first direction.
Jeong ‘384 teaches a deposition method for semiconductor devices (abstract, [0005]) comprising forming a first portion of a layer over a substrate by flowing a reactant gas past the substrate in a first direction (abstract, Fig. 1A, [0010]), and forming a second portion of the layer on the first portion by flowing the reactant gas past the substrate in a second direction different from the first direction (abstract, Fig. 1B, [0010]). Jeong ‘384 teaches that the second direction can be opposite to the first direction (abstract, Figs. 1A-B). Both Jeong ‘384 and Obu ‘380 teach deposition methods for semiconductor devices (‘380, abstract, [0001]; ‘384, abstract, [0005]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second direction be opposite to the first direction as taught by Jeong ‘384 in the method taught by the modified teachings of Obu ‘380 because it would have been a simple substitution that would have yielded predictable results.
Claim 4: Obu ‘380 teaches that the method can further comprise:
forming a source-level sacrificial layer (104) over the first semiconductor layer which comprises a lower source-level semiconductor layer (103) (Figs. 1A-C, [0059]);
forming an upper source-level semiconductor layer (116) over the source-level sacrificial layer (Figs. 1A-C, [0059]);
forming a first-tier alternating stack of first insulating layers (132) and first sacrificial material layers (142) over the upper source-level semiconductor layer (Fig. 2, [0073]);
forming first-tier memory openings (149) through the first-tier alternating stack, the upper source-level semiconductor layer, the source-level sacrificial layer, and at least part of the lower source-level semiconductor layer (Fig. 4A, [0082], [0086]);
forming sacrificial first-tier opening fill portions (148) in the first-tier memory openings (Fig. 5, [0088]);
forming a second tier alternating stack of second insulating layers (232) and second sacrificial material layers (242) (Fig. 6, [0094], [0095]);
forming second tier memory openings (249) through the second tier alternating stack to expose the sacrificial first tier opening fill portions (Fig. 7A, [0102]);
removing the sacrificial first tier opening fill portions through the second tier memory openings to form inter tier memory openings (49) comprising a combination of respective first tier memory openings and second tier memory openings (Fig. 8, [0106]);
forming memory stack structures (55) in the inter tier memory openings where each memory stack structure comprises a vertical semiconductor channel and a memory film (Figs. 9A-I, [0126]);
forming a backside trench (79) vertically extending through the first tier and second tier alternating stacks, the upper source-level semiconductor layer, and at least part of the source level sacrificial layer (Fig. 13A, [0135]);
removing the source-level sacrificial layer through the backside trench to form a source cavity (109) (Fig. 15B, [0137]);
exposing sidewalls of the vertical semiconductor channels through the source cavity (Figs. 15B-C, [0137], [0138]);
forming a source contact layer (114) in the source cavity through the backside trench wherein the source contact layer contacts the sidewalls of the vertical semiconductor channels exposed in the source cavity (Fig. 15D, [0143]); and
replacing the first and second sacrificial material layers with electrically conductive layers (146, 246) through the backside trench (Figs. 17-18, [0155], [0161]).
Claim 5: Obu ‘380 teaches that forming the semiconductor oxide layer can comprise forming a first silicon oxide portion on a portion of the lower source-level semiconductor layer exposed in each of the first tier memory openings ([0089]).
Claim 6: Obu ‘380 teaches that the first silicon oxide portion on the lower source-level semiconductor layer exposed in each of the first tier memory openings can act as an etch stop layer during removal of the sacrificial first tier opening fill portions ([0089]) and, therefore, protect the underlying lower source-level semiconductor layer.
Claim 7: Obu ‘380 teaches that forming the first silicon oxide portion on the lower source-level semiconductor layer exposed in each of the first tier memory openings can also comprise forming a second silicon oxide portion on the upper-source semiconductor layer exposed in each of the first tier memory openings ([0089]), where both silicon oxide portions are formed in the same step ([0089]).
Claim 8: Obu ‘380 teaches that the first and second silicon oxide portions can be removed after removing the sacrificial first-tier opening fill portions and before forming the memory stack structures (Fig. 9A, [0106], [0107]).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Obu et al. ‘380 in view of Jeong et al. ‘384 as applied to claim 2 above, and further in view of LaVoie (U.S. Patent Application Publication 2018/0138040, hereafter LaVoie ‘040).
The modified teachings of Obu ‘380 teach the limitations of claim 2, as discussed above. With respect to claim 9, they do not explicitly teach that the oxidant gas comprises water vapor.
LaVoie ‘040 teaches a deposition method for semiconductor devices (abstract, [0001]) comprising forming a semiconductor oxide by oxidizing portions of a semiconductor layer using an oxidant gas ([0059]). LaVoie ‘040 teaches that water vapor is a suitable material for the oxidant gas ([0059]). Both LaVoie ‘040 and Obu ‘380 teach deposition methods for semiconductor devices (‘380, abstract, [0001]; ‘040, abstract, [0001]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the water vapor taught by LaVoie ‘040 as the oxidant gas used in the method taught by the modified teachings of Obu ‘380 because it is a suitable material for an oxidant gas for forming a semiconductor oxide by oxidizing portions of a semiconductor layer, as taught by LaVoie ‘040. See MPEP 2144.07.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. ‘384 as applied to claim 1 above, and further in view of Kamakura et al. (U.S. Patent Application Publication 2021/0217608, hereafter Kamakura ‘608).
Jeong ‘384 teaches the limitations of claim 1, as discussed above. Jeong ‘384 further teaches that the method is for semiconductor devices ([0005]).
With respect to claim 10, Jeong ‘384 does not explicitly teach that the reactant gas comprises ammonia, that forming the first portion of the layer comprise forming a first portion of a semiconductor nitride layer by nitriding a portion of a first semiconductor layer, or that forming the second portion of the layer comprises forming a second portion of the semiconductor nitride layer.
Kamakura ‘608 teaches a deposition method of making for semiconductor devices (abstract, [0002], [0003]) comprising supplying a reactant gas to a substrate to form a layer ([0020], [0068]). Kamakura ‘608 teaches that the reactant gas can be ammonia, the formed layer can be a silicon nitride layer, and the substrate can be a semiconductor layer ([0068]). Both Kamakura ‘608 and Jeong ‘384 teach deposition method of making for semiconductor devices (‘384, abstract, [0005]; ‘608, abstract, [0002], [0003]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the ammonia reactant gas, silicon nitride layer, and semiconductor layer taught by Kamakura ‘608 as the reactant gas, formed layer, and substrate, respectively, in the method taught by the Jeong ’384 because it would have been a simple substitution that would have yielded predictable results.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADFORD M GATES whose telephone number is (571)270-3558. The examiner can normally be reached Monday-Friday 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Allen can be reached at (571) 270-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BG/
/JOSHUA L ALLEN/Supervisory Patent Examiner, Art Unit 1713