DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
For claim 6, the recitation “a differential input signal and a corresponding delayed input signal” on lines 3-4 is indefinite because it is not clear if “a differential input signal and a corresponding delayed input signal” are the same or different signals with “one of the first differential input signal (IN_A) or the second differential input signal (IN_B) and a corresponding one of the first delayed input signal (IN_A_DLY) or the second delayed input signal (IN_B_DLY)” recited earlier in claim 1 (see lines 18-22, claim 1). To overcome this problem, it is suggested that the recitation “if both a differential input signal and a corresponding delayed input signal have a same signal state” on lines 3-4 be changed to “in response to the one of the first differential input signal (IN_A) or the second differential input signal (IN_B) having a same logic state as the corresponding one of the first delayed input signal (IN_A_DLY) or the second delayed input signal (IN_B_DLY)”. Clarification and/or appropriate correction is required.
For claim 7, the recitation “the control signal” on line 2 lacks clear antecedent basis and should be changed to “a control signal”. Further, the recitation “a differential input signal having a same logic state as a corresponding delayed input signal” is indefinite because it is not clear if “a differential input signal” and “a corresponding delayed input signal” in the above phrase are the same or different signals with “one of the first differential input signal (IN_A) or the second differential input signal (IN_B)” and “a corresponding one of the first delayed input signal (IN_A_DLY) or the second delayed input signal (IN_B_DLY)”, respectively, recited earlier in claim 1 (see lines 18-22, claim 1). To overcome this problem, it is suggested that the recitation
“a differential input signal having a same logic state as a corresponding delayed input signal” on lines 2-3 be changed to “the one of the first differential input signal (IN_A) or the second differential input signal (IN_B) having a same logic state as the corresponding one of the first delayed input signal (IN_A_DLY) or the second delayed input signal (IN_B_DLY)”. Clarification and/or appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 9-10 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Virgil (USP 7,236,020).
For claim 1, Figure 2 of Virgil teaches: a level shifter circuit (Figure 2), comprising: an input port (219) configured to receive an input signal (IN HIGH); an output port (output of driver 246 DRVA) configured to transmit an output signal; a converter circuit (INV9 435 inside 210a of Figure 4a, wherein Figure 4a is a detail of 210 in Figure 2) configured to generate a first differential input signal (IN in Figure 4a) and a second differential input signal (/IN which is output of INV9 435 in Figure 4a) from the input signal (IN in Figure 4 which is IN HIGH in Figure 2); a delay circuit (all elements in Figure 4a except for INV9 435) including: a first delay chain (NAND1, and INV1-INV3) configured to generate a first delayed input signal (output of INV3) from the first differential input signal (IN), and a second delay chain (NAND2, INV5-INV7) configured to generate a second delayed input signal (output of INV7) from the second differential input signal (/IN which is output of INV9); wherein the first delay chain (NAND1, and INV1-INV3) includes a first logic gate (NAND1) coupled to receive both the first differential input signal (IN) and the second delayed input signal (output of INV7) from the second delay chain (NAND2, INV5-INV7); wherein the second delay chain (NAND2, INV5-INV7) includes a second logic gate (NAND2) coupled to receive both the second differential input signal (/IN which is output of INV9) and the first delayed input signal (output of INV3) from the first delay chain (NAND1, and INV1-INV3); a pulse generator (Figure 2, EDGE DETECTOR CHANNEL HIGH 212 which is shown in detail in Figure 5a or 5c; AND 290 and MN1) coupled to the delay circuit and configured to generate a pulse signal (drain of MN1 which is input of INVA1) from a combination of one of the first differential input signal (IN, Figure 2) or the second differential input signal (/IN which is output of INV9, Figure 2) and a corresponding one of the first delayed input signal (output of INV3, Figure 2) or the second delayed input signal (output of INV7, Figure 2); and a latch circuit (Figure 2, DFF1 254) coupled to the pulse generator and configured to generate and hold a state of the output signal (output of DRVA) in response to the pulse signal.
For claim 2, Figure 2 of Virgil teaches wherein the pulse generator (Figure 2, EDGE DETECTOR CHANNEL HIGH 212 which is shown in detail in Figure 5a or 5c; AND 290 and MN1) is coupled to the input port (219) and configured to generate the pulse signal (drain of MN1 which is input of INVA1) in response to either a rising edge or a falling edge of the input signal (219).
For claim 3, Figure 2 of Virgil teaches wherein the state of the output signal (output of DRVA) is a first state in response to a rising edge of the input signal (219); and wherein the state of the output signal (output of DRVA) is a second state in response to a falling edge of the input signal (219).
For claim 4, Figure 2 of Virgil teaches wherein the pulse generator (Figure 2, EDGE DETECTOR CHANNEL HIGH 212 which is shown in detail in Figure 5a or 5c; AND 290 and MN1) includes a switch (MN1) coupled to an AND gate (290).
For claim 5, Figure 2 of Virgil teaches wherein the AND gate (290) is configured to generate a control signal (output OUT of AND gate 290); and wherein the switch (MN1) is configured to generate the pulse signal (drain of MN1) sent to the latch circuit (DFF1 254) in response to the control signal (output OUT of AND gate 290) from the AND gate (290).
For claim 6, Figure 2 of Virgil teaches wherein the AND gate (290) is configured to generate the control signal (output OUT of AND 290) in response to the one of the first differential input signal (IN, Figure 4a) or the second differential input signal (/IN which is output of INV9, Figure 4A) having a same logic state as the corresponding one of the first delayed input signal (output of INV3, Figure 4a) or the second delayed input signal (output of INV7, Figure 4a).
For claim 7, Figure 2 of Virgil teaches wherein the AND gate (290) is configured to generate a control signal (output OUT of AND 290) in response to the one of the first differential input signal (IN, Figure 4a) or the second differential input signal (/IN which is output of INV9, Figure 4A) having a same logic state as the corresponding one of the first delayed input signal (output of INV3, Figure 4a) or the second delayed input signal (output of INV7, Figure 4a); and wherein the switch (MN1) is configured to generate the pulse signal (drain of MN1) in response to the control signal (output OUT of AND 290).
For claim 9, Figure 2 of Virgil teaches wherein a first instance of the pulse signal (drain of MN1) sets the state of the output signal (output of DRVA) from the latch circuit (DFF1 254) to a first state; and wherein a second instance of the pulse signal (drain of MN1) sets the state of the output signal (output of DRVA) from the latch circuit (DFF1 254) to a second state.
For claim 10, Figure 2 of Virgil teaches wherein the output signal (output of DRVA) has a higher voltage (HV + (Vdd-Vd1)) than the input signal (219). Note that the level shifter circuit in Figure 2 is also a low-to-high voltage level shifter (see title, and Col. 1, lines 8-12).
For claim 14, Figure 4a of Virgil teaches wherein the first logic gate (NAND1) is a first NAND gate (NAND1); and wherein the second logic gate (NAND2) is a second NAND gate (NAND2).
Allowable Subject Matter
Claims 15-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 20-21 and 23-24, as amended, are allowed.
Response to Arguments
Applicant’s arguments filed on 04/29/26 have been considered but are moot in view of the new ground of rejection(s).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch, can be reached at (571) 270-7101. The fax number for this group is (571) 273-8300.
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/Long Nguyen/
Primary Examiner
Art Unit 2836
Prosecution Insights