Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is in respond to the amendment filed on 09/12/25.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7, 9-10, and 14-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
For claim 1, the recitations “a delay circuit coupled to generate a delayed input signal (IN_DLY) having a same polarity as the polarity of the input signal (IN) from the input signal (IN); a pulse generator coupled to the delay circuit and configured to generate a pulse signal from an output of an AND gate that receives as inputs the input signal (IN) having the polarity and the delayed input signal (IN_DLY) having the same polarity as the polarity of the input signal (IN); and a latch circuit coupled to the pulse generator and configured to generate and hold a state of the output signal in response to the pulse signal; a converter circuit configured to generate a first differential input signal (IN_A) and a second differential input signal (IN_B) from the input signal (IN); wherein the delay circuit includes a first delay chain configured to generate a first delayed input signal (IN_A_DLY) from the first differential input signal (IN_A); wherein the delay circuit includes a second delay chain configured to generate a second delayed input signal (IN_B_DLY) from the second differential input signal (IN_B); wherein the first delay chain includes a first logic gate coupled to receive both the first differential input signal (IN_A) and the second delayed input signal (IN_B_DLY) from the second delay chain; and wherein the second delay chain includes a second logic gate coupled to receive both the second differential input signal (IN_B) and the first delayed input signal (IN_A_DLY) from the first delay chain” recited on lines 4-23 cause the claim to be indefinite because:
it is not clear if “a first delayed input signal (IN_A_DLY” (line 14-15) and “a second delayed input signal (IN_B_DLY)” (line 16-17) are in addition of “a delayed input signal (IN_DLY)” (line 4) of the delay circuit. It is also not understood why the claim first recited “a delay circuit coupled to generate a delayed input signal (IN_DLY) having a same polarity as the polarity of the input signal (IN) from the input signal (IN); a pulse generator coupled to the delay circuit and configured to generate a pulse signal from an output of an AND gate that receives as inputs the input signal (IN) having the polarity and the delayed input signal (INDLY) having the same polarity as the polarity of the input signal (IN); and a latch circuit coupled to the pulse generator and configured to generate and hold a state of the output signal in response to the pulse signal” (claim 1, lines 4-11) which refers to the level shifter in Figure 1; then also recited in the same claim “a converter circuit configured to generate a first differential input signal (INA) and a second differential input signal (INB) from the input signal (IN); wherein the delay circuit includes a first delay chain configured to generate a first delayed input signal (IN A DLY) from the first differential input signal (IN A); wherein the delay circuit includes a second delay chain configured to generate a second delayed input signal (IN B DLY) from the second differential input signal (IN B); wherein the first delay chain includes a first logic gate coupled to receive both the first differential input signal (INA) and the second delayed input signal (IN B DLY) from the second delay chain; and wherein the second delay chain includes a second logic gate coupled to receive both the second differential input signal (INB) and the first delayed input signal (IN A DLY) from the first delay chain” which refers to the level shifter in Figures 2A-2C; and Figure 2A-2C shows first and second pulse generators coupled to respective first and second delay chains of the delay circuit and configured to generate respective first and second pulse signals from respective first and second AND gates that receives as inputs the respective first and second differential signals and the respective first and second delayed input signals (i.e., not “a pulse generator coupled to the delay circuit and configured to generate a pulse signal from an output of an AND gate that receives as inputs the input signal (IN) having the polarity and the delayed input signal (IN_DLY) having the same polarity as the polarity of the input signal (IN)” which is recited on lines 6-9 of the claim). Clarification and/or appropriate correction is required.
Claims 2-7, 9-10, 14-19 and 22 are indefinite because they depend on claim 1 and includes the indefinite problems of claim 1.
Also, for claim 5, the recitation “wherein the switch is configured to send the pulse signal to the latch circuit in response to a signal from the output of the AND gate” is indefinite because claim 1 already recited that a pulse generator generates a pulse signal from an output of an AND gate (see lines 6-7 of claim 1), so it is not understood why claim 5 now recites “the switch is configured to send the pulse signal to the latch circuit in response to a signal from the output of the AND gate”, so it is not clear if the pulse signal is output from the output of the AND gate (as recited in claim 1), or the switch outputs the pulse signal in response to a signal from the output of the AND gate” (as recited in claim 5). Further, the recitation “a signal from the output of the AND gate” recited in the claim is also indefinite because claim 1 already recited “a pulse signal from an output of an AND gate (see lines 6-7 of claim 1), so it is not clear now it is recited “a signal from the output of the AND gate”. Clarification and/or appropriate correction is required.
Claim 6 is indefinite because it depends on claim 5. Also, the recitation “wherein the AND gate is configured to generate the signal from the output of the AND gate” also is indefinite for the same reasons as discussed in claim 5 above. Clarification and/or appropriate correction is required.
For claim 7, the recitation “wherein the AND gate and the switch are configured to generate the pulse signal” is indefinite because claim 1 already recited that a pulse generator generates a pulse signal from an output of an AND gate (see lines 6-7 of claim 1), so it implied that the AND gate generates the pulse signal (“a pulse signal from an output of an AND gate”, see line 6-7 of claim 1), and thus it is not understood why it is now recited “wherein the AND gate and the switch are configured to generate the pulse signal”. Clarification and/or appropriate correction is required.
For claim 15, the recitation “wherein the AND gate is a first AND gate … wherein the first AND gate is coupled to logically AND the first differential input signal (IN_A) with the first delayed input signal (IN_A_DLY) to create the first pulse signal” (recited on lines 7-8) causes the claim to be indefinite because it is recited in the claim 1 that “a pulse signal from an output of an AND gate that receives as inputs the input signal (IN) having the polarity and the delayed input signal (IN_DLY) having the same polarity as the polarity of the input signal (IN)” (see claim 1, lines 6-9) so it is not understood why the claim is now recited “wherein the first AND gate is coupled to logically AND the first differential input signal (INA) with the first delayed input signal (IN_A_DLY) to create the first pulse signal” (see lines 7-8, and it is noted that the AND gate is a first AND gate), and thus it is not clear which signals are received by the AND gate (which is the first AND gate) to generate the pulse signal (which also is the first pulse signal). Clarification and/or appropriate correction is required.
Claims 16-19 are indefinite because they depend on claim 15.
Also, for claim 17, the recitation “wherein the latch circuit is a first differential latch circuit coupled to the first and second pulse generators; and wherein the first differential latch circuit is configured to generate and hold a state of the output signal in response to the first differential latch signal (Xn) and the second differential latch signal (Xp)” causes the claim to be indefinite because the claim originally recited “a latch circuit coupled to the pulse generator and configured to generate and hold a state of the output signal in response to the pulse signal” (claim 1, lines 10-11), so it is not clear why so it is not clear what exactly signals the latch (which is the first differential latch) response to because claim 17 now recited “in response to the first differential latch signal (Xn) and the second differential latch signal (Xp)”. Clarification and/or appropriate correction is required.
Claim 18 is also indefinite because it depends on claim 17.
For claim 20, the recitations “a delay circuit coupled to generate a delayed input signal (IN_DLY) from the input signal (IN)” (recited on lines 4-5) and “wherein the delay circuit includes a first delay chain configured to generate a first delayed input signal (IN_A_DLY) from the first differential input signal (IN_A); wherein the delay circuit includes a second delay chain configured to generate a second delayed input signal (IN_B_DLY) from the second differential input signal (IN_B)” (recited on lines 12-15) cause the claim to be indefinite because it is not clear it is not clear if “a first delayed input signal (IN_A_DLY)” (line 14-15) and “a second delayed input signal (IN_B_DLY)” (line 16-17) are in addition of “a delayed input signal (IN_DLY)” (line 4) of the delay circuit. Further, the claim is also indefinite because it is also not understood why the claim first recited “a pulse generator coupled to the delay circuit and configured to generate a pulse signal from a combination of the input signal and the delayed input signal” (lines 6-7); and then also recited “wherein the pulse signal is a first pulse signal; wherein the pulse generator is a first pulse generator coupled to the delay circuit and configured to generate a first differential latch signal (Xn) from the first pulse signal generated by a combination of the first delayed input signal (IN_A_DLY) and the first differential input signal (INA)” (lines 16-20); so it is not clear whether the pulse generator (which is the first pulse generator) generates a pulse signal from a combination of the input signal and the delayed input signal (as recited on lines 6-7) or whether it generates “a first differential latch signal (Xn) from the first pulse signal generated by a combination of the first delayed input signal (IN_A_DLY) and the first differential input signal (INA)” (as recited on lines 16-20); and it is not clear what exact signals the pulse generator receives since the claim first recited “a pulse generator coupled to the delay circuit and configured to generate a pulse signal from a combination of the input signal and the delayed input signal” (lines 6-7); and then also recited “wherein the pulse signal is a first pulse signal; wherein the pulse generator is a first pulse generator coupled to the delay circuit and configured to generate a first differential latch signal (Xn) from the first pulse signal generated by a combination of the first delayed input signal (IN_A_DLY) and the first differential input signal (INA)” (lines 16-20). Further, it is also not clear why the claim recited “a latch circuit … in response to the pulse signal” (lines 8-9) then later recited “wherein the latch circuit is a first differential latch circuit coupled to the first and second pulse generators; wherein the first differential latch circuit is configured to generate and hold a state of the output signal in response to the first differential latch signal (Xn) and the second differential latch signal (Xp)” (lines 25-29), so it is not clear what exactly signals the latch (which is the first differential latch) response to. Clarification and/or appropriate correction is required.
For claim 21, the recitations “a delay circuit coupled to generate a delayed input signal (IN_DLY) from the input signal (IN)” (recited on lines 4-5) and “wherein the delay circuit includes a first delay chain configured to generate a first delayed input signal (IN_A_DLY) from the first differential input signal (IN_A); wherein the delay circuit includes a second delay chain configured to generate a second delayed input signal (IN_B_DLY) from the second differential input signal (IN_B)” (recited on lines 13-16) cause the claim to be indefinite because it is not clear it is not clear if “a first delayed input signal (IN_A_DLY)” (line 14) and “a second delayed input signal (IN_B_DLY)” (line 16) are in addition of “a delayed input signal (IN_DLY)” (line 4) of the delay circuit. Further, the claim is also indefinite because it is also not understood why the claim first recited “a pulse generator coupled to the delay circuit and configured to generate a pulse signal from an output of an AND gate that receives a inputs the input signal (IN) and the delayed input signal (IN_DLY)” (lines 6-8); and then also recited “wherein the AND gate is a first AND gate … wherein the first AND gate is coupled to logically AND the first differential input signal (IN_A) with the first delayed input signal (IN_A_DLY) to create the first pulse signal” (recited on lines 25 and 28-29), and thus it is not clear which signals are received by the AND gate (which is the first AND gate) to generate the pulse signal (which also is the first pulse signal, see line 24). Clarification and/or appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 9, 10, and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiu (USP 10,790,826).
Insofar as understood in claim 1, Figures 5 and 11 of Chiu teaches a level shifter circuit, comprising: an input port (IN) configured to receive an input signal (IN) having a polarity; an output port (OUT, or OUTB) configured to transmit an output signal (OUT, or OUTB); a delay circuit (INV-INV-XOR, Figure 11, see Col. 8, lines 4-16) coupled to generate a delayed input signal (IND or output of XOR, Figure 11) having a same polarity as the polarity of the input signal (IN) from the input signal (IN); a pulse generator (B2 in 52a and NLD1, also see Figure 11, and Col. 8, lines 4-16) coupled to the delay circuit (INV-INV-XOR in Figure 11 of 52a, see Col. 8, lines 4-16) and configured to generate a pulse signal (I5a) from an output of an AND gate (B2, Figure 11) that receives as inputs the input signal (IN) having the polarity and the delayed input signal (IND or output XOR) having the same polarity as the polarity of the input signal (IN); and a latch circuit (560) coupled to the pulse generator (B2 in 52a and NLD1, also see Figure 11, and Col. 8, lines 4-16) and configured to generate and hold a state of the output signal (OUT, OUTB) in response to the pulse signal (I5a); a converter circuit (an inverter, see Col. 5, lines 37-52, which recites “In addition, an inverter is required to generate the inverted input signal IBN from the input signal IN”) to generate a first differential input signal (IN) and a second differential input signal (INB) from the input signal (IN); wherein the delay circuit includes a first delay chain (INV-INV in Figure 11 inside of 52a, see Col. 8, lines 4-16) configured to generate a first delayed input signal (IND of Figure 11 inside 52a, see Col. 8, lines 4-16) from the first differential input signal (IN); and wherein the delay circuit includes a second delay chain (INV-INV in Figure 11 inside of 52b, see Col. 8, lines 4-16) configured to generate a second delayed input signal (IND of Figure 11 inside 52b, see Col. 8, lines 4-16) from the second differential input signal (INB). Note that because the newly added limitations “wherein the delay circuit includes a first delay chain configured to generate a first delayed input signal (IN_A_DLY) from the first differential input signal (IN_A); wherein the delay circuit includes a second delay chain configured to generate a second delayed input signal (IN_B_DLY) from the second differential input signal (IN_B); wherein the first delay chain includes a first logic gate coupled to receive both the first differential input signal (INA) and the second delayed input signal (IN B DLY) from the second delay chain; and wherein the second delay chain includes a second logic gate coupled to receive both the second differential input signal (INB) and the first delayed input signal (IN_A_DLY) from the first delay chain” is indefinite as discussed above, so it is not clear how much patentable weight can be given at this time.
Insofar as understood in claim 2, Figures 5 and 11 of Chiu teaches wherein the pulse generator (B2 in 52a and NLD1, also see Figure 11, and Col. 8, lines 4-16) is coupled to the input port (IN) and configured to generate the pulse signal (I5a) in response to either a rising edge or a falling edge of the input signal (IN).
Insofar as understood in claim 3, Figures 5 and 11 of Chiu teaches wherein the state of the output signal (OUT, OUTB) is a first state in response to a rising edge of the input signal (IN, see Figure 6); and wherein the state of the output signal (OUT, OUTB) is a second state in response to a falling edge of the input signal (IN, see Figure 6).
Insofar as understood in claim 4, Figures 5 and 11 of Chiu teaches wherein the pulse generator (B2 in 52a and NLD1, also see Figure 11, and Col. 8, lines 4-16) includes a switch (NLD1) coupled to the AND gate (B2).
Insofar as understood in claim 5, Figures 5 and 11 of Chiu teaches wherein the switch (NLD1) is configured to send the pulse signal (I5a) to the latch circuit (560) in response to a signal (PSS1a which is the PS1 signal that is the output of AND gate B2) from the output of the AND gate (B2).
Insofar as understood in claim 6, it is seen in the operation of Figures 5 and 11 of Chiu that teaches wherein the AND gate (B2) is configured to generate the signal (PSS1a which is the PS1 signal that is the output of AND gate B2) from the output of the AND gate (PS1) if both the input signal (IN) and the delayed input signal (output of XOR) have the same signal state.
Insofar as understood in claim 7, it is seen in the operation of Figures 5 and 11 of Chiu that teaches wherein the AND gate (B2) and the switch (NLD1) are configured to generate the pulse signal (I5a) in response to the input signal (IN) have the same logic state as the delayed input signal (output of XOR).
Insofar as understood in claim 9, Figures 5 and 11 of Chiu teaches wherein a first instance of the pulse signal (PSS1a, I5a) sets the state of the output signal (OUT, OUTB) from the latch circuit (560) to a first state; and wherein a second instance of the pulse signal (PSS1a, I5a) sets the state of the output signal (OUT, OUTB) from the latch circuit (560) to a second state (also see Figure 6).
Insofar as understood in claim 10, Figures 5 and 11 of Chiu teaches wherein the output signal (OUT) has a higher voltage than the input signal (IN), (see Figures 2 and 6, and Col. Line 65 to Col. 3, line 22).
Insofar as understood in claim 22, Figures 5 and 11 of Chiu teaches wherein the polarity (the signal IN) is either a non-inverted polarity of an inverted polarity.
Claims 1-7, 9, 10 and 22 are also rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong (US 2006/0139059).
Insofar as understood in claim 1, Figures 1-2 of Jeong teaches a level shifter circuit, comprising: an input port (IN) configured to receive an input signal (IN) having a polarity; an output port (OUT) configured to transmit an output signal (OUT); a delay circuit (INV1-INV4) coupled to generate a delayed input signal (output INV4) having a same polarity as the polarity of the input signal (IN) from the input signal (IN); a pulse generator (NAND-INV5 and NMOS1) coupled to the delay circuit (INV1-INV4) and configured to generate a pulse signal (NA) from an output of an AND gate (output of INV5) that receives as inputs the input signal (IN) having the polarity and the delayed input signal (output of INV4) having the same polarity as the polarity of the input signal (IN); and a latch circuit (PMOS1-PMOS2) coupled to the pulse generator (NAND-INV5 and NMOS1) and configured to generate and hold a state of the output signal (OUT) in response to the pulse signal (NA); a converter circuit (INV1) configured to generate a first differential input signal (IN) and a second differential input signal (output of INV1) from the input signal (IN). Note that because the newly added limitations “wherein the delay circuit includes a first delay chain configured to generate a first delayed input signal (IN_A_DLY) from the first differential input signal (IN_A); wherein the delay circuit includes a second delay chain configured to generate a second delayed input signal (IN_B_DLY) from the second differential input signal (IN_B); wherein the first delay chain includes a first logic gate coupled to receive both the first differential input signal (INA) and the second delayed input signal (IN B DLY) from the second delay chain; and wherein the second delay chain includes a second logic gate coupled to receive both the second differential input signal (INB) and the first delayed input signal (IN_A_DLY) from the first delay chain” is indefinite as discussed above, so it is not clear how much patentable weight can be given at this time.
Insofar as understood in claim 2, Figures 1-2 of Jeong teaches wherein the pulse generator (NAND-INV5 and NMOS1) is coupled to the input port (IN) and configured to generate the pulse signal (NA) in response to either a rising edge or a falling edge of the input signal (IN).
Insofar as understood in claim 3, Figures 1-2 of Jeong teaches wherein the state of the output signal (OUT) is a first state in response to a rising edge of the input signal (IN); and wherein the state of the output signal (OUT) is a second state in response to a falling edge of the input signal (IN).
Insofar as understood in claim 4, Figure 1-2 of Jeong teaches wherein the pulse (NAND-INV5 and NMOS1) includes a switch (NMOS1) coupled to the AND gate (NAND).
Insofar as understood in claim 5, Figures 1-2 of Chiu teaches wherein the switch (NMOS1) is configured to send the pulse signal (NA) to the latch circuit (PMOS1-PMOS2) in response to a signal (output of INV5) from the output of the AND gate (NAND-INV5).
Insofar as understood in claim 6, Figures 1-2 of Jeong teaches wherein the AND gate (NAND-INV5) is configured to generate the signal (output of INV5) from the output of the AND gate (NAND-INV5) if both the input signal (IN) and the delayed input signal (output of INV4) have the same signal state.
Insofar as understood in claim 7, Figures 1-2 of Jeong teaches wherein the AND gate (NAND-INV5) and the switch (NMOS1) are configured to generate the pulse signal (NA) in response to the input signal (IN) have the same logic state as the delayed input signal (output of INV4).
Insofar as understood in claim 9, Figures 1-2 of Jeong teaches wherein a first instance of the pulse signal (NA) sets the state of the output signal (OUT) from the latch circuit (PMOS1-PMOS2) to a first state; and wherein a second instance of the pulse signal (NA) sets the state of the output signal (OUT) from the latch circuit (560) to a second state.
Insofar as understood in claim 10, Figures 1-2 of Jeong teaches wherein the output signal (OUT) has a higher voltage than the input signal (IN), (see [0005]-[0022]).
Insofar as understood in claim 22, Figures 1-2 of Jeong teaches wherein the polarity (the signal IN) is either a non-inverted polarity of an inverted polarity.
Response to Arguments
Applicant’s arguments filed 09/12/25 have been considered but are moot in view of the new ground rejection(s): note the 112(b) rejections regarding the indefinite problems of the claim, so the prior art rejections are applied as insofar best understood in the claims.
Conclusion
For claims 14-21, because the scope of these claims cannot be determined due to the indefinite problems as discussed above, no prior art rejections can be applied against these claims at this time; and the allowability also cannot be indicated at this time.
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan, can be reached at (571) 272-1988. The fax number for this group is (571) 273-8300.
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/Long Nguyen/
Primary Examiner
Art Unit 2842