Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rzepiela (US 20070069759 A1), in view of Liu (US 9748352 B2).
Regarding independent claim 1, Rzepiela teaches a test structure (Fig. 1, 14, 34; [0145], "Test pad 34 includes a test structure that is configured such that one or more electrical properties of the test structure can be measured."), comprising: a scribe line area of a semiconductor substrate ([0165], "Each of the test pads may be formed in a test region of the wafer such as a scribe line on a patterned wafer."); an under-test region directly above the scribe line area of the semiconductor substrate (Fig. 3, 80; [0163], "As shown in FIG. 3, this test pad includes gate structure 80 configured such that one or more electrical properties of the gate structure can be measured.", (In the present application, the under-test region is described in this way: "The metal gate 220 may be formed by depositing a gate metal on top of the gate oxide layer 240 to form the under-test region 310.", (Current Application ,[0027]).); and a layer of dielectric material underneath the under-test region, insulating the under-test region from the semiconductor substrate (Fig. 3, 88; [0163], "...gate dielectric 88 formed on conductive layer 84…").
However, Rzepiela does not teach a first and a second conductive region directly adjacent to the under-test region.
However, in the same field of endeavor, Liu teaches a first and a second conductive region directly adjacent to the under-test region (Fig. 7B, 213a,b; (Col 7, Lines 11-13), "A source region 213a and a drain region 213b are then formed on either side of the gate stack.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the test structure of Rzepiela with the conductive regions of Liu so that "current flows through a semiconducting channel between a source and a drain", (Liu, Col. 1, Lines 20-21).
Claim(s) 2 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rzepiela (US 20070069759 A1), in view of Liu (US 9748352 B2) and Li (US 20210242334 A1).
Regarding dependent claim 2, Rzepiela, as previously modified by Liu, teaches the test structure of claim 1. However, as previously combined, they do not teach further comprising a first and a second fin of silicon material longitudinally separated by the layer of dielectric material, wherein the first and the second conductive region are a first and a second epitaxial region formed on top of the first and the second fin of silicon material and partially in contact with the layer of dielectric material.
However, in the same field of endeavor, Li teaches further comprising a first and a second fin of silicon material longitudinally separated by the layer of dielectric material (Fig. 1E, 110A,B, 114; [0027], "...while an upper portion of the fin structures 110A and 110B protrudes from the isolation structure 114."), and Liu further teaches wherein the first and the second conductive region are a first and a second epitaxial region formed on top of the first and the second fin of silicon material and partially in contact with the layer of dielectric material (Fig. 7B, 213a,b, 215; (Col 7, Lines 13-16), " In one embodiment, the source and drain formation includes epitaxial growth of a semiconductor film during which dopants are introduced and incorporated into the film while it is being deposited.", (Col 7, Lines 20-22), "Next, an inter-layer dielectric (ILD) 215 such as SiO.sub.2 is deposited on top of each of the source and drain regions 213a and 213b, respectively.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the test structure as described by the combination of Rzepiela and Liu with the fins of Li for "reducing the short channel effect and providing a higher current flow", (Li, [0003]) and the epitaxial regions of Liu so that "dopants are introduced and incorporated into the film while it is being deposited", (Liu, Col. 7, Lines 15-16).
Regarding independent claim 12, Rzepiela teaches a test structure (Fig. 1, 14, 34; [0145], "Test pad 34 includes a test structure that is configured such that one or more electrical properties of the test structure can be measured."), comprising: a scribe line area of a semiconductor substrate ([0165], "Each of the test pads may be formed in a test region of the wafer such as a scribe line on a patterned wafer."); and an under-test region on top of the insulating region in the scribe line area and between the first epitaxial region and the second epitaxial region (Fig. 3, 80; [0163], "As shown in FIG. 3, this test pad includes gate structure 80 configured such that one or more electrical properties of the gate structure can be measured.", (In the present application, the under-test region is described in this way: "The metal gate 220 may be formed by depositing a gate metal on top of the gate oxide layer 240 to form the under-test region 310.", (Current Application ,[0027]).).
However, Rzepiela does not teach a first fin and a second fin in the scribe line area, and an insulating region between the first fin and the second fin; and a first epitaxial region directly on top of the first fin and a second epitaxial region directly on top of the second fin.
However, in the same field of endeavor, Li teaches a first fin and a second fin in the scribe line area (Fig. 1E, 110A,B, 114; [0027], "...while an upper portion of the fin structures 110A and 110B protrudes from the isolation structure 114."), and an insulating region between the first fin and the second fin (Fig. 1C, 110A,B, 112; [0023], "After the fin structures 110A and 110B are formed, an insulating layer 112 is formed to cover the fin structures 110A and 110B…"); and Liu teaches a first epitaxial region directly on top of the first fin and a second epitaxial region directly on top of the second fin (Fig. 7B, 213a,b; (Col 7, Lines 13-16), " In one embodiment, the source and drain formation includes epitaxial growth of a semiconductor film during which dopants are introduced and incorporated into the film while it is being deposited.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the test structure of Rzepiela with the fins of Li for "reducing the short channel effect and providing a higher current flow", (Li, [0003]) and the epitaxial regions of Liu so that "dopants are introduced and incorporated into the film while it is being deposited", (Liu, Col. 7, Lines 15-16).
Claim(s) 3-5, 13, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rzepiela (US 20070069759 A1), in view of Liu (US 9748352 B2), Li (US 20210242334 A1), and Cheng (US 10115629 B2).
Regarding dependent claim 3, Rzepiela, as previously modified by Liu and Li, teaches the test structure of claim 2, and further teaches wherein the under-test region includes a gate and a first and a second sidewall spacer formed at a first and a second sidewall of the gate (Fig. 3, 80, 88, 90; [0163], "...polysilicon gate electrode 90 formed on gate dielectric 88, and insulating side walls or "spacers" 82 formed on both lateral sides of polysilicon gate electrode 90.").
However, as previously combined, they do not teach the first epitaxial region being in contact with the first sidewall spacer and the second epitaxial region being in contact with the second sidewall spacer.
However, in the same field of endeavor, Cheng teaches the first epitaxial region being in contact with the first sidewall spacer and the second epitaxial region being in contact with the second sidewall spacer (Fig. 13, 225, 234; (Col. 14, Lines 61-63), "The lower sidewall spacers 234 electrically insulate the metal gate structures 230-1, 230-2, 230-3 from the adjacent source/drain regions 225.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the test structure as described by the combination of Rzepiela, Liu, and Li with the spacers in contact with the epitaxial regions of Cheng so that "the metal gate structures are electrically insulated", (Cheng, Col. 14, Lines 55-56).
Regarding dependent claim 4, Rzepiela, as previously modified by Liu, Li, and Cheng, teaches the test structure of claim 3. However, as previously combined, they do not teach wherein the first and the second fin are substantially aligned to each other longitudinally and formed in a direction orthogonal to the gate.
However, Li further teaches wherein the first and the second fin are substantially aligned to each other longitudinally and formed in a direction orthogonal to the gate (Fig. 1K, 110A,C, 130; [0035], "After the isolation structure 114 is formed, dummy gate structures 130 are formed across the fin structures 110A and 110C…").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the test structure as described by the combination of Rzepiela, Liu, Li, and Cheng with the alignment of the fins of Li for "higher device density, higher performance, and lower costs", (Li, [0003]).
Regarding dependent claim 5, Rzepiela, as previously modified by Liu, Li, and Cheng, teaches the test structure of claim 4, and further teaches wherein a leakage current, a breakdown voltage, or a breakdown time of the first sidewall spacer is measured by applying a voltage between the first conductive region and the gate ([0313], "In a further embodiment, the one or more electrical properties can be measured by depositing a charge on a polysilicon test area of the polysilicon finger pattern. In one such embodiment, the one or more electrical properties include leakage current...").
Regarding dependent claim 13, Rzepiela, as previously modified by Li and Liu, teaches the test structure of claim 12, and further teaches wherein the under-test region includes a gate and a first and a second sidewall spacer formed at a first and a second sidewall of the gate (Fig. 3, 80, 88, 90; [0163], "...polysilicon gate electrode 90 formed on gate dielectric 88, and insulating side walls or "spacers" 82 formed on both lateral sides of polysilicon gate electrode 90.").
However, as previously combined, they do not teach the first epitaxial region being in contact with the first sidewall spacer and the second epitaxial region being in contact with the second sidewall spacer.
However, in the same field of endeavor, Cheng teaches the first epitaxial region being in contact with the first sidewall spacer and the second epitaxial region being in contact with the second sidewall spacer (Fig. 13, 225, 234; (Col. 14, Lines 61-63), "The lower sidewall spacers 234 electrically insulate the metal gate structures 230-1, 230-2, 230-3 from the adjacent source/drain regions 225.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the test structure as described by the combination of Rzepiela, Li, and Liu with the spacers in contact with the epitaxial regions of Cheng so that "the metal gate structures are electrically insulated", (Cheng, Col. 14, Lines 55-56).
Regarding dependent claim 14, Rzepiela, as previously modified by Li, Liu, and Cheng, teaches the test structure of claim 13. However, as previously combined, they do not teach wherein the first fin and the second fin are substantially aligned to each other and are formed in a direction orthogonal to the gate.
However, Li further teaches wherein the first fin and the second fin are substantially aligned to each other and are formed in a direction orthogonal to the gate (Fig. 1K, 110A,C, 130; [0035], "After the isolation structure 114 is formed, dummy gate structures 130 are formed across the fin structures 110A and 110C…").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the test structure as described by the combination of Rzepiela, Li, Liu, and Cheng with the fin alignment of Li for "higher device density, higher performance, and lower costs", (Li, [0003]).
Claim(s) 6 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rzepiela (US 20070069759 A1), in view of Liu (US 9748352 B2), Li (US 20210242334 A1), Cheng (US 10115629 B2), and Jen (US 20220059556 A1).
Regarding dependent claim 6, Rzepiela, as previously modified by Liu, Li, and Cheng, teaches the test structure of claim 3. However, as previously combined, they do not teach further comprising a gate oxide layer between the first sidewall spacer and the gate and between the second sidewall spacer and the gate.
However, in the same field of endeavor, Jen teaches further comprising a gate oxide layer between the first sidewall spacer and the gate and between the second sidewall spacer and the gate (Fig. 15, 116, 122, 120; [0046], "...and a continuous second gate oxide layer 116L. Next, in step 412, a continuous control gate layer 120L may be deposited...may be deposited and patterned to form sidewall spacers 122…").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the test structure as described by the combination of Rzepiela, Liu, Li, and Cheng with the gate oxide layer of Jen for "reducing or eliminating photolithographic damage", (Jen, [0024]).
Regarding dependent claim 15, Rzepiela, as previously modified by Li, Liu, and Cheng, teaches the test structure of claim 14. However, as previously combined, they do not teach further comprising a gate oxide layer between the first sidewall spacer and the gate and between the second sidewall spacer and the gate.
However, in the same field of endeavor, Jen teaches further comprising a gate oxide layer between the first sidewall spacer and the gate and between the second sidewall spacer and the gate (Fig. 15, 116, 122, 120; [0046], "...and a continuous second gate oxide layer 116L. Next, in step 412, a continuous control gate layer 120L may be deposited...may be deposited and patterned to form sidewall spacers 122…").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the test structure as described by the combination of Rzepiela, Li, Liu, and Cheng with the gate oxide layer of Jen for "reducing or eliminating photolithographic damage", (Jen, [0024]).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rzepiela (US 20070069759 A1), in view of Liu (US 9748352 B2) and Zhang (US 20190189520 A1).
Regarding dependent claim 7, Rzepiela, as previously modified by Liu, teaches the test structure of claim 1. However, as previously combined, they do not teach further comprising a first and a second metal contact, the first and the second metal contact being in contact, respectively, with the first and the second conductive region.
However, in the same field of endeavor, Zhang teaches further comprising a first and a second metal contact, the first and the second metal contact being in contact, respectively, with the first and the second conductive region (Fig. 24, 2202, 2206, 302; [0073], "As shown in FIG. 22, contacts 2202, 2204 and 2206 are then formed in the ILD 2102...In this particular example, contact 2202 is formed to the bottom source and drains 302…").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the test structure as described by the combination of Rzepiela and Liu with the metal contacts of Zhang so as to "be used during contact resistance measurements", (Zhang, [0078]).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rzepiela (US 20070069759 A1), in view of Liu (US 9748352 B2), Li (US 20210242334 A1), and Zhang (US 20190189520 A1).
Regarding dependent claim 16, Rzepiela, as previously modified by Li and Liu, teaches the test structure of claim 12. However, as previously combined, they do not teach further comprising a first and a second metal contact, the first and the second metal contact being in contact with the first and the second epitaxial region respectively.
However, in the same field of endeavor, Zhang teaches further comprising a first and a second metal contact, the first and the second metal contact being in contact with the first and the second epitaxial region respectively (Fig. 24, 2202, 2206, 302; [0073], "As shown in FIG. 22, contacts 2202, 2204 and 2206 are then formed in the ILD 2102...In this particular example, contact 2202 is formed to the bottom source and drains 302…").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the test structure as described by the combination of Rzepiela, Li, and Liu with the metal contacts of Zhang so as to "be used during contact resistance measurements", (Zhang, [0078]).
Claim(s) 8-11 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rzepiela (US 20070069759 A1), in view of Liu (US 9748352 B2) and Xie (US 20230095140 A1).
Regarding dependent claim 8, Rzepiela, as previously modified by Liu, teaches the test structure of claim 1. However, as previously combined, they do not teach wherein the under-test region is a plurality of dielectric bridges between a first set of nanosheets and a second set of nanosheets.
However, in the same field of endeavor, Xie teaches wherein the under-test region is a plurality of dielectric bridges between a first set of nanosheets and a second set of nanosheets (Fig. 10C, 24S, 16; [0096], "Each dielectric bridge structure 24S is thinner than the suspended semiconductor channel material nanosheets 16 of the first and second vertical nanosheet stacks, VNS1 and VNS2.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the test structure as described by the combination of Rzepiela and Liu with the dielectric bridges of Xie so as to "connect each of the suspended semiconductor channel material nanosheets to a respective sidewall of the dielectric pillar", (Xie, [0004]).
Regarding dependent claim 9, Rzepiela, as previously modified by Liu and Xie, teaches the test structure of claim 8. However, as previously combined, they do not teach wherein the first conductive region is in conductive contact with the plurality of dielectric bridges of the under-test region through the first set of nanosheets, and the second conductive region is in conductive contact with the plurality of dielectric bridges of the under-test region through the second set of nanosheets.
However, Liu further teaches wherein the first conductive region is in conductive contact with the plurality of dielectric bridges of the under-test region through the first set of nanosheets, and the second conductive region is in conductive contact with the plurality of dielectric bridges of the under-test region through the second set of nanosheets (Fig. 7B, 213a,b, 211; (Col. 7, Lines 39-41), "The fins 221 include the active layer 187 and the top layer of silicon 190, separated by layers of the dielectric fill material 211.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the test structure as described by the combination of Rzepiela, Liu, and Xie with the conductive contact of Liu so as to "protect the source and drain regions, respectively, from being eroded", (Liu, Col. 8, Lines 27-29).
Regarding dependent claim 10, Rzepiela, as previously modified by Liu and Xie, teaches the test structure of claim 9. Xie further teaches wherein the plurality of dielectric bridges includes a first dielectric material ([0070], "In some embodiments, the dielectric spacer material that provides dielectric spacer 24 can be composed of silicon oxide.").
However, as previously combined, they do not teach and the first set of nanosheets are separated by the first dielectric material.
However, Liu further teaches and the first set of nanosheets are separated by the first dielectric material (Fig. 9B, 236, 211; (Col. 7, Lines 60-63), "FIGS. 9A-9C illustrate the process step 180 in which a matrix of silicon channels is formed according to one embodiment. The channels can be referred to as silicon nanowires.", (Col. 8, Lines 14-16), "The channel matrix includes an upper array of conducting channels 235 and a lower array of conducting channels 237...").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the test structure as described by the combination of Rzepiela, Liu, and Xie with the separation with the first dielectric material of Liu so as to "couple the charge reservoirs that make up the source region and the drain region", (Liu, Col. 8, Lines 16-17).
Regarding dependent claim 11, Rzepiela, as previously modified by Liu and Xie, teaches the test structure of claim 10. However, as previously combined, they do not teach wherein the plurality of dielectric bridges is at least partially covered by a second dielectric material, the second dielectric material being different from the first dielectric material.
However, Xie further teaches wherein the plurality of dielectric bridges is at least partially covered by a second dielectric material (Fig. 11C, 46; [0099], "The functional gate structure 46 includes forming a continuous layer of gate dielectric material and a gate electrode material inside and outside the gate cavity 44."), the second dielectric material being different from the first dielectric material ([0099], "Illustrative examples of high-k gate dielectric materials include metal oxides such as, for example, hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO4), zirconium silicon oxynitride (ZrSiOxNy), tantalum oxide (TaOx), titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Yb2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc,Ta)O3), and/or lead zinc niobite (Pb(Zn,Nb)O).").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the test structure as described by the combination of Rzepiela, Liu, and Xie with the second dielectric material of Xie so as to have "a dielectric constant greater than silicon oxide", (Xie, [0099]).
Regarding independent claim 17, Rzepiela teaches a test structure (Fig. 1, 14, 34; [0145], "Test pad 34 includes a test structure that is configured such that one or more electrical properties of the test structure can be measured."), comprising: a scribe line area of a semiconductor substrate ([0165], "Each of the test pads may be formed in a test region of the wafer such as a scribe line on a patterned wafer."); and an under-test region above the scribe line area (Fig. 3, 80; [0163], "As shown in FIG. 3, this test pad includes gate structure 80 configured such that one or more electrical properties of the gate structure can be measured.", (In the present application, the under-test region is described in this way: "The metal gate 220 may be formed by depositing a gate metal on top of the gate oxide layer 240 to form the under-test region 310.", (Current Application ,[0027]).).
However, Rzepiela does not teach the under-test region including a plurality of dielectric bridges between a first set of nanosheets and a second set of nanosheets; a first conductive region, the first set of nanosheets being between the first conductive region and the under-test region; and a second conductive region, the second set of nanosheets being between the second conductive region and the under-test region.
However, in the same field of endeavor, Xie teaches the under-test region including a plurality of dielectric bridges between a first set of nanosheets and a second set of nanosheets (Fig. 10C, 24S, 16; [0096], "Each dielectric bridge structure 24S is thinner than the suspended semiconductor channel material nanosheets 16 of the first and second vertical nanosheet stacks, VNS1 and VNS2."); the first set of nanosheets being between the first conductive region and the under-test region (Fig. 10C, VNS1, (This is in the space where the first conductive region is in Liu)); the second set of nanosheets being between the second conductive region and the under-test region (Fig. 10C, VNS2, (This is in the space where the second conductive region is in Liu)), and Liu teaches a first conductive region (Fig. 7B, 213a,b; (Col 7, Lines 11-13), "A source region 213a and a drain region 213b are then formed on either side of the gate stack."), and a second conductive region (Fig. 7B, 213a,b; (Col 7, Lines 11-13), "A source region 213a and a drain region 213b are then formed on either side of the gate stack.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the test structure of Rzepiela with the dielectric bridges of Xie so as to "connect each of the suspended semiconductor channel material nanosheets to a respective sidewall of the dielectric pillar", (Xie, [0004]), and the conductive regions of Liu so that "current flows through a semiconducting channel between a source and a drain", (Liu, Col. 1, Lines 20-21).
Regarding dependent claim 18, Rzepiela, as previously modified by Xie and Liu, teaches the test structure of claim 17. However, as previously combined, they do not teach wherein the first conductive region is in conductive contact with the plurality of dielectric bridges of the under-test region through the first set of nanosheets, and the second conductive region is in conductive contact with the plurality of dielectric bridges of the under-test region through the second set of nanosheets.
However, Liu further teaches wherein the first conductive region is in conductive contact with the plurality of dielectric bridges of the under-test region through the first set of nanosheets, and the second conductive region is in conductive contact with the plurality of dielectric bridges of the under-test region through the second set of nanosheets (Fig. 7B, 213a,b, 211; (Col. 7, Lines 39-41), "The fins 221 include the active layer 187 and the top layer of silicon 190, separated by layers of the dielectric fill material 211.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the test structure as described by the combination of Rzepiela, Xie, and Liu with the conductive contact of Liu so as to "protect the source and drain regions, respectively, from being eroded", (Liu, Col. 8, Lines 27-29).
Regarding dependent claim 19, Rzepiela, as previously modified by Xie and Liu, teaches the test structure of claim 18. Xie further teaches wherein the plurality of dielectric bridges is made of a first dielectric material ([0070], "In some embodiments, the dielectric spacer material that provides dielectric spacer 24 can be composed of silicon oxide.").
However, as previously combined, they do not teach and the first and the second set of nanosheets are separated by the first dielectric material.
However, Liu further teaches and the first and the second set of nanosheets are separated by the first dielectric material (Fig. 7B, 213a,b; (Col 7, Lines 13-16), " In one embodiment, the source and drain formation includes epitaxial growth of a semiconductor film during which dopants are introduced and incorporated into the film while it is being deposited.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the test structure as described by the combination of Rzepiela, Xie, and Liu with the separation with the first dielectric material of Liu so as to "couple the charge reservoirs that make up the source region and the drain region", (Liu, Col. 8, Lines 16-17).
Regarding dependent claim 20, Rzepiela, as previously modified by Xie and Liu, teaches the test structure of claim 19. However, as previously combined, they do not teach wherein the plurality of dielectric bridges is covered by a second dielectric material at a top thereof, the second dielectric material being different from the first dielectric material.
However, Xie further teaches wherein the plurality of dielectric bridges is covered by a second dielectric material at a top thereof (Fig. 11C, 46; [0099], "The functional gate structure 46 includes forming a continuous layer of gate dielectric material and a gate electrode material inside and outside the gate cavity 44."), the second dielectric material being different from the first dielectric material ([0099], "Illustrative examples of high-k gate dielectric materials include metal oxides such as, for example, hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO4), zirconium silicon oxynitride (ZrSiOxNy), tantalum oxide (TaOx), titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Yb2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc,Ta)O3), and/or lead zinc niobite (Pb(Zn,Nb)O).").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the test structure as described by the combination of Rzepiela, Xie, and Liu with the second dielectric material of Xie so as to have "a dielectric constant greater than silicon oxide", (Xie, [0099]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20220051955 A1,.
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/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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