DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to amendment filed on 02/11/2026. Claims 1-16 were canceled before. Claims 17-36 have been examined and are pending in this application.
Response to Arguments
Applicant’s arguments with respect to claims 17-36 have been considered but are moot in view of the current rejection.
A new reference Best US 2009/0049324 is cited in this Office Action necessitated by the amendment.
The disclosed invention repeatedly uses the term “host controller” and even describes the host controller as “processor 130, e.g., a controller external to the memory device 100, may be a memory controller or other external host device.” Paragraph [0021] of the instant filed specification. Therefore, the claim limitation “from a host external to the memory device” is taught by the memory controller of Kim.
In view of the new reference and the foregoing remark, independent claims 17, 26, and 33 are not in a condition for allowance. Claims depending therefrom, either directly or indirectly, are also not in a condition for allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17, 22-23, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. US 2009/0154256 (“Kim”) in view of Best US 2009/0049324 (“Best”).
As per independent claim 17, Kim teaches A memory device (“a memory system may include an integrated circuit (IC) memory device 103 and a memory controller 101” para 0044 and FIG. 1), comprising:
a number of memory cells (“memory cell array 105” para 0044 and FIG. 1);
a number of input/output (I/O) nodes (“data input/output transmission lines DQ-1 to DQ-n,” para 0044 and FIG. 1) to receive, from a host external to the memory device (“a memory controller 101” para 0044 and FIG. 1), input data comprising a predefined data pattern and for programming one or more memory cells of the number of memory cells (“During a data training operation, a plurality of data training write operations are performed using known data transmitted from the memory controller in parallel over the parallel data input/output transmission lines” para 0004) each I/O node of the number of I/O nodes for receiving an associated data (DQ) signal of a number of DQ signals including the input data (“a first set of delays may be desirable for delay circuits D-1 to D-n when a number of 0's is greater than a number of 1's being transmitted in parallel over transmission lines DQ-1 to DQ-n during a write operation, and a second set of delays (different than the first set of delays) may be desirable for delay circuits D-1 to D-n when a number of 0's is less than a number of 1's being transmitted in parallel over transmission lines DQ-1 to DQ-n during a write operation.” Para 0066);
logic coupled between the number of I/O nodes and the number of memory cells (“delay controller 111 may be coupled to each of the variable delay circuits D-1 to D-n,” para 0058 and FIG. 1) and to perform write training (“The memory controller 101 may thus be configured to provide write data training so that data communication between the memory controller 101 and the IC memory device 103 is selectively delayed across the different transmission lines DQ-1 to DQ-n during read and/or write operations.” Para 0053 and FIG. 1) including:
analyze eye openings for the received input data (“FIGS. 6A and 6B are graphical eye diagrams illustrating simulations of even and odd data reception at the IC memory device 103 when different delays are provided by at least some [of] the delay circuits D-1 to D-n (where n=8) so that parallel data from memory controller 101 is received over parallel transmission lines DQ-1 to DQ-n at different times.” Para 0055);
adjust setup and hold time margins for each I/O node of the number of I/O nodes based on the analysis of the eye openings (“a jitter of about 18 ps (picoseconds) may result thereby increasing setup/hold margins relative to the scenario discussed above with respect to FIGS. 5A and 5B.” Para 0055 and FIGS. 6A-B).
Kim teaches all of the claim limitations from above, but does not explicitly disclose “to align each DQ signal of the number of DQ signals with every other DQ signal of the number of DQ signals”.
However, in an analogous art in the same field of endeavor, Best teaches to align each DQ signal of the number of DQ signals with every other DQ signal of the number of DQ signals (“In this method, a strobe signal (referred to as the DQS signal in DDR-SDRAM parlance) is edge-aligned to and accompanies a group of data signals (referred to as the DQ signals in DDR-SDRAM parlance) sent by the DRAM in a ‘read’ operation, and is center-aligned (also referred to as ‘quadrature aligned’, as DQS is offset from the data edge by a quarter of the clock cycle time) to and accompanies the DQ signals in a ‘write’ operation.” Para 0004).
Given the teaching of Best, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Kim with “to align each DQ signal of the number of DQ signals with every other DQ signal of the number of DQ signals”. The motivation would be that it may be advantageous to implement such devices with different types of memory buses, para 0005 of Best.
As per dependent claim 22, Kim in combination with Best discloses the device of claim 17. Kim teaches wherein the logic is further to sweep a delay value to adjust a signal edge for each I/O node as the input data is received (“the different delay circuits D-1 to D-n may be used to provide different delays of the internal clock signal iCK at different ones of the input buffers and at different ones of the output buffers.” Para 0056).
As per dependent claim 23, Kim in combination with Best discloses the device of claim 17. Kim teaches wherein the logic is further to individually set a delay for each I/O node to adjust the setup and hold time margins for each I/O node (“the memory controller 101 may perform write data training to selectively delay/advance transmission of individual bits relative to the external clock signal eCK during write operations.” Para 0052, FIG. 1).
As per dependent claim 25, Kim in combination with Best discloses the device of claim 17. Kim teaches wherein trim values for each I/O node are selected to align data received on each I/O node (“The memory controller may be configured to perform write data training to selectively delay data transmission to the input buffers so that reception of the data at the input buffers is aligned with the clock signals received at the different input/output buffers during write operations.” Para 0025).
Claims 18-21, 24, and 26-36 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Best and in further view of Chaudhuri et al. US 2011/0078370 (“Chaudhuri”).
As per dependent claim 18, Kim in combination with Best discloses the device of claim 17. Kim and Best may not explicitly disclose, but in an analogous art in the same field of endeavor, Chaudhuri teaches wherein the logic is further to: latch the input data; store the latched input data; and compare the stored latched input data to an expected data pattern to analyze the eye openings (“The received pattern is compared to the expected pattern to determine whether a write error has occurred.” para 0024).
Given the teaching of Chaudhuri, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Kim and Best with “wherein the logic is further to: latch the input data; store the latched input data; and compare the stored latched input data to an expected data pattern to analyze the eye openings”. The motivation would be that the techniques disclosed by the invention may provide significantly improved link initialization times, para 0013 of Chaudhuri.
As per dependent claim 19, Kim in combination with Best and Chaudhuri discloses the device of claim 18. Kim and Best may not explicitly disclose, but Chaudhuri teaches wherein the logic is further to generate the expected data pattern (“The received pattern is compared to the expected pattern to determine whether a write error has occurred.” para 0024).
The same motivation that was utilized for combining Kim and Chaudhuri as set forth in claim 18 is equally applicable to claim 19.
As per dependent claim 20, Kim in combination with Best and Chaudhuri discloses the device of claim 18. Kim, Best, and Chaudhuri do not explicitly teach “wherein the logic comprises an XOR circuit to compare the stored latched input data to the expected data pattern”.
However, Chaudhuri teaches “The received pattern is compared to the expected pattern to determine whether a write error has occurred.” para 0024.
Hence, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Chaudhuri with “wherein the logic comprises an XOR circuit to compare the stored latched input data to the expected data pattern”. The motivation would be that an XOR circuit is traditionally used to compare two binary numbers which allows the determination of equality or inequality of two binary numbers.
As per dependent claim 21, Kim in combination with Best and Chaudhuri discloses the device of claim 18. Kim and Best may not explicitly disclose, but Chaudhuri teaches wherein the logic is further to adjust a trim value for at least one I/O node of the number of I/O nodes based on the comparison (“the reference voltage is swept from a minimum value to a maximum value [the reference voltage is mapped to the trim value] and, for each value, the receive equalizer is optimized, 330, and the timing margin is measured, 340, using strobe sweeping in the memory controller..” Para 0028).
The same motivation that was utilized for combining Kim and Chaudhuri as set forth in claim 18 is equally applicable to claim 21.
As per dependent claim 24, Kim in combination with Best discloses the device of claim 17. Kim and Best may not explicitly disclose, but in an analogous art in the same field of endeavor, Chaudhuri teaches wherein the logic is further to adjust an edge of a data strobe signal used to latch the input data (“Write training may also include one … strobe alignment.” Para 0023).
Given the teaching of Chaudhuri, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Kim and Best with “wherein the logic is further to adjust an edge of a data strobe signal used to latch the input data”. The motivation would be that the techniques disclosed by the invention may provide significantly improved link initialization times, para 0013 of Chaudhuri.
As per independent claim 26, Kim in combination with Best discloses most of the claim limitations of this claim. Kim and Best do not explicitly teach “a data strobe signal (DQS) node to receive a DQS signal from a host external to the memory device” and “align, based on the analysis, the DQS signal with each data signal of the number of data signals”.
However, in an analogous art in the same field of endeavor, Chaudhuri teaches a data strobe signal (DQS) node to receive a DQS signal from a host external to the memory device (“the sweeping of the strobe signal, for either read training or write training, is performed by the memory controller.” Para 0035);
align, based on the analysis, the DQS signal with each data signal of the number of data signals (“the sweeping of the strobe signal, for either read training or write training, is performed by the memory controller. … If zero errors are recorded at a certain setting over a specified number of bytes, the strobe may be considered too far from the edge and the strobe may be moved forward before the default number of bytes are tested.” Para 0035).
Given the teaching of Chaudhuri, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Kim with “a data strobe signal (DQS) node to receive a DQS signal from a host external to the memory device” and “align, based on the analysis, the DQS signal with each data signal of the number of data signals”. The motivation would be that the techniques disclosed by the invention may provide significantly improved link initialization times, para 0013 of Chaudhuri.
As per dependent claim 27, this claim is rejected based on arguments provided above for similar rejected dependent claim 20.
As per dependent claim 28, Kim in combination with Best and Chaudhuri discloses the device of claim 27. Kim and Best may not explicitly disclose, but Chaudhuri teaches further comprising memory to store the expected data pattern (“The received pattern is compared to the expected pattern to determine whether a write error has occurred.” para 0024).
The same motivation that was utilized for combining Kim and Chaudhuri as set forth in claim 27 is equally applicable to claim 28.
As per dependent claims 29-32, these claims are respectively rejected based on arguments provided above for similar rejected dependent claims 21, 21, 18, and 22.
As per claims 33-34, these claims are respectively rejected based on arguments provided above for similar rejected claims 26 and 26.
As per dependent claim 35, Kim in combination with Best and Chaudhuri discloses the system of claim 33. Kim teaches wherein the circuitry is further to individually set a delay for each DQ node of the plurality of DQ nodes to adjust the setup and hold time margins for each DQ node (“the memory controller 101 may perform write data training to selectively delay/advance transmission of individual bits relative to the external clock signal eCK during write operations.” Para 0052, FIG. 1)..
As per dependent claim 36, Kim in combination with Best and Chaudhuri discloses the system of claim 33. Kim and Best may not explicitly disclose, but Chaudhuri teaches wherein the circuitry is further to adjust an edge of the DQS signal based on the measured DQS-DQ timing (“the sweeping of the strobe signal, for either read training or write training, is performed by the memory controller. … If zero errors are recorded at a certain setting over a specified number of bytes, the strobe may be considered too far from the edge and the strobe may be moved forward before the default number of bytes are tested.” Para 0035).
The same motivation that was utilized for combining Kim and Chaudhuri as set forth in claim 33 is equally applicable to claim 36.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132