Prosecution Insights
Last updated: October 02, 2026
Application No. 18/351,575

SUPERCONDUCTING DEVICE, METHOD OF MANUFACTURING SUPERCONDUCTING DEVICE, AND LAMINATED BODY

Non-Final OA §102§103
Filed
Jul 13, 2023
Priority
Mar 22, 2021 — continuation of PCTJP2021011752
Examiner
WARTALOWICZ, PAUL A
Art Unit
Tech Center
Assignee
Fujitsu Limited
OA Round
1 (Non-Final)
64%
Grant Probability
Moderate
1-2
OA Rounds
3m
Est. Remaining
83%
With Interview

Examiner Intelligence

Grants 64% of resolved cases
64%
Career Allowance Rate
549 granted / 853 resolved
+4.4% vs TC avg
Strong +19% interview lift
Without
With
+18.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
35 currently pending
Career history
873
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
51.1%
+11.1% vs TC avg
§102
15.8%
-24.2% vs TC avg
§112
24.8%
-15.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 853 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 2, 5, 9-13, 17, 19-20 is/are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Das (US 2017/0373044). Regarding claims 1 and 11, Das discloses a superconducting device and a method of making thereof (Fig. 16) comprising a substrate (interposer 1630); a through hole provided in the substrate (superconducting through silicon via (TSV) 1635, cf. paragraph [0148]); a through electrode that is an electrode provided in the through hole and that includes a first portion (cavity 1635, cf. paragraph [0439]) and a second portion provided between the first portion and an inner wall surface of the through hole (pad interconnects 1633 and 1634), in which the second portion is formed of a material that includes a first metal that exhibits superconductivity at a temperature equal to or lower than a predetermined temperature (the pad interconnects are made from superconducting TiN, cf. paragraphs [0451], [0452]); a junction electrode that is an electrode electrically coupled to the through electrode ("second section" of "interconnect structure" 1671, i.e. solder bump 1673), that has at least a part provided outside the through hole (the bump is outside the through hole), and that is formed of a material that includes a second metal that exhibits superconductivity at a temperature equal to or lower than a predetermined temperature (paragraph [0368] discloses superconducting solder bumps made of In, whereby we note that paragraph [0461] states that "cryogenic electronic package 1600 can additionally or alternatively include one or more of the semiconductor structures and/or interconnect structures described in figures above"); and a partition wall that is provided between the through electrode and the junction electrode and that is formed of a material that includes the first metal (interconnect pad 1631, whereby Figs. 11 and 12 show a TSV 1117, which is similar as Fig. 16, with interconnect pads 1111, 1113 made of the same material as the pad interconnects 1115, 1116), wherein a melting point of the first metal is higher than a melting point of the second metal (the first metal TiN has a melting point of 2930 °C, whereas the second metal In has a melting point of 157 °C). Regarding claim 2, 12, Das teaches that the top structures of the TSV are cap plated with TiN (meets the limitation of the first metal) (para. 0460). Additionally, the SFT is provided on the surface such that the top of the TSV would include wiring coupled to the superconductor qubit and the through electrode (see fig. 16, SFQ, TSV). Regarding claim 5 and 17, Das teaches that the second portion (1633 and 1634) and the partition wall (1631) surround the first portion (1635). Regarding claims 9-10, Das teaches that the first portion is a cavity (para. 0366, 0435, 0439) and that the junction electrode (1671) is at a different lateral position than the through electrode (1635). Regarding claim 13, Das teaches a layer of SiO2 lining the inner wall of the through hole (para. 0474). Additionally, it appears that the bottom inner layer surface is covered as the through “bottom surface” is interpreted as the bottom part of the inner surface of the through hole. Regarding claims 19 and 20, Das teaches that the superconductor device (SFQ) and another device (MCM2) are laminated (para. 0432) and the junction electrode is coupled to the another device (para. 0436). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Das (US 2017/0373044) in view of Ryan (US 2018/0131376). Das teaches a product as described in claim 1, but fails to teach a dummy wiring that is provided on a side of a surface of the substrate opposite to a surface of a side on which the wiring is provided and that is not coupled to the superconducting qubit element. Ryan, however, teaches a RQL superconducting device (abstract) wherein the use of dummy elements for the purpose of lowering the thermal induced stress in superconducting devices operating in cryogenic environments (para. 0030). Therefore, it would have been obvious to one of ordinary skill in the art to provide dummy elements in Das in order to lower the thermal induced stress in superconducting devices operating in cryogenic environments as taught by Ryan. Claim(s) 4, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Das (US 2017/0373044) in view of Rigetti (US 9836699). Das teaches a product and method as described above in claims 1 and 11, respectively but fails to teach a wiring that is electrically coupled to the superconducting qubit element and the through electrode and that is formed of a material that includes the first metal. Rigetti, however, teaches a superconductor device (figs. 13, 16) wherein the junction electrode is provided and a base film is provided between the junction electrode and insulating layer is provided in openings in the passivation layer that reach the partition walls and the solder bumps (junction electrode) is provided in the passivation layer (col. 38, lines 30-60). Therefore, it would have been obvious to one of ordinary skill in the art to provide a base film between the junction electrode and insulating layer in openings in the passivation layer that reach the partition walls and the solder bumps (junction electrode) is provided in the passivation layer in Das in order to provide a configuration known in the art as taught by Rigetti. Regarding claim 18, Rigetti teaches that the base film includes the first metal (col. 38, lines 40-55). Claim(s) 6-8, 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Das. Das teaches a product and method as described above in claims 1 and 11, but fails to teach the limitations of claims 6-8 and 14-16. However, it would have been obvious to provide the selections of materials for the first portion as Das is not particularly limited with regard to the material of the first portion or the substrate such that it would have been routine to form the first portion and the substrate of the same material (eg. Ti) absent a showing of unexpected results. Additionally, it would have been obvious to provide the first portion comprising the first or second metal as Das teaches that the first portion is a superconductor and is not limited to the specific material. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A WARTALOWICZ whose telephone number is (571)272-5957. The examiner can normally be reached Monday-Friday 9 am - 5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Keith Walker can be reached at 571-272-3458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PAUL A WARTALOWICZ/ Primary Examiner, Art Unit 1735
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Prosecution Timeline

Jul 13, 2023
Application Filed
Aug 11, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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CIRCUIT MANUFACTURING METHOD AND SUPERCONDUCTING CIRCUIT
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SUPERCONDUCTING QUANTUM INTERFERENCE DEVICES AND USES THEREOF
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
64%
Grant Probability
83%
With Interview (+18.8%)
3y 5m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 853 resolved cases by this examiner. Grant probability derived from career allowance rate.

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