Prosecution Insights
Last updated: May 29, 2026
Application No. 18/351,991

OPTIMIZATION OF DATA ACCESS AND COMMUNICATION IN MEMORY SYSTEMS

Final Rejection §DOUBLEPATENT§DP
Filed
Jul 13, 2023
Priority
Feb 12, 2018 — provisional 62/629,628 +2 more
Examiner
TIV, BACKHEAN
Art Unit
2459
Tech Center
2400 — Computer Networks
Assignee
Micron Technology, Inc.
OA Round
4 (Final)
75%
Grant Probability
Favorable
5-6
OA Rounds
1y 0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allowance Rate
676 granted / 897 resolved
+17.4% vs TC avg
Strong +20% interview lift
Without
With
+20.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 11m
Avg Prosecution
19 currently pending
Career history
912
Total Applications
across all art units

Statute-Specific Performance

§101
4.4%
-35.6% vs TC avg
§103
80.9%
+40.9% vs TC avg
§102
3.1%
-36.9% vs TC avg
§112
5.0%
-35.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 897 resolved cases

Office Action

§DOUBLEPATENT §DP
Detailed Action Claims 1-20 are pending in this application. This is a response to the Amendments/Remarks filed on 4/14/26. This is a Final Rejection. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 14-20 of U.S. Patent No. 10,880,401(US 16/183,234). Although the claims at issue are not identical, they are not patentably distinct from each other because ‘401 teaches the instant claims, only differs in statutory class, and/or well known and obvious to one ordinary skill in the art. Allowable Subject Matter Claims 1-20 are allowed over prior art. REASONS FOR ALLOWANCE The following is an examiner’s statement of reasons for allowance: the prior art singly or in combination does not teach the totality of the independent claims when read in light of the specification. The closest prior art of record is US 2014/0310470 issued to Rash et al.(Rash) Rash teaches, para.49….the processor 210 creates a first read request to read the data from the storage unit. At step 425, the cache updating module 230 determines whether new data required to serve predicted queries is available in the cache. Responsive to a determination that the new data is not available in the cache, the processor 210 creates a second read request to read the new data from the storage unit; para.50; At step 435, the processor 210 combines the first read request and the second read request. At step 440, processor 210 retrieves the data and the new data from the storage unit in response to the combined read request…., therefore teaches as per claims 1,9,17 receive, from a host system, first access requests; generate second access requests in accordance with the first access request; transmit the second access requests to the one or more memory components However these prior art does not teach nor would it be obvious to one ordinary skill in the art to combine to teach the totality of the claim and at least the underlined portions below receive, from a host system, first access requests; receive, from the host system, information identifying contexts of the first access requests; generate second access requests in accordance with the first access requests and the contexts; and transmit the second access requests to the one or more memory components in response to the first access requests. The applicant's reply makes evident the reason for allowance, satisfying the record as a whole as required by rule 37 CFR 1.104 (e). In this case, the substance of applicant's remarks filed on 12/3/25 in combination with other claimed features point out the reason that claims are patentable over the prior art of record. Thus, the reason for allowance is in all probability evident from the record (see MPEP 1302.14). Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Response to Arguments Applicant's arguments filed on 4/14/26 have been fully considered but they are not persuasive. The applicant argues in substance, that US 10,880,401 is distinct from the instant claims. In reply, US 10,880,401 teaches the instant claims and only differs in statutory class, and/or well known and obvious to one ordinary skill in the art. The applicant argues that 1, 9, and 14 of ‘401 doesn’t teach the instant claims. Firstly claims 1,9 was not used in the double patenting rejection, rather 14-20 of US 10,880,401 was cited, see chart below for a comparison. In further to transmit the second access request to the one or more memory component in response to the first access requests would have been obvious to one ordinary skill in the art given the teachings of 10,880,401. Instant claims US 10,880,401 1. A memory system, comprising: one or more memory components; and a processing device, operatively coupled with the one or more memory components, to at least: receive, from a host system, first access requests; receive, from the host system, information identifying contexts of the first access requests; generate second access requests in accordance with the first access requests and the contexts; and transmit the second access requests to the one or more memory components in response to the first access requests. 14. A memory system, comprising: one or more memory components; and a processing device, operatively coupled with the one or more memory components, to at least: receive, from a host system, first access requests; receive, from the host system, information identifying contexts of the first access requests; generate different tags to represent different contexts; generate second access requests in accordance with the first access request, the second access request including the different tags representing the contexts of the first access requests; and transmit the second access requests to the one or more memory components. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892. US 2017/0315735 issued to Leggettee et al., teaches a processing system of a dispersed storage network (DSN) selecting a first proper subset of dispersed storage and task (DST) execution units of the DSN. The method continues with the processing system batching access requests over a time period in accordance with the first proper subset of the DST execution units of the DSN to limit the access requests to the first proper subset of DST execution units of the DSN during the time period. US 10,270,855 issued to Palthepu et al., teaches a computer generating a first set of access requests regarding a first set of encoded data slices and storage units of a dispersed storage network. A first data segment is encoded into the first set of encoded data slices. The method continues with the computer generating a second set of access requests regarding a second set of encoded data slices and the storage units. A second data segment is encoded into the second set of encoded data slices. The method continues with the computer grouping the first set of access requests and the second set of access requests to produce a set of combined requests. The method continues with the computer sending the set of combined requests to the storage units. US 6,247,101 issued to Settles teaches reusable tags are assigned to read and write requests on a tagged access synchronous bus. This allows multiple reads to be queued and overlapped on the tagged access synchronous bus to maximize data transfer rates. Writes are buffered to similarly allow multiple writes to be over-lapped. All data transfers on the tagged access synchronous bus typically would default to a cache block amount of data, with critical word first and early termination capabilities provided to permit processor execution to proceed without waiting for an entire cache block to be loaded. The tagged access synchronous bus architecture thus allows the system to take full advantage of high speed memory devices such as SDRAMs, RDRAMs, etc. while decoupling the bus data transfers from processor execution for increased overall system performance. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BACKHEAN TIV whose telephone number is (571)272-5654. The examiner can normally be reached on Mon.-Thurs. 5:30-3:30. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TONIA DOLLINGER can be reached on (571) 272-4170. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BACKHEAN TIV/ Primary Examiner, Art Unit 2459
Read full office action

Prosecution Timeline

Show 3 earlier events
Sep 03, 2025
Final Rejection mailed — §DOUBLEPATENT, §DP
Oct 31, 2025
Response after Non-Final Action
Dec 03, 2025
Request for Continued Examination
Dec 15, 2025
Response after Non-Final Action
Dec 22, 2025
Response Filed
Jan 14, 2026
Non-Final Rejection mailed — §DOUBLEPATENT, §DP
Apr 14, 2026
Response Filed
Apr 29, 2026
Final Rejection mailed — §DOUBLEPATENT, §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
75%
Grant Probability
96%
With Interview (+20.3%)
3y 11m (~1y 0m remaining)
Median Time to Grant
High
PTA Risk
Based on 897 resolved cases by this examiner. Grant probability derived from career allowance rate.

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