DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II (claims 1-13) in the reply filed on 3-9-2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 and 12-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cui (US 11,069,410).
[claim 1] A semiconductor structure (fig. 24A,24B), comprising: vertically-alternating stacks of insulating strips (32, fig. 24A), and electrically conductive strips (46, fig. 24A) laterally spaced apart from each other by line trenches (filled in by 55, 162, and/or 460-463, fig. 24B, 24A); laterally-alternating sequences of semiconductor channels (460, fig. 24B, 24A) and source/drain pillar structures (461, 463, fig. 24B, 24A) located within a respective one of the line trenches; and memory films (450L, fig. 24B, 24A) located between each neighboring pair of the vertically-alternating stacks and the laterally-alternating sequences, wherein each of a plurality of the source/drain pillar structures is in direct contact with a respective pair of vertical semiconductor channels (fig. 24B).
[claim 2] The semiconductor structure of Claim 1, wherein each of the semiconductor channels vertically extends from a first horizontal plane including bottommost surfaces of the vertically-alternating stacks to a second horizontal plane including topmost surfaces of the vertically-alternating stacks (fig. 24A).
[claim 3] The semiconductor structure of Claim 2, wherein the source/drain pillar structures vertically extend from the first horizontal plane to the second horizontal plane (fig. 24A).
[claim 4] The semiconductor structure of Claim 3, wherein interfaces between the semiconductor channels and the source/drain pillar structures are located within a respective planar vertical plane that is perpendicular to the first horizontal plane (fig. 24A).
[claim 5] The semiconductor structure of Claim 1, wherein the line trenches laterally extend along a second horizontal direction and have a respective uniform width along a first horizontal direction that is perpendicular to the second horizontal direction (fig. 24A,24B, two horizontal directions of 460 extend in a hd1 and hd2 direction).
[claim 6] The semiconductor structure of Claim 5, wherein each of the semiconductor channels comprises: a respective pair of first outer sidewalls that are parallel to the first horizontal direction; and a respective pair of second outer sidewalls that are parallel to the second horizontal direction (fig. 24A,24B, two horizontal directions of the sidewalls of 460 extend in a hd1 and hd2 direction).
[claim 7] The semiconductor structure of Claim 6, wherein: each of the first outer sidewalls contacts a respective one of the source/drain pillar structures (fig. 24B); and each of the second outer sidewalls contacts a respective one of the memory films (fig. 24B).
[claim 8] The semiconductor structure of Claim 1, wherein each of the semiconductor channels laterally surrounds a respective dielectric core (462, fig. 24B, 24A) having a top surface located within a horizontal plane including topmost surfaces of the semiconductor channels (fig. 24A).
[claim 12] The semiconductor structure of Claim 1, wherein: the semiconductor structure comprises a NOR memory device (semiconductor channels 460 are NOR channel structures, fig. 24A); and each of the memory films comprises a layer stack including, from one side to another, a tunneling dielectric layer (456, fig. 24A, see blowup), a charge storage layer (454, fig. 24A, see blowup), and a blocking dielectric layer (452, fig. 24A, see blowup).
[claim 13] The semiconductor structure of Claim 12, wherein each of the electrically conductive strips is laterally spaced from a respective most proximal one of the memory films by a respective backside blocking dielectric layer (52L, fig. 24A), and is laterally spaced from a respective overlying insulating strip (62, fig. 24A) and a respective underlying insulating strip (56L, fig. 24A) by the respective backside blocking dielectric layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cui (US 11,069,410) in view of Chia (US 2022/0020774).
Cui discloses the semiconductor structure of claim 1 but does not expressly disclose a first drain connection via structures below the drain pillar or a second source connection via structures above the source pillar.
Chia discloses a semiconductor structure (fig. 3) with a first drain connection via structures (BL, fig. 3) below the drain pillar (180, fig. 3, [0034]) or a second source connection via structures (194, SL, fig. 3) above the source pillar (170, fig. 3, [0034]).
It would have been obvious to one of ordinary skill in the art before the time of filing to have used Chia’s source and drain connection structures in Cui’s device in order to provide a means to interconnect the source and drain pillars to the rest of the device.
With this modification Cui discloses:
[claim 9] The semiconductor structure of Claim 1, further comprising: first source/drain connection via structures (BL, fig. 3, Chia) located below a first subset of the source/drain pillar structures (180, fig. 3, [0034], Chia), wherein each of the first source/drain connection via structures is in contact with a bottom horizontal surface of a respective one of the first subset of the source/drain pillar structures (fig. 3, Chia); and second source/drain connection via structures (194, fig. 3, Chia) located above a second subset of the source/drain pillar structures (170, fig. 3, [0034], Chia), wherein each of the second source/drain connection via structures is in contact with a top horizontal surface of a respective one of the second subset of the source/drain pillar structures (fig. 3, Chia).
[claim 10] The semiconductor structure of Claim 9, further comprising an array of semiconductor channel contact via structures (fig. 4 of Chia), wherein each of the semiconductor channel contact via structures is in contact with a respective one of the semiconductor channels (fig. 3,4 of Chia).
[claim 11] The semiconductor structure of Claim 9, further comprising: first bit lines (BL into the page, fig. 3, Chia) contacting a bottom surface of the first source/drain connection via structures and laterally extending along a first horizontal direction that is perpendicular to a lengthwise second direction horizontal direction of the line trenches (upon modification); and second bit lines (SL, fig. 3, Chia)contacting a top surface of the second source/drain connection via structures and laterally extending along the first horizontal direction that is perpendicular to the lengthwise second direction horizontal direction of the line trenches (fig. 3, Chia).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMAR MOVVA whose telephone number is (571)272-9009. The examiner can normally be reached Monday-Friday 9AM-5PM.
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/AMAR MOVVA/Primary Examiner, Art Unit 2898
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