DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Restriction by Original Presentation
Newly submitted claims 21-26 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
Restriction to one of the following inventions is required under 35 U.S.C. 121:
I. Claims 5-7, drawn to the line trenches laterally extending along a second horizontal direction and a uniform width along the first horizontal direction perpendicular to the second horizontal direction.
II. Claims 21-26, drawn to the vertically-alternating stacks of insulating strips and electrically conductive strips are laterally spaced apart from each other along a first horizontal direction and laterally extend along a second horizontal direction; the laterally-alternating sequences of semiconductor channels and source/drain pillar structures laterally alternate along the second horizontal direction.
The inventions are independent or distinct, each from the other because:
Inventions I and II are related as subcombinations disclosed as usable together in a single combination. The subcombinations are distinct if they do not overlap in scope and are not obvious variants, and if it is shown that at least one subcombination is separately usable. In the instant case, subcombination I has separate utility such as where the insulating/conductive strip stack and the semiconductor channels laterally aternate along the first horizontal direction instead of the second horizontal direction. See MPEP § 806.05(d).
Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply: the inventions require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries).
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 21-26 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 and 12-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cui (US 11,069,410).
[claim 1] A semiconductor structure (fig. 24A,24B), comprising: vertically-alternating stacks of insulating strips (32, fig. 24A), and electrically conductive strips (46, fig. 24A) laterally spaced apart from each other by line trenches (filled in by 55, 162, and/or 460-463, fig. 24B, 24A); laterally-alternating sequences of semiconductor channels (460 which comprises pairs of 460T and 460P which are pairs of channel tubes and channel plates, fig. 24B, 24A) and source/drain pillar structures (461, 463, fig. 24B, 24A) located within a respective one of the line trenches; and memory films (450L, fig. 24B, 24A) located between each neighboring pair of the vertically-alternating stacks and the laterally-alternating sequences, wherein each of a plurality of the source/drain pillar structures is in direct contact with a respective pair of the semiconductor channels (pairs of 460T and 460P, fig. 24B).
[claim 2] The semiconductor structure of Claim 1, wherein each of the semiconductor channels vertically extends from a first horizontal plane including bottommost surfaces of the vertically-alternating stacks to a second horizontal plane including topmost surfaces of the vertically-alternating stacks (fig. 24A).
[claim 3] The semiconductor structure of Claim 2, wherein the source/drain pillar structures vertically extend from the first horizontal plane to the second horizontal plane (fig. 24A).
[claim 4] The semiconductor structure of Claim 3, wherein interfaces between the semiconductor channels and the source/drain pillar structures are located within a respective planar vertical plane that is perpendicular to the first horizontal plane (fig. 24A).
[claim 5] The semiconductor structure of Claim 1, wherein the line trenches laterally extend along a second horizontal direction and have a respective uniform width along a first horizontal direction that is perpendicular to the second horizontal direction (fig. 24A,24B, two horizontal directions of 460 extend in a hd1 and hd2 direction).
[claim 6] The semiconductor structure of Claim 5, wherein each of the semiconductor channels comprises: a respective pair of first outer sidewalls that are parallel to the first horizontal direction; and a respective pair of second outer sidewalls that are parallel to the second horizontal direction (fig. 24A,24B, two horizontal directions of the sidewalls of 460 extend in a hd1 and hd2 direction).
[claim 7] The semiconductor structure of Claim 6, wherein: each of the first outer sidewalls contacts a respective one of the source/drain pillar structures (fig. 24B); and each of the second outer sidewalls contacts a respective one of the memory films (fig. 24B).
[claim 8] The semiconductor structure of Claim 1, wherein each of the semiconductor channels laterally surrounds a respective dielectric core (462, fig. 24B, 24A) having a top surface located within a horizontal plane including topmost surfaces of the semiconductor channels (fig. 24A).
[claim 12] The semiconductor structure of Claim 1, wherein: the semiconductor structure comprises a NOR memory device (semiconductor channels 460 are NOR channel structures, fig. 24A); and each of the memory films comprises a layer stack including, from one side to another, a tunneling dielectric layer (456, fig. 24A, see blowup), a charge storage layer (454, fig. 24A, see blowup), and a blocking dielectric layer (452, fig. 24A, see blowup).
[claim 13] The semiconductor structure of Claim 12, wherein each of the electrically conductive strips is laterally spaced from a respective most proximal one of the memory films by a respective backside blocking dielectric layer (52L, fig. 24A), and is laterally spaced from a respective overlying insulating strip (62, fig. 24A) and a respective underlying insulating strip (56L, fig. 24A) by the respective backside blocking dielectric layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cui (US 11,069,410) in view of Chia (US 2022/0020774).
Cui discloses the semiconductor structure of claim 1 but does not expressly disclose a first drain connection via structures below the drain pillar or a second source connection via structures above the source pillar.
Chia discloses a semiconductor structure (fig. 3) with a first drain connection via structures (BL, fig. 3) below the drain pillar (180, fig. 3, [0034]) or a second source connection via structures (194, SL, fig. 3) above the source pillar (170, fig. 3, [0034]).
It would have been obvious to one of ordinary skill in the art before the time of filing to have used Chia’s source and drain connection structures in Cui’s device in order to provide a means to interconnect the source and drain pillars to the rest of the device.
With this modification Cui discloses:
[claim 9] The semiconductor structure of Claim 1, further comprising: first source/drain connection via structures (BL, fig. 3, Chia) located below a first subset of the source/drain pillar structures (180, fig. 3, [0034], Chia), wherein each of the first source/drain connection via structures is in contact with a bottom horizontal surface of a respective one of the first subset of the source/drain pillar structures (fig. 3, Chia); and second source/drain connection via structures (194, fig. 3, Chia) located above a second subset of the source/drain pillar structures (170, fig. 3, [0034], Chia), wherein each of the second source/drain connection via structures is in contact with a top horizontal surface of a respective one of the second subset of the source/drain pillar structures (fig. 3, Chia).
[claim 10] The semiconductor structure of Claim 9, further comprising an array of semiconductor channel contact via structures (fig. 4 of Chia), wherein each of the semiconductor channel contact via structures is in contact with a respective one of the semiconductor channels (fig. 3,4 of Chia).
[claim 11] The semiconductor structure of Claim 9, further comprising: first bit lines (BL into the page, fig. 3, Chia) contacting a bottom surface of the first source/drain connection via structures and laterally extending along a first horizontal direction that is perpendicular to a lengthwise second direction horizontal direction of the line trenches (upon modification); and second bit lines (SL, fig. 3, Chia)contacting a top surface of the second source/drain connection via structures and laterally extending along the first horizontal direction that is perpendicular to the lengthwise second direction horizontal direction of the line trenches (fig. 3, Chia).
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any interpretation applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMAR MOVVA whose telephone number is (571)272-9009. The examiner can normally be reached Monday-Friday 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AMAR MOVVA/Primary Examiner, Art Unit 2898
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