DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 09/29/2025 have been fully considered but they are not persuasive.
Applicant’s arguments (Summary of pages 13-15, Examiner emphasis – Bold)
Argument 1:
…Applicant argues there is no error flag message used to convey an error event occurrence at the error detection module 121 to the error handling module 156 for error recovery. Instead, in Chae, the error handling module 156 has its own error detection mechanism to generate a complete frame without usage of an error flag message.
Response:
Examiner respectfully disagrees.
Furthermore, Chae, fig.6, [0031; 0036-0037] when an error detection module 121 detects an error, a software issues an error interrupt/flag to notify a host processor to handle the resulting error frame. For example, the host processor may mark the frame which may be saved into memory 130 as having a size error. When a continuous stream of image data frames is being received by image processing unit 155, error handling module 156 may check each incoming frame to ensure that the synchronization markers or signals transition properly for each normal frame input. Error handling module 156 may utilize an illegal line or frame transition detected based on the received frame synchronization markers as flags for reporting the error. A protocol signal violation may be another form of error that may be detected by the system. when one or more of the above frame sync signal protocol violations are detected, error handling module 156 generates an interrupt/flag and reports the detected violations (e.g., protocol violation or error). In [0063] fig. 6, For the line fetched at block 630, the line-level error handling module at block 640 detects whether the current received line of the current frame violates any of the frame sync signal protocols. At block 640, the error handler utilizes frame synchronization markers/flags that are active during beginning and end of each line to check whether the sync signals are missing or misaligned (e.g., HS-HS check, HE-HE check, and the like). If the line-level error handling module detects at block 640 any violation of the frame sync signal protocols (YES at block 640), the module flags the current frame for issuing an interrupt to the host processor indicating the protocol error for the current frame and line (block 642). Therefore, Chae discloses error flag message used to convey an error event occurrence at the error detection module 121 to the error handling module 156 for error recovery.
Argument 2: (Summary of page 15)
…Applicant argued that Chae's disclosure is in distinct contradiction to the amended recited pending claims where an aggregator is configured "to send an error flag message using a multiplexed data stream" and a processing unit is configured "to substitute an errored pixel with a dummy pixel upon receipt of the error flag message from the multiplexed data stream". The pending claims recite an error flag message to coordinate error detection and error recovery actions by the aggregator and the processing unit. This is in contrast to the independent error handling module disclosed by Chae which does not require an error flag message, and teaches away from the requirement of an error flag message to coordinate error detection and error recovery actions.
Response:
Examiner respectfully disagrees.
See detailed response to argument 1 and the updated rejection of independent claim 1.
In particular, Honguu, fig. 1, [0051] discloses a multiplexing circuit 11 as a channel encoder that encodes image data that has been inputted from a transmission changeover portion 10 of a video telephone 1, and serves as the transmitted data, encodes the audio data that has been inputted from the audio processing portion/audio storage portion 30, adds an error correction code/flag, multiplexes the data with data classification flags, control signals and synchronization signals, and outputs/sends the error correction code/flag via a multiplexed stream data to a modem 3, where the correction code is used to substitute an errored pixel, therefore, correcting the detected error and correcting the error using the correction code.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1- 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Stone et al. (US 2013/0312043 A1) in view of Luitje et al. (US 5,936,520), in view of Chae et al. (US 2021/0209390 A1), further in view of Honguu et al. (US 2002/0015091 A1).
Regarding claim 1, Stone discloses an apparatus (Fig. 5 – data acquiring/error detection system) for error recovery (fig. 5 - Error correction system), the apparatus comprising (Stone, fig. 5, [0051] discloses a data acquiring system used for capturing telemetry data from various data sources/devices. The system performs several functions including error correction):
a plurality of sensors (fig. 5, sensor array -122) configured to generate a plurality of sensor data (heterogeneous sensor data set) (Stone, fig. 5, [0041] sensor arrays 122 in a particular monitored venue 120 can include a wide variety of different sensors. The sensors generate a data set that can be a highly heterogeneous. The data set may be generated and provided by different sensing devices such as a metal detector, temperature sensor, video camera, etc. These heterogeneous sensor data sets may be converted into homogeneous sensor data sets with consistent formats and data structures, which can be more easily and quickly processed by downstream data processing modules);
an aggregator (edge device data aggregator 2202) coupled to a plurality of sensors (sensor array -122) (Stone, fig. 5, [0042-0043] discloses sensor array -122 coupled to an edge device data aggregator 2202 via a sensor protocol interface 2201);
the aggregator configured a) to multiplex the plurality of sensor data (data feeds from various sensor arrays 122) into a single (combined sensor data) aggregator output stream (Stone, fig. 2, [0043] an edge device data aggregator 2102 receives data feeds from the various sensor arrays 122, the edge device data aggregator 2102 can perform a variety of processing operations on the raw sensor data. The edge device data aggregator 2402 can simply marshal the raw sensor data and send the combined or “multiplexed” sensor data to the real time wireless data integrator 2103. The real time wireless data integrator 2103 can use wireless and wired data connections to transfer the sensor data to the analytic engine 260); and
b) to detect a transmission error in the plurality of sensor data (Stone [0023;0042], in real time, the aggregator acquires sensor data streams can be analyzed by parts of the aggregator which includes an analysis tools module 240, rule manager module 250 and analytic engine 260 to detect threats/illegal/error in the data that is being transmitted),
a processing unit coupled to the aggregator (Stone, fig. 6, [0052], components of data aggregator 2202, which include a video/audio adapters 2206, sensor inputs 2208, GPS input 2210, local sensor data processing 2212, local image processing 2214, data and code storage 2216, and a wireless transceiver 2218. One or more of these components of the edge device data aggregator 2202 can be implemented as software or firmware functional components executable by the processor 2204 connected to or included within the aggregator 2202).
Stone did not explicitly disclose a plurality of sensor interfaces, wherein each one of the plurality of sensor interfaces is coupled to each one of the plurality of sensors, c) to send an error flag message using a “multiplexed” data stream; wherein the aggregator uses an aggregator hardware without software involvement; the processing unit configured to recover the transmission error using a processor hardware without software involvement and to substitute an errored pixel with a dummy pixel upon receipt of the error flag message from the multiplexed data stream, wherein the dummy pixel enables an error recovery scheme for maintenance of a data packet dimension and wherein the maintenance avoids a hardware violation and avoids a reset.
Luitje discloses a plurality of sensor interfaces (fig. 1, digital smart sensor interfaces), wherein each one of the plurality of sensor interfaces is coupled to each one of the plurality of sensors (Luitje, fig. 1, col. 2, lines 53-62, discloses plurality of digital smart sensor interfaces. Each of the interfaces has an associated sensor. The interfaces are individually addressed and polled, and status data for associated sensor is obtained).
One of ordinary skill would have been motivated to combine the teachings of Stone and Luitje because these teachings are from the same field of endeavor with respect to the use of sensors for data collection and processing.
Therefore, before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to incorporate the strategies by Luitje into the method by Stone, thereby enabling the use of a single wire bus multiplex to monitor sensors and obviate the need for separate dedicated line to handle monitoring of the data output to each sensor, Luitje Col. 1, lines 54-63).
Stone modified by Luitje did not explicitly disclose c) to send an error flag message using a multiplexed data stream; wherein the aggregator uses an aggregator hardware without software involvement; the processing unit configured to recover the transmission error using a processor hardware without software involvement and to substitute an errored pixel with a dummy pixel upon receipt of the error flag message from the multiplexed data stream, wherein the dummy pixel enables an error recovery scheme for maintenance of a data packet dimension and wherein the maintenance avoids a hardware violation and avoids a reset.
Chae discloses c)…wherein the aggregator uses an aggregator hardware (fig. 1 – Control unit 105, [0023]) without software involvement (hardware-based solution); and
the processing unit configured to recover the transmission error using a processor hardware without software involvement (Chae, fig. 1, [0067] an image processing system (fig.1, 100/Control unit 105) with frame-level or line-level error detection and recovery operations provides a hardware-based solution to prevent deadlock conditions by maintaining full frame size and concealing frame errors. The solution provides frame- and line-level handling of frame errors and graceful error recovery in hardware), and
to substitute an errored pixel with a dummy pixel upon receipt of the error flag message (receiving an interrupt/error flag message and reports detecting violations) from the data stream (Chae, figs. 1-4, [0037; 0045, 0054] when one or more of the above frame sync signal protocol violations are detected, error handling module 156 generates an interrupt and reports/flags the detected violations (e.g., protocol violation or error). Frame-based (or frame-level) error handling and concealment in which once a size error is detected at any point in a given image frame by error handling module 156, the remainder of the erroneous frame is discarded and filled with dummy data),
wherein the dummy pixel enables an error recovery scheme for maintenance of a data packet dimension (repeat image data of the last known good pixel to complete the frame) (Chae, fig. 1, [0043-0045] when error handling module 156 detects an oversized input frame (e.g., long frame, line line) while processing the current input frame received from receiver 120 (e.g., first frame or line size greater than reference frame or line size, the error handling module 156 goes into error handling mode to perform oversized input frame handling (error concealment operation) by discarding all remaining incoming streams of the current oversized image frame and going into error frame quick completion mode by generating the remaining pixel/line data to complete the oversized frame as quickly as possible with dummy data. Since the frame is deemed an error frame, error handling module 156 may repeat image data of the last known good pixel to complete the frame according to its normal expected size (maintenance of a data packet dimension)); and
wherein the maintenance avoids a hardware violation and avoids a reset (Chae, [0045], The error concealment operation of error handling module 156, that enables image processing unit 155 to complete the current frame with the correct frame size, prevents any deadlock conditions in the control logic in the rest of image processing unit 155 or in other downstream modules of the image processing pipeline and enables seamless error recovery with minimal frame loss and without a hardware (sub-system) reset from a frame size error).
One of ordinary skill would have been motivated to combine the teachings of Stone, Luitje and Chae because these teachings are from the same field of endeavor with respect to error recovery in a received or transmitted image data.
Therefore, before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to incorporate the strategies by Chae into the method by Stone and Luitje, thereby enabling a hardware-based approach to image error correction, thus enhancing high performance, high reliability, and low-latency in the image processing system, Chae [0045].
Stone, Luitie and Chae did not explicitly disclose c) to send an error flag message using a multiplexed data stream.
Honguu discloses c) to send an error flag message using a multiplexed data stream (Honguu, fig. 1, [0051] discloses a multiplexing circuit 11 as a channel encoder that encodes image data that has been inputted from the transmission changeover portion 10 of a video telephone 1, and that serve as the transmitted data, encodes the audio data that has been inputted from the audio processing portion/audio storage portion 30, adds an error correction code or “error flag”, multiplexes the data with data classification flags, control signals and synchronization signals, and outputs/sends the error correction code or “error flag” via a multiplexed stream data to a modem 3).
One of ordinary skill would have been motivated to combine the teachings of Stone, Luitje, Chae and Honguu because these teachings are from the same field of endeavor with respect to error recovery in a received or transmitted image data.
Therefore, before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to incorporate the strategies by Honguu into the method by Stone, Luitje and Chae, thereby enabling efficient use of the function of a video telephone to store incoming calls, Honguu [Abstract].
Regarding claim 2, Stone, Luitje, Chae and Honguu disclose the apparatus of claim 1, further comprising a processing unit (analytic engine 260) configured to receive the single (combined sensor data) aggregator (aggregator 2102) output stream and to process the plurality of sensor data (Stone, fig. 2, [0043] an edge device data aggregator 2102 receives data feeds from the various sensor arrays 122, the edge device data aggregator 2102 can perform a variety of processing operations on the raw sensor data. The edge device data aggregator 2402 can simply marshal the raw sensor data and send the combined sensor data to the real time wireless data integrator 2103. The real time wireless data integrator 2103 can use wireless and wired data connections to transfer the sensor data to the analytic engine 260).
The motivation to combine is similar to that of claim 1.
Regarding claim 3, Stone, Luitje, Chae and Honguu disclose the apparatus (computer system 700) of claim 2, further comprising a processor memory (704) coupled to the processing unit (CPU) (stone, [0064-0065] discloses a computer system 700 which includes a data processor 702 (e.g., a central processing unit (CPU), as graphics processing unit (GPU), or both), a main memory 704 and a static memory 706, which communicate with each other via a bus 708).
The motivation to combine is similar to that of claim 1.
Regarding claim 4, Stone, Luitje, Chae and Honguu disclose the apparatus of claim 3, further comprising an aggregator memory (fig. 6, - 2216 coupled to the aggregator (fig. 6 - 2202) (Stone, fig. 6, [0052] discloses components of an edge device data aggregator 2202. The aggregator includes a processor 2204 and a data and code storage 2216).
The motivation to combine is similar to that of claim 1.
Regarding claim 5, Stone, Luitje, Chae and Honguu disclose the apparatus of claim 4, wherein the aggregator (multiplex system) comprises a plurality of input interfaces configured to receive the plurality of sensor data (Luitje, fig. 1, col. 2, lines 53-62, discloses plurality of digital smart sensor interfaces. Each of the interfaces has an associated sensor, including at least one with an analog type sensor. The interfaces are individually addressed and polled, and status data for associated sensor is obtained. Col. 4, lines 50-67, each sensor is connected the multiplex system through a multiplex bus).
The motivation to combine is similar to that of claim 1.
Regarding claim 6, Stone, Luitje, Chae and Honguu disclose the apparatus of claim 5, wherein the aggregator comprises a multiplexer configured to generate the single aggregator output stream (combined sensor data) (Stone, fig. 2, [0043] an edge device data aggregator 2102 receives data feeds from the various sensor arrays 122, the edge device data aggregator 2102 can perform a variety of processing operations on the raw sensor data. The edge device data aggregator 2402 multiplex sensor data by simply marshal the raw sensor data and send the combined sensor data to the real time wireless data integrator 2103. The real time wireless data integrator 2103 can use wireless and wired data connections to transfer the sensor data to the analytic engine 260).
The motivation to combine is similar to that of claim 1.
Regarding claim 7, Stone, Luitje, Chae and Honguu disclose the apparatus of claim 6, wherein the processor (the analytic engine 260) comprises a processor interface configured to receive the single aggregator output stream (Stone, fig. 2, [0043] an edge device data aggregator 2102 receives data feeds from the various sensor arrays 122, the edge device data aggregator 2102 can perform a variety of processing operations on the raw sensor data. The edge device data aggregator 2402 can simply marshal the raw sensor data and send the combined sensor data to the real time wireless data integrator 2103. The real time wireless data integrator 2103 can use single channel via either a wireless or wired data connections to transfer the sensor data to the analytic engine 260).
The motivation to combine is similar to that of claim 1.
Claim(s) 8 - 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Stone et al. (US 2013/0312043 A1) in view of Luitje et al. (US 5,936,520), in view of Chae et al. (US 2021/0209390 A1), in view of Honguu et al. (US 2002/0015091 A1), further in view of Chen et al. (CN 115963917 B).
Regarding claim 8, Stone, Luitje, Chae and Honguu disclose the apparatus of claim 7, but did not explicitly disclose wherein the processing unit comprises a plurality of processors wherein each of the plurality of processors is coupled to the processor interface.
Chen discloses wherein the processing unit comprises a plurality of processors (first auxiliary processor 550_1 - first auxiliary processor 550_k) wherein each of the plurality of processors is coupled to the processor interface (Chen, fig. 5, [0129-0132], discloses a plurality of first auxiliary processors 550 which includes a first auxiliary processor 550_1, a first auxiliary processor 550_2, ..., a first auxiliary processor 550_k, ..., a first auxiliary processor 550_K. K can be an integer greater than or equal to 1, k E (1, 2, ..., K-1, K. The plurality of first auxiliary processors 550 may be connected to a plurality of visual sensors 510 via second data lines. The main processor 520 may be connected to a plurality of first auxiliary processors 550 via a third data line 506. The plurality of first auxiliary processors 550 may be configured to process the plurality of original visual data in response to receiving the original visual data from the plurality of visual sensors 510 to obtain the plurality of visual data. The first auxiliary processor can be in one-to-one correspondence with the visual sensor).
One of ordinary skill would have been motivated to combine the teachings of Stone, Luitje, Chae, Honguu and Chen because these teachings are from the same field of endeavor with respect to the use of sensors to collect and process the data
Therefore, before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to incorporate the strategies by Chen into the method by Stone, Luitje, Chae and Honguu, thereby enable synchronous collection instruction in response to detecting the synchronous collection instruction to obtain the visual data corresponding to the plurality of visual sensors, wherein the visual angle ranges of the plurality of visual sensors are different from each other, Chen [Abstract].
Regarding claim 9, Stone, Luitje, Chae, Honguu and Chen disclose the apparatus of claim 8, wherein each of the plurality of processors is assigned a one-to- one correspondence with each of the plurality of sensor data (Chen, [0131-0132] the first auxiliary processor can be in one-to-one correspondence/assignment with the visual sensor. For example, the first auxiliary processor 550_1 can be connected with the visual sensor 510_1 through the second data line 505_1, the first auxiliary processor 550_2 can be connected with the visual sensor 510_2 through the second data line 505_2, ... The first auxiliary processor 550_k may be connected to the visual sensor 510_k through the second data line 505_k, ..., the first auxiliary processor 550_K may be connected to the visual sensor 510_K through the second data line 505_K).
The motivation to combine is similar to that of claim 8.
Regarding claim 10, Stone, Luitje, Chae, Honguu and Chen disclose the apparatus of claim 8, wherein each of the plurality of processors processes the one-to-one correspondence of each of the plurality of sensor data (Chen, fig. 5, [0129-0132], discloses a plurality of first auxiliary processors 550 which includes a first auxiliary processor 550_1, a first auxiliary processor 550_2, ..., a first auxiliary processor 550_k, ..., a first auxiliary processor 550_K. K can be an integer greater than or equal to 1, k E (1, 2, ..., K-1, K. The plurality of first auxiliary processors 550 may be connected to a plurality of visual sensors 510 via second data lines. The main processor 520 may be connected to a plurality of first auxiliary processors 550 via a third data line 506. The plurality of first auxiliary processors 550 may be configured to process the plurality of original visual data in response to receiving the original visual data from the plurality of visual sensors 510 to obtain the plurality of visual data. The first auxiliary processor can be in one-to-one correspondence with the visual sensor).
The motivation to combine is similar to that of claim 8.
Regarding claim 11, Stone, Luitje, Chae, Honguu and Chen disclose the apparatus of claim 10, wherein the plurality of sensor data has a one-to-one correspondence with each of the plurality of sensors (Luitje, fig. 1, col. 2, lines 53-62, discloses plurality of digital smart sensor interfaces. Each of the interfaces has an associated sensor (one-to-one correspondence). The interfaces are individually addressed and polled, and status data for associated sensor is obtained).
The motivation to combine is similar to that of claim 8.
Claim(s) 12 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gowda et al. (US 6,344,877 B1), in view of Chae et al. (US 2021/0209390 A1), further in view of Honguu et al. (US 2002/0015091 A1).
Regarding claim 12, Gowda discloses a method for error recovery, the method comprising (Gowda, Col. 3, lines 23-25, discloses techniques for using dummy pixel to correct error within main pixel cells):
detecting a packet data corruption event (i.e., nonlinearities in the transfer characteristic of a source) in a series of frames of data transmission from a plurality of sensors (Gowda, fig. 3, col. 3, lines 10 -20, discloses the use of dummy pixels to compensate for errors detected in pixels/frames captured and transmitted by plurality sensors. Col. 11, lines 62-64, the type of data that is captured by image sensors and transmitted may include still images and series of image frames from moving pictures).
determining if the packet data corruption event is an errored pixel or an errored line in the series of frames of data transmission from the plurality of sensors (Gowda, fig. 3, col. 3, lines 10 -20, when errors are identified by the pixels of the images that captured and transmitted by the image sensors, dummy pixels are used to compensate for the errors detected in pixels/frames captured and transmitted by plurality sensors. Col. 11, lines 62-64, the type of data that is captured by image sensors and transmitted may include still images and series of image frames from moving pictures);
substitute an errored pixel with a dummy pixel upon receipt of the error flag message on the multiplexed data stream (Gowda, fig. 3, col. 3, lines 10 -20, when errors are identified by the pixels of the images that captured and transmitted by the image sensors, dummy pixels are used to compensate for the errors detected in pixels/frames captured and transmitted by plurality sensors. Col. 11, lines 62-64, the type of data that is captured by image sensors and transmitted may include still images and series of image frames from moving pictures).
Gowda did not explicitly disclose wherein the dummy pixel enables an error recovery scheme for maintenance of a data packet dimension and wherein the maintenance avoids a hardware violation and avoids a reset; and where the error flag message is sent to notify a plurality of processors of a presence and a location of the dummy pixel or the dummy line in the series of frames of data transmission from the plurality of sensors.
Chae discloses wherein the dummy pixel enables an error recovery scheme for maintenance of a data packet dimension (repeat image data of the last known good pixel to complete the frame) (Chae, fig. 1, [0043-0044] when error handling module 156 detects an oversized input frame (e.g., long frame, line line) while processing the current input frame received from receiver 120 (e.g., first frame or line size greater than reference frame or line size, the error handling module 156 goes into error handling mode to perform oversized input frame handling (error concealment operation) by discarding all remaining incoming streams of the current oversized image frame and going into error frame quick completion mode by generating the remaining pixel/line data to complete the oversized frame as quickly as possible with dummy data. Since the frame is deemed an error frame, error handling module 156 may repeat image data of the last known good pixel to complete the frame according to its normal expected size (maintenance of a data packet dimension)); and
wherein the maintenance avoids a hardware violation and avoids a reset (Chae, [0045], The error concealment operation of error handling module 156, that enables image processing unit 155 to complete the current frame with the correct frame size, prevents any deadlock conditions in the control logic in the rest of image processing unit 155 or in other downstream modules of the image processing pipeline and enables seamless error recovery with minimal frame loss and without a hardware (sub-system) reset from a frame size error); and
wherein the error flag message (performing error information reporting to host processor) is sent to notify a plurality of processors of a presence and a location (error location information) of the dummy pixel or the dummy line in the series of frames of data transmission from the plurality of sensors (Chae figs. 1-4, [0054-0056] when an error is detected in a transmitted image, a line-based error handling module may perform error information reporting that provides additional information (e.g., error location information, frame confidence value or factor information, and the like) to the host processor along with the software interrupt to aid the processor in making a frame rejection decision. In frame-based (or frame-level) error handling and concealment, once a size error is detected at any point/location in a given image frame by error handling module 156, based on error location information provided to the processor, the remainder of the erroneous frame is discarded and filled with dummy data).
One of ordinary skill would have been motivated to combine the teachings of Gowda and Chae because these teachings are from the same field of endeavor with respect to error recovery in a received or transmitted image data.
Therefore, before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to incorporate the strategies by Chae into the method by Gowda, thereby enabling a hardware-based approach to image error correction, thus enhancing high performance, high reliability, and low-latency in the image processing system, Chae [0045].
Gowda and Chae did not explicitly disclose sending an error flag message on a multiplexed data stream to provide packet data corruption event notification.
Honguu discloses sending an error flag message on a multiplexed data stream to provide packet data corruption event notification (Honguu, fig. 1, [0051] discloses a multiplexing circuit 11 as a channel encoder that encodes image data that has been inputted from the transmission changeover portion 10 of a video telephone 1, and that serve as the transmitted data, encodes the audio data that has been inputted from the audio processing portion/audio storage portion 30, adds an error correction code/flag, multiplexes the data with data classification flags, control signals and synchronization signals, and outputs/sends the error correction code/flag via a multiplexed stream data to a modem 3).
One of ordinary skill would have been motivated to combine the teachings of Gowda, Chae and Honguu because these teachings are from the same field of endeavor with respect to error recovery in a received or transmitted image data.
Therefore, before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to incorporate the strategies by Honguu into the method by Gowda and Chae, thereby enabling efficient use of the function of a video telephone to store incoming calls, Honguu [Abstract].
Regarding claim 28, Gowda, Chae and Honguu disclose a non-transitory computer-readable medium storing computer executable code, operable on a device comprising at least one processor and at least one memory coupled to the at least one processor, wherein the at least one processor is configured to implement error recovery, the computer executable code (Chae, [0069] fig. 7 illustrates that memory 708 may be operatively coupled to processor 702. Memory 708 may be a non-transitory medium configured to store various types of data, the stored data when executed by the processor 702 perform a robust frame size error detection and recovery mechanism to minimize frame loss for camera input sub-systems) comprising:
The rest of the limitations are rejected with rational similar to that of claim 12.
Claim(s) 13 -16 and 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gowda et al. (US 6,344,877 B1), in view of Chae et al. (US 2021/0209390 A1), in view of Honguu et al. (US 2002/0015091 A1), further in view WAKABAYASHI (US 2015/0312476 A1).
Regarding claim 13, Gowda, Chae and Honguu disclose the method of claim 12, but did not explicitly disclose further comprising detecting the packet data corruption event using an error correction code (ECC).
Wakabayashi discloses detecting the packet data corruption event using an error correction code (ECC) (Wakabayashi [0127] discloses Based on the payload data supplied by the conversion unit 62, the payload ECC insertion unit 63 calculates an error correction code used for error correction of payload data and inserts parity which is the calculated error correction code into the payload data).
One of ordinary skill would have been motivated to combine the teachings of Gowda, Chae, Honguu and Wakabayashi because these teachings are from the same field of endeavor with respect to the use of correcting errors/distortions in image data captured and processed by image sensors.
Therefore, before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to incorporate the strategies by Wakabayashi into the method by Gowda, Chae and Honguu, thereby improving flexibility in compression and to make connectivity between an image sensor and a DSP better, Wakabayashi, [Abstract]).
Regarding claim 14, Gowda, Chae and Honguu disclose the method of claim 12, but did not explicitly disclose further comprising detecting the packet data corruption event using an error detection code (EDC).
Wakabayashi discloses detecting the packet data corruption event using an error detection code (EDC) (Wakabayashi [0111] FIG. 6, discloses in a Header ECC arranged next to the header information, a cyclic redundancy check (CRC) code which is a two-byte error detection code calculated based on six-byte header information is included. Also, in the Header ECC, two pieces of information each of which is identical to eight-byte information which information is a pair of header information and a CRC code are included next to the CRC code. The error detect code in the packet is used to detect errors in images captured by image sensors).
The motivation to combine is similar to that of claim 13.
Regarding claim 15, Gowda, Chae and Honguu disclose the method of claim 12, but did not explicitly disclose further comprising detecting the packet data corruption event using a payload count value.
Wakabayashi discloses detecting the packet data corruption event using a payload count value (Wakabayashi [0173] discloses that when parity is inserted into the payload data supplied by the packet separation unit 123, the payload error correction unit 124, uses the parity inserted in the payload to detect an error in the payload data and corrects the detected error by performing error correction calculation based on the parity).
The motivation to combine is similar to that of claim 13.
Regarding claim 16, Gowda, Chae, Honguu Wakabayashi disclose the method of claim 15, wherein the payload count value is a byte count or a bit count (Wakabayashi [0228] discloses in step S40, a conversion unit 125 which converts payload data into a compression data format of the prescribed number of bits in a unit of eight bits, 10 bits, 12 bits, 14 bits, or 16 bits and outputs the converted data to the expansion unit 144. Error correction using parity is arbitrarily performed by the payload error correction unit 124 with respect to payload data to be converted. Here, it is assumed that conversion into a 12-bit compression data format is performed).
The motivation to combine is similar to that of claim 13.
Regrading claim 30, the claim is rejected with rational similar to that of claim 14.
Claim(s) 17 – 20 and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gowda et al. (US 6,344,877 B1), in view of Chae et al. (US 2021/0209390 A1), in view of Honguu et al. (US 2002/0015091 A1), further in view Hyatt (US 2012/0188406 A1).
Regarding claim 17, Gowda, Chae and Honguu disclose the method of claim 12, but did not explicitly disclose further comprising determining if the packet data corruption event is the errored pixel or the errored line by using an aggregator hardware without software involvement.
Hyatt discloses determining if the packet data corruption event is the errored pixel (determines if a pixel is an outliner) or the errored line by using an aggregator hardware (ASIC/multiplexer) without software involvement (Hyatt [0007] discloses a computing system which includes an image capture device and an application specific integrated circuit (ASIC) filter coupled to the image capture device and a multiplexer. The ASIC filter includes an averaging circuit configured to provide an output representing an average value of a first set of values of a pixel grouping and an outlier determining circuit configured to determine if a value of a target pixel is outside a range of values for first set of values of the pixel grouping. [0009] a charge-coupled device (CCD) for image capture coupled to the processor. A filter device is coupled to between the CCD and the processor. The filter device is configured to determine if a value of a target pixel is an outlier/errored pixel relative to a range of values representing a set of pixels surrounding the target pixel. If the target pixel is an outlier, the filter replaces the value of the target pixel with an average of the values of the pixels surrounding the target pixel and outputs the average of the range of values).
One of ordinary skill would have been motivated to combine the teachings of Gowda, Chae, Honguu and Hyatt because these teachings are from the same field of endeavor with respect to the use of correcting errors/distortions in image data captured and processed by image sensors.
Therefore, before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to incorporate the strategies by Hyatt into the method by Gowda, Chae and Honguu, thereby improving the speed of identifying and correcting of the error using a hardware, Hyatt [0009].
Regarding claim 18, Gowda, Chae, Honguu and Hyatt disclose the method of claim 17, further comprising substituting the errored pixel with the dummy pixel by using the aggregator hardware without software involvement (Gowda, col. 3, lines 11-17, an image sensor including one or more dummy pixels are produced as reference signal which is used to compensate for errors within the devices of the main pixel cells. At least one dummy pixel is used in conjunction with other circuitry to correct for nonlinearities in the transfer characteristic of a source follower transistor within each pixel).
The motivation to combine is similar to that of claim 17
Regarding claim 19, Gowda, Chae, Honguu and Hyatt disclose the method of claim 18, wherein, the errored pixel is an element of an image and the errored line is one dimensional (line-based/line-level error handling) with a plurality of errored pixels within the image (Chae [0022] an error handling module may perform error handling operations on the stream of image frames on a ‘line-by-line’ basis. That is, the error handling module may perform processing for each erroneously sized (undersized or oversized) input line of the frame by either generating missing pixel data of the current faulty line or discarding the remainder of incoming pixel data of the oversized line, and then handle the next line of pixel data of the frame independently of the previous line. Thus, line-based (line-level) error handling may replicate missing pixel data only within the current line and the next line is handled as a normal line (with any applicable error handling based on detected size error)).
The motivation to combine is similar to that of claim 17
Regarding claim 20, Gowda, Chae, Honguu and Hyatt disclose the method of claim 19, wherein the location is a numerical index (error start line n+1, and error end line n+m+1) which indicates which pixel of the image is the dummy pixel or which line of the image is the dummy line (Chae [0022; 0056;0061] fig. 5, the line-level error handling module may report the error pixel count (e.g., number of pixels that had to be replicated for the short line n+1, number of pixels that had to be discarded for the long line n+m+1), and the error location or region (e.g., error start line n+1, and error end line n+m+1) within the current frame when issuing the interrupt to the host processor regarding the current faulty frame. Because error pixels are replaced with dummy pixels, the error start line and end line values in an image also represent the locations filled by the dummy pixels).
The motivation to combine is similar to that of claim 17
Regarding claim 29, the claim is rejected with rational similar to that of claim 17.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gowda et al. (US 6,344,877 B1), in view of Chae et al. (US 2021/0209390 A1), in view of Honguu et al. (US 2002/0015091 A1), in view Hyatt (US 2012/0188406 A1), further in view of Clayton et al. (US 2018/0359405 A1)
Regarding claim 21, Gowda, Chae, Honguu and Hyatt disclose the method of claim 20, but did not explicitly disclose further comprising resuming data transmission in the series of frames of data transmission from the plurality of sensors with a subsequent line.
Clayton discloses resuming data transmission in the series of frames of data transmission from the plurality of sensors with a subsequent line (Clayton [0022] discloses a frame capture synchronizer used to determine when a capture offset of any of the image sensors is above an offset threshold value. If the capture offset for a particular image sensor is determined to above the offset threshold value, a restart signal is sent to that image sensor. The restart signal causes that image sensor to restart image data capture operations at a different capture offset relative to the common time base).
One of ordinary skill would have been motivated to combine the teachings of Gowda, Chae, Honguu, Hyatt and Clayton because these teachings are from the same field of endeavor with respect to the capturing and processing of image data.
Therefore, before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to incorporate the strategies by Clayton into the method by Gowda, Chae, Honguu and Hyatt thereby synchronizing image frame capture timing for a plurality of fixed-frame rate image sensors having the same frame rate, Clayton [Abstract]).
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Stone et al. (US 2013/0312043 A1) in view of Chae et al. (US 2021/0209390 A1), in view of Kloth (US 2007/0195699 A1), further in view of Honguu et al. (US 2002/0015091 A1),
Regarding claim 22, Stone discloses a method for error recovery, the method comprising (Stone, fig. 5, [0051] discloses a data acquiring system used for capturing telemetry data from various data sources/devices. The system performs several functions including error correction):
detecting an image control error event in a series of frames of data transmission from a plurality of sensors (Stone [0023;0042], in real time, the aggregator acquires sensor data streams from a plurality of sensors that can be analyzed by parts of the aggregator which includes an analysis tools module 240, rule manager module 250 and analytic engine 260 to detect threats/illegal/error in the data that is being transmitted),
generating a synthesized control packet (alert) based on a detection of the image control error event (Stone [0024] discloses a system that monitors venue 120, using the real time data acquired from the sensor arrays 122 and the facial recognition techniques, isolate and identify these potentially threating patterns of activity, behavior, and/or status and issue alerts or pre-alerts in advance of undesirable conduct),
Stone did not explicitly disclose substituting an errored pixel upon receipt of the error flag message on the multiplexed data stream, wherein the dummy pixel enables an error recovery scheme for maintenance of a data packet dimension and wherein the maintenance avoids a hardware violation and avoids a reset; and resuming data transmission in the series of frames of data transmission from the plurality of sensors with a subsequent line after the detection of the image control error event.
Chae discloses substituting an errored pixel with a dummy pixel upon receipt of the error flag message (receiving an interrupt/error flag message and reports detecting violations) on the data stream (Chae, figs. 1-4, [0037; 0045, 0054] when one or more of the above frame sync signal protocol violations are detected, error handling module 156 generates an interrupt and reports/flags the detected violations (e.g., protocol violation or error). Frame-based (or frame-level) error handling and concealment in which once a size error is detected at any point in a given image frame by error handling module 156, the remainder of the erroneous frame is discarded and filled with dummy data),
wherein the dummy pixel enables an error recovery scheme for maintenance of a data packet dimension (repeat image data of the last known good pixel to complete the frame) (Chae, fig. 1, [0043-0044] when error handling module 156 detects an oversized input frame (e.g., long frame, line line) while processing the current input frame received from receiver 120 (e.g., first frame or line size greater than reference frame or line size, the error handling module 156 goes into error handling mode to perform oversized input frame handling (error concealment operation) by discarding all remaining incoming streams of the current oversized image frame and going into error frame quick completion mode by generating the remaining pixel/line data to complete the oversized frame as quickly as possible with dummy data. Since the frame is deemed an error frame, error handling module 156 may repeat image data of the last known good pixel to complete the frame according to its normal expected size (maintenance of a data packet dimension)); and
wherein the maintenance avoids a hardware violation and avoids a reset (Chae, [0045], The error concealment operation of error handling module 156, that enables image processing unit 155 to complete the current frame with the correct frame size, prevents any deadlock conditions in the control logic in the rest of image processing unit 155 or in other downstream modules of the image processing pipeline and enables seamless error recovery with minimal frame loss and without a hardware (sub-system) reset from a frame size error).
One of ordinary skill would have been motivated to combine the teachings of Stone and Chae because these teachings are from the same field of endeavor with respect to error recovery in a received or transmitted image data.
Therefore, before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to incorporate the strategies by Chae into the method by Stone, thereby enabling a hardware-based approach to image error correction, thus enhancing high performance, high reliability, and low-latency in the image processing system, Chae [0045].
Stone and Chae did not explicitly disclose, “multiplexed data stream” resuming data transmission in the series of frames of data transmission from the plurality of sensors with a subsequent line after the detection of the image control error event.
Kloth discloses resuming data transmission in the series of frames of data transmission from the plurality of sensors with a subsequent line after the detection of the image control error event (Kloth, fig. 3C, [0040-0041] discloses block 336 where direct transmission of additional frames to a network entity is suspended because of a pause frame received from the network entity due to a corruption of an error correction value. In blocks 338-340, upon expiration of the pause resume transmission of frames in the output buffer).
One of ordinary skill would have been motivated to combine the teachings of Stone, Chae, and Kloth because these teachings are from the same field of endeavor with respect to the capturing and processing of image data.
Therefore, before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to incorporate the strategies by Kloth into the method by Stone and Chae so that when an entity detects an impending full condition, it cuts short its transmission of the current frame that is being sent, and immediately sends a pause signal, enabling efficient flow control and enhancing efficient data transfer, Kloth, [Abstract].
Stone, Chae and Kloth did not explicitly disclose sending an error flag message on a multiplexed data stream to provide packet data corruption event notification.
Honguu discloses sending an error flag message on a multiplexed data stream to provide packet data corruption event notification (Honguu, fig. 1, [0051] discloses a multiplexing circuit 11 as a channel encoder that encodes image data that has been inputted from the transmission changeover portion 10 of a video telephone 1, and that serve as the transmitted data, encodes the audio data that has been inputted from the audio processing portion/audio storage portion 30, adds an error correction code/flag, multiplexes the data with data classification flags, control signals and synchronization signals, and outputs/sends the error correction code/flag via a multiplexed stream data to a modem 3).
substituting an errored pixel upon receipt of the error flag message on the multiplexed data stream (Honguu, fig. 1, [0051] discloses a multiplexing circuit 11 as a channel encoder that encodes image data that has been inputted from the transmission changeover portion 10 of a video telephone 1, and serves as the transmitted data, encodes the audio data that has been inputted from the audio processing portion/audio storage portion 30, adds an error correction code/flag, multiplexes the data with data classification flags, control signals and synchronization signals, and outputs/sends the error correction code/flag via a multiplexed stream data to a modem 3, where the correction code is used to substitute an errored pixel),
One of ordinary skill would have been motivated to combine the teachings of Stone, Chae, Kloth and Honguu because these teachings are from the same field of endeavor with respect to error recovery in a received or transmitted image data.
Therefore, before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to incorporate the strategies by Honguu into the method by Stone, Chae and Kloth, thereby enabling efficient use of the function of a video telephone to store incoming calls, Honguu [Abstract].
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Stone et al. (US 2013/0312043 A1) in view of Chae et al. (US 2021/0209390 A1), in view of Kloth (US 2007/0195699 A1), in view of Honguu et al. (US 2002/0015091 A1), further in view of Yonge, III et al. (US 2006/0198387 A1)
Regarding claim 23, Stone, Chae, Kloth and Honguu disclose the method of claim 22, but did not explicitly disclose wherein the image control error event is a start of frame (SOF) packet control error or an end of frame (EOF) packet control error.
Yonge discloses wherein the image control error event is a start of frame (SOF) packet control error or an end of frame (EOF) packet control error (Yonge [0008] discloses a transmission format that includes a start of frame delimiter (SOF), a payload, and an end of frame delimiter (EOF), wherein the SOF and EOF each contain sufficient information to permit a station receiving only one of the SOF and EOF to determine the start of a priority resolution period, and wherein the SOF can specify that a response delimiter is expected).
One of ordinary skill would have been motivated to combine the teachings of Stone, Chae, Kloth, Honguu and Yonge because these teachings are from the same field of endeavor with respect to the capturing and processing of image data.
Therefore, before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to incorporate the strategies by Yonge into the method by Stone, Chae, Kloth and Honguu enabling a plurality of stations communicate over a shared medium and contend for access during a priority resolution period, Yonge, [Abstract].
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Stone et al. (US 2013/0312043 A1) in view of Chae et al. (US 2021/0209390 A1), in view of Kloth (US 2007/0195699 A1), in view of Honguu et al. (US 2002/0015091 A1), further in view Chapman et al. (US 2005/0141943 A1).
Regarding claim 24, Stone, Chae, Kloth and Honguu disclose the method of claim 22, but did not explicitly disclose wherein the image control error event is a start of line (SOL) packet control error or an end of line (EOL) packet control error.
Chapman discloses wherein the image control error event is a start of line (SOL) packet control error or an end of line (EOL) packet control error (Chapman [0033] when the transmitter detects the LC line going to logic high, it sends a line of data, with control characters, across the communication link. The line of data is sent as follows: the transmitter sends a SOL character followed by the image data a specified number of clocks later. A specific number of clocks after the last data byte is sent, the transmitter sends the EOL character. A specific number of clocks after the EOL character is sent, the transmitter sends the EXP character. The transmitter then waits for the next LC transition to send the next line of data).
One of ordinary skill would have been motivated to combine the teachings of Stone, Chae, Kloth, Honguu and Chapman because these teachings are from the same field of endeavor with respect to the capturing and processing of image data.
Therefore, before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to incorporate the strategies by Chapman into the method by Stone, Chae, Kloth and Honguu to improve the retention of synchronization between the transmitter and receiver of image data across a communication channel, Chapman, [Abstract].
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Stone et al. (US 2013/0312043 A1) in view of Chae et al. (US 2021/0209390 A1), in view of Kloth (US 2007/0195699 A1), in view of Honguu et al. (US 2002/0015091 A1), further in view Johnson et al. (US 5,961,655).
Regarding claim 25, Stone, Chae, Kloth and Honguu disclose the method of claim 22, but did not explicitly disclose further comprising generating the synthesized control packet by using an aggregator hardware without software involvement.
Johnson discloses generating the synthesized control packet by using an aggregator hardware without software involvement (Johnson, col. 4, line 58- col.5, line 30, one or more error correction schemes are applied 1014 to the fetched data by an error correction hardware 106. When a fetched data is determined to be incorrect, a correction 1014 of the fetched data begins with the error correction hardware’s transmission of an error signal 120 to a processing unit 104. Once the error is corrected, corrected data is outputted from the error correction hardware 106 and transmitted via a bus 116 to an internal cache 122).
One of ordinary skill would have been motivated to combine the teachings of Stone, Chae, Kloth, Honguu and Johnson because these teachings are from the same field of endeavor with respect to the use of sensors for data collection and processing.
Therefore, before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to incorporate the strategies by Johnson into the method by Stone, Chae, Kloth and Honguu thereby enabling the use of pre-corrected data to improve the performance of processors, Johnson, [Abstract].
Claim(s) 26 – 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Stone et al. (US 2013/0312043 A1) in view of Chae et al. (US 2021/0209390 A1), in view of Kloth (US 2007/0195699 A1), in view of Honguu et al. (US 2002/0015091 A1), further in view Seaman et al. (US 2006/0044582 A1).
Regarding claim 26, Stone, Chae, Kloth and Honguu disclose the method of claim 22, but did not explicitly disclose further comprising creating a synthesized user-defined (UD) packet to signify the detection of the image control error event.
Seaman discloses creating a synthesized user-defined (UD) packet to signify the detection of the image control error event (Processor generates an error message) (Seaman, fig. 11, [0047] discloses an execution of the process flow begins at block 142. A process flow, which is one of the process flows 48, is created by a user and provided to the processor 56 in blocks 144-148. At block 144, the user selects image-processing modules to be included in the process flow. The user may also use a user-defined process flow or a previously created process flow. The processor 56 verifies that the image-processing modules in the process flow are valid at block 148. If one or more of the image-processing modules are invalid, then the processor 56 does not perform the process flow and generates an error message that is presented to the user, as shown in block 158. However, if the image-processing modules are valid, then the processor 56 executes each of the image-processing modules in the process flow, as shown in blocks 150-156).
One of ordinary skill would have been motivated to combine the teachings of Stone, Chae, Kloth, Honguu and Seaman because these teachings are from the same field of endeavor with respect to the use of sensors for data collection and processing.
Therefore, before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to incorporate the strategies by Seaman into the method by Stone, Chae, Kloth ,and Honguu provide a processor with a standard image format for uniformly using at least one image file for each of the image-processing modules, and provide the processor with a standard file reference for uniformly accessing the at least one image file for each of the image-processing modules, Seaman, [Abstract].
Regarding claim 27, Stone, Chae, Kloth, Honguu and Seaman disclose the method of claim 26, further comprising creating the synthesized user-defined (UD) packet by using an aggregator hardware (processor 59) without software involvement (Seaman, fig. 11, [0047] discloses an execution of the process flow begins at block 142. A process flow, which is one of the process flows 48, is created by a user and provided to the processor 56 in blocks 144-148. At block 144, the user selects image-processing modules to be included in the process flow. The user may also use a user-defined process flow or a previously created process flow. The processor 56 verifies that the image-processing modules in the process flow are valid at block 148. If one or more of the image-processing modules are invalid, then the processor 56 does not perform the process flow and generates an error message that is presented to the user, as shown in block 158. However, if the image-processing modules are valid, then the processor 56 executes each of the image-processing modules in the process flow, as shown in blocks 150-156).
The motivation to combine is similar to that of claim 26.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.F.D/ Examiner, Art Unit 2451
/Chris Parry/Supervisory Patent Examiner, Art Unit 2451