Prosecution Insights
Last updated: July 17, 2026
Application No. 18/352,525

DISPLAY PANEL AND METHOD FOR FABRICATING THE SAME

Non-Final OA §103
Filed
Jul 14, 2023
Priority
Mar 03, 2023 — CN 202310197089.4
Examiner
FAROKHROOZ, FATIMA N
Art Unit
2875
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
HKC Corporation Limited
OA Round
3 (Non-Final)
48%
Grant Probability
Moderate
3-4
OA Rounds
0m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 48% of resolved cases
48%
Career Allowance Rate
413 granted / 851 resolved
-19.5% vs TC avg
Strong +33% interview lift
Without
With
+33.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
40 currently pending
Career history
901
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
96.7%
+56.7% vs TC avg
§102
2.4%
-37.6% vs TC avg
§112
0.3%
-39.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 851 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/22/26 has been entered. Claims 1-2,6-11 and 15-20 remain pending in the application. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1,7,8,10 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Applicant’s Admitted Prior art (AAPA, Fig.1 in Applicant’s disclosure US Pub: US 20240298475 A1, cited previously) in view of Park (US 20240276786 A1, cited previously) and Wang (CN 107819017 A) Regarding claim 1, AAPA teaches a display panel (Fig.1 and [0029],[0037]), comprising, from bottom to top: a substrate (bottom most layer), a drive layer (the layer that is electrically connecting the anode and is right on top surface of substrate), an anode layer (the layer with V marks that is connected to the driver layer), a luminescent layer (the layer above the anode layer), a cathode layer (the black layer above the luminescent layer), and an encapsulation layer (first inorganic encapsulation layer 61); wherein the anode layer comprises a plurality of anode units arranged at intervals (because of pixel defining layers which is indicative of several anodes, and also as is well known in the art); a pixel defining layer (lowest layer separating the anodes on the left and right side) is arranged around the plurality of anode units; the pixel defining layer comprises a plurality of pixel defining units (because Fig.1 is a display device and has to have several pixels and pixel defining units), each of the plurality of pixel defining units is arranged between adjacent anode units; a plurality of conductive units (the while layer above the pixel defining units in Fig.1) are arranged on the plurality of pixel defining unit, respectively, and a plurality of eave layers 90 ([0037] top most layer over the pixel defining unit) are arranged on the plurality of conductive units, respectively; the luminescent layer is covered on the plurality of anode units and the plurality of pixel defining units; the cathode layer is covered on the luminescent layer; the encapsulation layer 61 is covered on the cathode layer, the plurality of conductive units, and the plurality of eave layers; wherein the encapsulation layer comprises a first inorganic encapsulation layer (61 in [0037]), an organic buffer layer 62 ([0037]) and a second inorganic encapsulation layer (top most cover layer), the first inorganic encapsulation layer is disposed above the cathode layer and the plurality of eave layers, the organic buffer layer is disposed above the first inorganic encapsulation layer, and the second inorganic encapsulation layer is disposed above the organic buffer layer. Although AAPA does not explicitly label the substrate, driver layer, anode, luminescent layer, cathode and the second inorganic encapsulation layer, however, Applicant discloses throughout the disclosure that the only difference or improvement between the AAPA of Fig.1 and Applicant’s invention is the region 99 of AAPA; see in [0038] of Applicant’s invention: [0038] In view of this, embodiments of the present application provide a display panel, which is used to reduce the formation of voids in the region below the eave layer 90 when the light emitting device is fabricated using photolithography technology, thereby reducing the occurrence of display defects on the display panel. and therefore, the rest of the elements of Applicant’s invention/other Drawings are all disclosed similarly in AAPA of Fig.1, excepting the problem that the Applicant is solving regarding the region 99 of AAPA). Further even more, regarding the material of the second encapsulation layer, that is not disclosed in AAPA, Park explicitly teaches the top most inorganic encapsulation layer UIL ([0171],[172] and [0168]). Further Park teaches the first inorganic encapsulation layer LIL, the organic buffer layer OL and the second inorganic encapsulation layer UIL ([0171],[172] and [0168])) and therefore it would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to use the second inorganic material, in the device of Park, in the device of AAPA in order to achieve robust sealing and protection for the device. AAPA in view of Park does not teach: at least one step is formed on a top of a lateral side of the pixel defining layer. Wang teaches formation of at least one step on a top of a lateral side of the pixel defining layer (at least Fig.3). Wang discloses: The invention claims a pixel definition structure comprises an at least two-layer step of the stepped structure is provided, the pixel definition structure defining ink flowing into the sub-pixel area, on one hand, can inhibit the climbing of ink drop height is too high, on the other hand, it can maintain the loading amount of ink droplet. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to form a step on a top of a lateral side of the pixel defining layer of AAPA in view of Park, from the teachings of Wang, in order to inhibit the climbing of ink drop and to maintain the loading amount of ink droplet. Regarding claim 10, AAPA in view of Park and Wang teaches a method for fabricating the display panel according to claim 1, the method comprising: forming the drive layer on the substrate; forming the anode layer on the drive layer, wherein the anode layer comprises the plurality of anode units arranged at intervals; forming each of the plurality of pixel defining units between adjacent anode units; forming the luminescent layer above the anode layer and the plurality of pixel defining units, and forming the cathode layer on the luminescent layer; forming the plurality of conductive units on the plurality of pixel defining units, respectively, and forming the plurality of eave layers on the plurality of conductive units, respectively; and forming the encapsulation layer above the cathode layer, the plurality of conductive units, and the plurality of eave layer; wherein at least one step is formed on a top of a lateral side of the pixel defining layer; the encapsulation layer comprises a first inorganic encapsulation layer, an organic buffer layer and a second inorganic encapsulation layer, the first inorganic encapsulation layer is disposed above the cathode layer and the plurality of eave layers, the organic buffer layer is disposed above the first inorganic encapsulation layer, and the second inorganic encapsulation layer is disposed above the organic buffer layer (see rejection in claim 1 as the scope of the claims is the same). Regarding claims 8, 17, 18 and 19, AAPA in view of Park and Wang teaches each of the plurality of pixel defining units partially covers corresponding anode units (Fig.1 of AAPA). Regarding claims 7 and 16, AAPA in view of Park and Wang teaches an included angle between the upper end surface of the anode layer and the inclined lateral side surface of each of the plurality of pixel defining units is an acute angle (Fig.1 of AAPA) PNG media_image1.png 255 446 media_image1.png Greyscale but does not explicitly the angle is greater than or equal to 15 degrees, and smaller than or equal to 45 degrees. However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to use the acute angle to be greater than or equal to 15 degrees, and smaller than or equal to 45 degrees, by routine experimentation, in order to optimize the reduction in an emission area relative to the pixel area. Claims 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over AAPA in view of Park and Wang and further in view of Chen (CN 107658326 A, cited previously) Regarding claims 9 and 20, AAPA in view of Park and Wang teaches the invention set forth in claims 1 and 10 above, but is silent regarding a width of each of the plurality of pixel defining units covering a corresponding anode unit is greater than or equal to 0.5 μm and smaller than or equal to 1 μm; and a thickness of each of the plurality of pixel defining units covering a corresponding anode unit is greater than or equal to 0.3 μm and smaller than or equal to 2 μm. Chen teaches the dimensions range of the pixel defining unit as below: a) the thickness of the pixel defining layer of the pixel electrodes of two sub-pixel in each sub-pixel group is 0.1 μ % of the thickness of the pixel defining layer between 0.2 μ m, and the adjacent sub-pixel group is 0.5 μ m to 2 μ m. b) In one embodiment, two sub-pixels of each sub-pixel group 215 in the 21 of the pixel electrode 214 between the pixel defining layer 218 has a thickness of 0.1 μ m to 0.2 μ m, and the adjacent sub-pixel groups 218 of the thickness of the pixel defining layer 215 is 0.5 μ m to 2 μ m. c) a pixel defining layer may be formed by, but not limited to half-exposure process once. the thickness of different regions, in one further embodiment, the pixel defining layer are different, according to the thickness of the pixel defining layer between two sub-pixel electrodes in one sub-pixel electrode group to be thin. The can is 0.1 μ m to 0.2 μ m, the thickness is the thickness of the pixel defining layer between different sub-pixel electrode group, such as is 0.5 μ m to 2 μm, but with thinner thickness region or thicker area, are formed by one-step moulding technology. Therefore, from the teachings of the known dimensions in Chen, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to achieve the dimensions with respect to the anode, by routine experimentation, in the device of AAPA in view of Park and Wang in order to achieve a high-resolution display. Claims 2,6 ,11 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Applicant’s Admitted Prior art (AAPA) in view of Park and Wang and further in view of Choung (US 11348983 B1, cited previously) Regarding claim claims 2 and 11, AAPA in view of Park and Wang teaches in a top-view projection onto the substrate, a projection area of a lower end surface of each of the plurality of conductive units onto the substrate is within a projection area of an upper end surface of a corresponding pixel defining unit onto the substrate; and there is a lateral distance between an edge of the upper end surface of each of the plurality of pixel defining units and an edge of the lower end surface of a corresponding conductive unit (the distance is shown within the vertical lines below): PNG media_image2.png 301 464 media_image2.png Greyscale but does not teach the maximum lateral distance is smaller than or equal to 1 micrometer. However, this configuration is well known in the art, and it is a well-known technique maintain this distance. Additional Prior art Choung discloses the same configuration of the lateral distance (Fig.1B) as claimed. PNG media_image3.png 292 381 media_image3.png Greyscale Choung further discloses: The cathode 114 is be disposed on a portion of a sidewall 111 of the base portion 110A. The conductive base portion 110A ensures permanent connection to the cathode 114. Therefore, since the profile/shapes are relatively the same as claimed, in both AAPA and Choung and the disposition of the cathode on the pixel defining layer is a result effective design variable, therefore It would have been obvious to a person having to achieve teach the maximum lateral distance is smaller than or equal to 1 micrometer by routine experimentation or simulation in order to optimize the connection between the cathode and the conductive layer. Regarding claims 6 and 15, AAPA in view of Park, Wang and Choung teaches the same relative shape or profile of the conductive units when compared to the eave layer, but does not teach a distance between an edge of a lower end surface of each of the plurality of conductive units and an edge of a lower end surface of a corresponding eave layer is greater than or equal to 2 μm and smaller than or equal to 3 μm. However since the profile/shapes are relatively the same as claimed, therefore It would have been obvious to a person having to achieve a distance between an edge of a lower end surface of each of the plurality of conductive units and an edge of a lower end surface of a corresponding eave layer is greater than or equal to 2 μm and smaller than or equal to 3 μm by routine experimentation in order to increase the pixel-per-inch (as disclosed in Choung). Other art KR 20140127688 A also teaches stepped shape at the top of the pixel defining layer as shown below: PNG media_image4.png 274 465 media_image4.png Greyscale Response to Arguments The arguments filed by the Applicant on 4/22/26 is acknowledged, however they are moot in light of new grounds of rejection for the amended claims. KR 20140127688 A also teaches stepped shape at the top of the pixel defining layer as shown below: PNG media_image4.png 274 465 media_image4.png Greyscale Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to Fatima Farokhrooz whose telephone number is (571)-272-6043. The examiner can normally be reached on Monday- Friday, 9 am - 5 pm. If attempts to reach the examiner by telephone are unsuccessful, the Examiner’s Supervisor, James Greece can be reached on (571) 272-3711. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Fatima N Farokhrooz/ Examiner, Art Unit 2875
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Prosecution Timeline

Jul 14, 2023
Application Filed
Sep 10, 2025
Non-Final Rejection mailed — §103
Dec 03, 2025
Response Filed
Feb 12, 2026
Final Rejection mailed — §103
Apr 22, 2026
Request for Continued Examination
Apr 27, 2026
Response after Non-Final Action
May 05, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
48%
Grant Probability
82%
With Interview (+33.3%)
2y 11m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 851 resolved cases by this examiner. Grant probability derived from career allowance rate.

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