DETAILED ACTION
Amendments submitted on June 11, 2026 for Application No. 18/352602 are presented for examination by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Internet Communications
Applicant is encouraged to submit a written authorization for Internet communications (PTO/SB/439, found at http:/www.uspto.gov/sites/default/files/documents/sb0439.pdf) in the instant patent application to authorize the examiner to communicate with the applicant via email. The authorization will allow the examiner to better practice compact prosecution. The written authorization can be submitted via one of the following methods only: (1) Central Fax, which can be found in the Conclusion section of this Office action; (2) regular postal mail; (3) EFS WEB; or (4) the service window on the Alexandria campus. EFS web is the recommended way to submit the form since this allows the form to be entered into the file wrapper within the same day (system dependent). Written authorization submitted via other methods, such as direct fax to the examiner or email, will not be accepted. See MPEP § 502.03.
Applicant is also encouraged to contact the Examiner for an Interview, should the Applicant determine that clarifying and further illustrating the distinguishing features of the instant application may further the prosecution.
Response to Arguments
4. Applicant’s arguments filed June 11, 2026 have been considered but they are not persuasive. In the remarks applicant argues:
I) On page 7, Applicant argues that the previous claim objections and 35 USC 112 rejections should be withdrawn.
Applicant’s amendments have overcome the previous claim objections and 35 USC 112 rejections; therefore, they have been withdrawn.
II) On pages 7-8, Applicant argues that the cited prior art does not teach the new limitation of claim 16 reciting “evaluating performance of the processor architecture and the AI model, without executing the AI model on a processor configured according to the processor architecture, using a software composer module, a hardware composer module, and a performance calculator module”.
Applicant’s arguments are considered moot based on the new grounds of rejection as set forth below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Honnavara-Prasad (US 10884485) in view of Vandriessche (US 2019/0004920).
As per claim 16, Honnavara-Prasad discloses A method of improving performance of a processor system and associated software, comprising:
selecting a set of performance parameter targets for a processor architecture having a set of functional units and an AI model (Honnavara-Prasad, Figure 2 and associated texts such as cols. 3-5, teaches training and testing an AI models power consumption data.);
evaluating performance of the processor architecture and the AI model … using a software composer module, a hardware composer module, and a performance calculator module (Honnavara-Prasad, Figure 2 and associated texts such as cols. 3-5, teaches training and testing an AI models power consumption data. The Examiner would note that since the software composer module, hardware composer module, and performance calculator module have not been specifically defined that the training and testing of the AI model by Honnavara-Prasad will be considered as using the software composer module, hardware composer module, and performance calculator module.);
adjusting at least one of the functional units of the processor architecture to form a new processor architecture prior to iteratively evaluating the combination of the new processor architecture and the AI model (Honnavara-Prasad, Figure 2 and associated texts such as cols. 3-5, teaches optimizing the AI model based on the training and testing.); and
repeating the evaluating step and the adjustment step until the performance evaluation of the processor architecture and the AI model meets the set of performance parameter targets (Honnavara-Prasad, col. 4 lines 44-61, teaches optimizing the AI model based on the power consumption analysis multiple times.)
However, Honnavara-Prasad does not specifically teach “without executing the AI model on a processor configured according to the processor architecture”.
Vandriessche discloses without executing the … model on a processor configured according to the processor architecture (Vandriessche, paragraphs 1, 20, 30, and 47, and Figures 3-7 and their associated texts, teaches simulating a processor architecture for testing purposes.)
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Vandriessche with the teachings of Honnavara-Prasad. Honnavara-Prasad teaches training and testing an AI models power consumption data using the AI processor. Vandriessche teaches simulating a processor architecture for testing purpose. Therefore, it would have been obvious for the system of Honnavara-Prasad to have used a simulated AI processor instead of using the actual AI processor (as in Vandriessche) as this would allow the AI processor to be tested without having to actually build the physical AI processor to test. This would allow any issues to be discovered and rectified prior to building the AI processor.
As per claim 17, Honnavara-Prasad in view of Vandriessche discloses The method of claim 16, wherein selecting the performance parameters targets are at least one of consumed power, latency, throughput constraint, accuracy, die-area, or thermal performance for the processor architecture (Honnavara-Prasad, Figure 2 and associated texts, teaches testing power consumption.)
As per claim 18, Honnavara-Prasad in view of Vandriessche discloses The method of claim 16, wherein the processor architecture is deterministic (Honnavara-Prasad, col. 4 lines 7-12, teaches that the system is deterministic.)
As per claim 19, Honnavara-Prasad in view of Vandriessche discloses The method of claim 16, wherein the processor architecture is a tensor streaming processor (Honnavara-Prasad, col. 3 lines 42-60, col. 5 lines 36-38, and claim 17, teaches representing the AI model as a tensorflow graph and also teaches a tensor streaming processor.)
Allowable Subject Matter
Claims 1, 9, and 20 are objected to as being allowable, but would be allowable if the 35 USC 112 Rejections and Claim Objections are overcome. The following is an examiner’s statement of reasons for allowance: The primary reason for the allowance of the claims is the inclusion of the limitation, inter alia, “a hardware composer module configured to provide a processor architecture representation to a mapper module; a software composer module configured to take the AI model and pass it to a compiler for conversion into a device agnostic intermediate representation module, the mapper module further to map an output of the device agnostic intermediate representation module onto the processor architecture representation; and a performance calculator module configured to receive results derived from the software composer module and the hardware composer module and model performance of the AI model on the processor architecture, with performance results being provided to the software composer module and the hardware composer module to permit respectively configured to adjust the AI model and the processor specific architecture". The closest prior art of record includes:
Honnavara-Prasad (US 10884485) – teaches converting an AI model to be for a specific type of hardware or “circuit blocks in the AI processor”. Honnavara-Prasad also teaches training and testing the AI model to be optimized based on power consumption data.
Aldana Lopez (US 2019/0095794) – teaches training a neural network processor using a learning rate calculated based on tuning parameters.
Varadarajan (US 2019/0244139) – teaches automatic optimization for machine learning and deep learning models.
Javaheri (US 2022/0058578) – teaches a device agnostic AI model.
Sommer (US 2017/0357910) – teaches that an AI model can be device dependent or device independent.
Vandriessche (US 2019/0004920) – teaches simulating a processor architecture for testing purposes.
Smith (US 8862770) – teaches simulating a processor architecture using two different simulators and comparing the results.
Zhang (US 2021/0334137) – teaches testing the performance of an AI model running on an AI processor by simulating the AI processor using a cloud AI processor based on the AI processor and executing an AI learning task based on the binary instructions of the AI model.
However, the combination of limitations as currently claimed cannot be found in the cited prior art of record.
Claims 2-8 and 10-15 are objected to for the same reasons as cited above and for being dependent on a previously objected to base claim.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN B KING whose telephone number is (571)270-7310. The examiner can normally be reached on Monday-Friday 10AM-6PM EST.
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/John B King/
Primary Examiner, Art Unit 2498
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