Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
In response to the Non-Final Rejection of 25-August-2025, Applicant has submitted a set of Amendments on 19-November-2025 adding clarifying language to independent claims 1, 21 and 26 and modifying their dependent claims to match the changes.
Response to Arguments
In response to the Non-Final Rejection of 25-August-2025, Applicant has submitted a set of Arguments on 19-November-2025. These arguments have been fully considered and are not found persuasive.
In their first argument, Applicant acknowledged the Double Patenting rejections of independent claims 1, 21 and 26 contained in the Non-Final Rejection (without admitting the propriety of those rejections) and states that a Terminal Disclaimer is forthcoming which will cure the Double Patenting issues. As of the date of this Final Rejection, however no Terminal Disclaimer has been received. As a result, the Double Patenting rejections are maintained below.
In their second argument, Applicant essentially states that the limitation send a signal to the non-volatile memory identifying memory regions of the non-volatile memory from which to access data; access multiple copies of data from the identified memory regions (emphasis added by Applicant) is not taught by Cullen, and that independent claims 1, 21 and 26 (and their dependent claims) are allowable for this reason.
Although Examiner agrees with the first part of this conclusion, after further search and consideration, Examiner notes that Feeley teaches “Performing the error correction operation can, in some embodiments, include performing a bit-by-bit comparison of multiple previously read-verified and stored copies of the defined set of data, where the solid state device validates one or more copies from among the multiple copies by selecting from a majority of matching copies” (Col 15, lines 65-67 and Col 16 lines 1-4) and that this comparison of stored copies from the solid-state device would require read requests to the memory storing the data that (at a minimum) identify the address(es) of the data in the solid-state device. As a result, Examiner must respectfully disagree with this conclusion.
Any rejections from the Non-Final Rejection not repeated below are hereby withdrawn.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 21 and 26 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 13 of U.S. Patent No. 10,901,862. Although the claims at issue are not identical, they are not patentably distinct from each other because they are claiming similar subject matter as showed, for example, in the Claims Comparison Tables below. It would have been obvious to a person of ordinary skill in the art at the time the intention was made to modify, add or omit the additional elements of claims to arrive at the claims 1, 21 and 26 of the instant application because the skilled person in the art would have realized that the remaining element would perform the same functions as before. “Omission of element and its function in combination is obvious expedient if the remaining elements perform same functions as before.” See In re Karlson (CCPA) 136 USPQ 184, decide Jan 16 , 1963, Appl. No. 6857, U. S. Court of Customs and Patent Appeals.
Application 16189697 (Patent 10901862)
Instant Application 18352744
1. A system comprising: non-volatile memory; a processing device; and memory storing instructions configured to instruct the processing device to: receive a request to access data; in response to receiving the request, access data from multiple copies stored in the non-volatile memory; match data from the copies with each other; select, based on matching the data from the copies with each other, first data associated with a first copy of the copies; and provide the first data as an output from the non-volatile memory.
1. An apparatus comprising: a non-volatile memory; at least one processing device configured to: send a signal to the non-volatile memory identifying memory regions of the non-volatile memory from which to access data; access multiple copies of data from the identified memory regions; and select a copy of the multiple copies based on matching portions of the data from the multiple copies with each other.
1. A system comprising: non-volatile memory; a processing device; and memory storing instructions configured to instruct the processing device to: receive a request to access data; in response to receiving the request, access data from multiple copies stored in the non-volatile memory; match data from the copies with each other; select, based on matching the data from the copies with each other, first data associated with a first copy of the copies; and provide the first data as an output from the non-volatile memory.
13 . The system of claim 11, wherein the request to access data is received from a host system, wherein providing the first data comprises sending the first data to the host system, and wherein the host system is configured to (store the first data) in a volatile memory of the host system.
21. An apparatus comprising: a volatile memory; and at least one processing device configured to: send a signal identifying memory regions; access multiple copies of data in parallel from the identified memory regions; select a copy of the multiple copies based on matching portions of the data from the copies with each other; and transfer the selected copy to the volatile memory.
1. A system comprising: non-volatile memory; a processing device; and memory storing instructions configured to instruct the processing device to: receive a request to access data; in response to receiving the request, access data from multiple copies stored in the non-volatile memory; match data from the copies with each other; select, based on matching the data from the copies with each other, first data associated with a first copy of the copies; and provide the first data as an output from the non-volatile memory.
26. An apparatus comprising: a non-volatile memory; and at least one processing device configured to: detect an event; in response to detecting the event, send a signal identifying memory regions of the non-volatile memory; and select a copy from the identified memory regions based on matching data
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 5, 8, 21, 22, 24 - 27, 29 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent 9110832-(Feeley et al.) [herein “Feeley”] in view of U.S. Patent Publication 20150280919-(Cullen et al.) [herein “Cullen”].
Regarding claim 1 –
Feeley teaches (a)n apparatus comprising: a non-volatile memory; and a volatile memory; “Memory devices may be combined together to form a solid state device. A solid state device may include non-volatile memory (e.g., NAND flash memory and/or NOR flash memory) and/or may include volatile memory (e.g., DRAM and/or SRAM), among various other types of non-volatile and volatile memory” (col 2, lines 34-39).
Feeley also teaches access multiple copies of data in parallel from the identified memory regions; and select a copy of the multiple copies based on matching portions of the data from the multiple copies with each other; and transfer the selected copy to the volatile memory, “where the solid state device validates one or more copies from among the multiple copies by selecting from a majority of matching copies” ( Col 16, Lines 1-4).
Feeley also teaches send a signal to the non-volatile memory identifying memory regions of the non-volatile memory from which to access data “Performing the error correction operation can, in some embodiments, include performing a bit-by-bit comparison of multiple previously read-verified and stored copies of the defined set of data, where the solid state device validates one or more copies from among the multiple copies by selecting from a majority of matching copies” (Col 15, lines 65-67 and Col 16 lines 1-4).
Feeley does not teach at least one processing device configured to: detect an event; in response to detecting the event, (send a signal to the non-volatile memory identifying memory regions of the non-volatile memory from which to access data).
Cullen, however teaches at least one processing device configured to: detect an event; in response to detecting the event, (send a signal to the non-volatile memory identifying memory regions of the non-volatile memory from which to access data); (Fig 9 - “example processing module 110”) plus “A voting master (V M) unit 132 is arranged to determine a majority vote from amongst the received and acceptably signed messages obtained via the signature verification units 131. The voting master unit 13 2 determines the majority vote from amongst the received information payload and supplies the voted information content to the applications 160” (Page 5, [0066]).
Feeley and Cullen are analogous art because they are both directed to advanced methods of operating high-reliability memory based systems. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the memory architecture of Feeley with the voting mechanisms of Cullen, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to provide higher reliability memory capabilities.
Regarding claim 2 –
The combination of Feeley and Cullen teaches all the limitations of claim 1 above.
Cullen also teaches wherein the at least one processing device is further configured to vary a number of the copies accessed based on a type of the data being accessed, (Fig 9, “example processing module 110”) plus “A voting master (V M) unit 132 is arranged to determine a majority vote from amongst the received and acceptably signed messages obtained via the signature verification units 131. The voting master unit 13 2 determines the majority vote from amongst the received information payload and supplies the voted information content to the applications 160” (Page 5, [0066]).
Regarding claim 5 –
The combination of Feeley and Cullen teaches all the limitations of claim 1 above.
Cullen also teaches wherein the at least one processing device is further configured to monitor second data collected from at least one sensor, and send the signal in response to detecting an the event is-based on the monitoring, “the control system comprising: a control processing unit arranged to receive input signals from one or more sensors and to supply output signals to one or more actuators” (Page 6, Paragraph [0077]).
Regarding claim 8 –
The combination of Feeley and Cullen teaches all the limitations of claim 1 above.
Cullen also teaches wherein the selected copy is selected based on matching a majority of data entries with each other, “example processing module 110” plus “A voting master (V M) unit 132 is arranged to determine a majority vote from amongst the received and acceptably signed messages obtained via the signature verification units 131. The voting master unit 13 2 determines the majority vote from amongst the received information payload and supplies the voted information content to the applications 160” (Page 5, [0066]).
Regarding claim 21 –
Feeley teaches (a)n apparatus comprising: a volatile memory; “Memory devices may be combined together to form a solid state device. A solid state device may include non-volatile memory (e.g., NAND flash memory and/or NOR flash memory) and/or may include volatile memory (e.g., DRAM and/or SRAM), among various other types of non-volatile and volatile memory” (col 2, lines 34-39).
Feeley also teaches access multiple copies of data in parallel from the identified memory regions; “where the solid state device validates one or more copies from among the multiple copies by selecting from a majority of matching copies” ( Col 16, Lines 1-4).
In addition, Feeley teaches select a copy of the multiple copies based on matching portions of the data from the copies with each other; and transfer the selected copy to the volatile memory, “where the solid state device validates one or more copies from among the multiple copies by selecting from a majority of matching copies” ( Col 16, Lines 1-4).
Feeley also teaches (at least one processing device configured to) send a signal identifying memory regions, “Performing the error correction operation can, in some embodiments, include performing a bit-by-bit comparison of multiple previously read-verified and stored copies of the defined set of data, where the solid state device validates one or more copies from among the multiple copies by selecting from a majority of matching copies” (Col 15, lines 65-67 and Col 16 lines 1-4).
Feeley does not teach at least one processing device (configured to: send a signal identifying memory regions).
Cullen, however teaches at least one processing device configured to: (send a signal identifying memory regions); (Fig 9 - “example processing module 110”) plus “A voting master (V M) unit 132 is arranged to determine a majority vote from amongst the received and acceptably signed messages obtained via the signature verification units 131. The voting master unit 13 2 determines the majority vote from amongst the received information payload and supplies the voted information content to the applications 160” (Page 5, [0066]).
Feeley and Cullen are analogous art because they are both directed to advanced methods of operating high-reliability memory based systems. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the memory architecture of Feeley with the voting mechanisms of Cullen, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to provide higher reliability memory capabilities.
Regarding claim 22 –
The combination of Feeley and Cullen teaches all the limitations of claim 21 above.
Cullen also teaches wherein the at least one processing device is further configured to: detect an event; and in response to detecting the event, send the signal to non-volatile memory, “the control system comprising: a control processing unit arranged to receive input signals from one or more sensors and to supply output signals to one or more actuators” (Page 6, Paragraph [0077]).
Regarding claim 24 –
The combination of Feeley and Cullen teaches all the limitations of claim 21 above.
Feeley also teaches wherein matching data from the multiple copies comprises matching each of a sequential series of corresponding entries read in parallel from each of the multiple copies, “where the solid state device validates one or more copies from among the multiple copies by selecting from a majority of matching copies” ( Col 16, Lines 1-4).
Regarding claim 25 –
The combination of Feeley and Cullen teaches all the limitations of claim 24 above.
Feeley also teaches wherein the sequential series of corresponding entries are read in response to receiving a read command from a host system, “Read and write access to the memory device by the host may be performed using the logical block numbers“ (Col 4, Lines 19-20).
Regarding claim 26 –
Feeley teaches (a)n apparatus comprising: a non-volatile memory; “Memory devices may be combined together to form a solid state device. A solid state device may include non-volatile memory (e.g., NAND flash memory and/or NOR flash memory) and/or may include volatile memory (e.g., DRAM and/or SRAM), among various other types of non-volatile and volatile memory” (col 2, lines 34-39).
Feeley also teaches select a copy from the identified memory regions based on matching data, “where the solid state device validates one or more copies from among the multiple copies by selecting from a majority of matching copies” ( Col 16, Lines 1-4).
In addition, Feeley teaches send a signal identifying memory regions of the non-volatile memory, “Performing the error correction operation can, in some embodiments, include performing a bit-by-bit comparison of multiple previously read-verified and stored copies of the defined set of data, where the solid state device validates one or more copies from among the multiple copies by selecting from a majority of matching copies” (Col 15, lines 65-67 and Col 16 lines 1-4).
Feeley does not teach at least one processing device configured to: detect an event; in response to detecting the event, (send a signal identifying memory regions of the non-volatile memory).
Cullen, however teaches at least one processing device configured to: detect an event; in response to detecting the event, send a signal identifying memory regions of the non-volatile memory; (Fig 9 - “example processing module 110”) plus “A voting master (V M) unit 132 is arranged to determine a majority vote from amongst the received and acceptably signed messages obtained via the signature verification units 131. The voting master unit 13 2 determines the majority vote from amongst the received information payload and supplies the voted information content to the applications 160” (Page 5, [0066]).
Feeley and Cullen are analogous art because they are both directed to advanced methods of operating high-reliability memory based systems. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the memory architecture of Feeley with the voting mechanisms of Cullen, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to provide higher reliability memory capabilities.
Regarding claim 27 –
The combination of Feeley and Cullen teaches all the limitations of claim 26 above.
Feeley also teaches wherein the at least one processing device is further configured to access multiple copies from the identified memory regions, and the copy is selected from the multiple copies, “where the solid state device validates one or more copies from among the multiple copies by selecting from a majority of matching copies” ( Col 16, Lines 1-4).
Regarding claim 29 –
The combination of Feeley and Cullen teaches all the limitations of claim 27 above.
Feeley also teaches wherein the multiple copies are accessed in parallel, “where the solid state device validates one or more copies from among the multiple copies by selecting from a majority of matching copies” ( Col 16, Lines 1-4).
Regarding claim 30 –
The combination of Feeley and Cullen teaches all the limitations of claim 26 above.
Feeley also teaches wherein the at least one processing device is further configured to transfer the selected copy to volatile memory, “where the solid state device validates one or more copies from among the multiple copies by selecting from a majority of matching copies” ( Col 16, Lines 1-4).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent 9110832-(Feeley et al.) [herein “Feeley”], in view of U.S. Patent Publication 20150280919-(Cullen et al.) [herein “Cullen”], and further in view of U.S. Patent 9613214-(Dover).
Regarding claim 3 –
The combination of Feeley and Cullen teaches all the limitations of claim 1 above.
The combination of Feeley and Cullen does not teach the multiple copies of data are boot code stored in a boot partition of the non-volatile memory.
Dover, however teaches wherein the multiple copies of data are boot code stored in a boot partition of the non-volatile memory, (Fig 4, Item 454)
Feeley, Cullen and Dover are analogous art because they are all directed to advanced methods of operating high-reliability memory based systems. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the memory architecture of Feeley with the voting mechanisms of Cullen and the reading of boot memory as in Dover, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to provide higher reliability memory capabilities.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent 9110832-(Feeley et al.) [herein “Feeley”], in view of U.S. Patent Publication 20150280919-(Cullen et al.) [herein “Cullen”], and further in view of U.S. Patent Publication 20190163367-(Bazarsky et al.) [herein “Bazarsky”].
Regarding claim 4 –
The combination of Feeley and Cullen teaches all the limitations of claim 1 above.
The combination of Feeley and Cullen does not teach wherein a controller of the non-volatile memory determines, based on the signal, physical addresses of the non-volatile memory from which to access the multiple copies.
Bazarsky, however teaches wherein a controller of the non-volatile memory determines, based on the signal, physical addresses of the non-volatile memory from which to access the multiple copies, “A non-volatile memory system may receive a host read request from a host that requests the non-volatile memory system to read a data set. Upon receipt of the host read request, the non-volatile memory system may determine a physical address that identifies where in a nonvolatile memory array of the non-volatile memory system the data set is stored. The host read request may identify the data set by identifying a logical address in the host read request. A controller of the non-volatile memory system may be configured to translate the logical address to the physical address by maintaining a directory system that maps logical addresses to physical addresses…” (Page 1, Paragraph [0002]).
Feeley, Cullen and Bazarsky are analogous art because they are all directed to advanced methods of operating high-reliability memory based systems. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the memory architecture of Feeley with the voting mechanisms of Cullen and the host communications of Bazarsky, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to provide higher reliability and more flexible memory capabilities.
Claims 6, 7, 9 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent 9110832-(Feeley et al.) [herein “Feeley”], in view of U.S. Patent Publication 20150280919-(Cullen et al.) [herein “Cullen”], and further in view of U.S. Patent Publication 20170351968-(Bowers et al.) [herein “Bowers”].
Regarding claim 6 –
The combination of Feeley and Cullen teaches all the limitations of claim 1 above.
The combination of Feeley and Cullen does not teach wherein second data from at least one sensor is stored in memory, the signal is sent in response to an event detected detecting the event is based on output from an artificial neural network(ANN), and the second data is an input to the ANN.
Bowers, however teaches wherein second data from at least one sensor is stored in memory, the signal is sent in response to an event detected detecting the event is based on output from an artificial neural network(ANN), and the second data is an input to the ANN, (Fig 9, Item 915) plus “In step 915, the sets of storage volume parameters for the new candidate storage volumes are evaluated by using the machine learning program” Page 7, Paragraph [0061]).
Feeley, Cullen and Bowers are analogous art because they are all directed to advanced methods of operating high-reliability memory based systems. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the memory architecture of Feeley with the voting mechanisms of Cullen and the Machine Learning of Bowers, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to provide higher reliability and more flexible memory capabilities.
Regarding claim 7 –
The combination of Feeley and Cullen teaches all the limitations of claim 1 above.
The combination of Feeley and Cullen does not teach further comprising a cache, wherein the multiple copies are stored in the cache for performing the matching of data.
Bowers, however teaches further comprising a cache, wherein the multiple copies are stored in the cache for performing the matching of the portions of the data, (Fig 2) plus “In another example, a bus system may be used to implement communications fabric 202 and may be comprised of one or more buses, such as a system bus or an input/output bus. Of course, the bus system may be implemented using any suitable type of architecture that provides for a transfer of data between different components or devices attached to the bus system. Additionally, a communications unit may include one or more devices used to transmit and receive data, such as a modem or a network adapter. Further, a memory may be, for example, memory 206 or a cache such as found in an interface and memory Controller hub… “ (Page 3, Paragraph [0033]).
Feeley, Cullen and Bowers are analogous art because they are all directed to advanced methods of operating high-reliability memory based systems. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the memory architecture of Feeley with the voting mechanisms of Cullen and the cache use of Bowers, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to provide higher reliability and more flexible memory capabilities.
Regarding claim 9 –
The combination of Feeley and Cullen teaches all the limitations of claim 1 above.
The combination of Feeley and Cullen does not teach wherein the processing device is further configured to provide the selected copy as output data sent over a bus to a host system.
Bowers, however teaches wherein the processing device is further configured to provide the selected copy as output data sent over a bus to a host system, (Fig 2) plus “In another example, a bus system may be used to implement communications fabric 202 and may be comprised of one or more buses, such as a system bus or an input/output bus. Of course, the bus system may be implemented using any suitable type of architecture that provides for a transfer of data between different components or devices attached to the bus system. Additionally, a communications unit may include one or more devices used to transmit and receive data, such as a modem or a network adapter. Further, a memory may be, for example, memory 206 or a cache such as found in an interface and memory Controller hub… “ (Page 3, Paragraph [0033]).
Feeley, Cullen and Bowers are analogous art because they are all directed to advanced methods of operating high-reliability memory based systems. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the memory architecture of Feeley with the voting mechanisms of Cullen and the host communications of Bowers, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to provide higher reliability and more flexible memory capabilities.
Regarding claim 31 –
The combination of Feeley and Cullen teaches all the limitations of claim 26 above.
The combination of Feeley and Cullen does not teach wherein detecting the event is based on output from an artificial neural network.
Bowers, however teaches wherein detecting the event is based on output from an artificial neural network, (Fig 9, Item 915) plus “In step 915, the sets of storage volume parameters for the new candidate storage volumes are evaluated by using the machine learning program” Page 7, Paragraph [0061]).
Feeley, Cullen and Bowers are analogous art because they are all directed to advanced methods of operating high-reliability memory based systems. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the memory architecture of Feeley with the voting mechanisms of Cullen and the Machine Learning of Bowers, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to provide higher reliability and more flexible memory capabilities.
Claims 23 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent 9110832-(Feeley et al.) [herein “Feeley”], in view of U.S. Patent Publication 20150280919-(Cullen et al.) [herein “Cullen”], and further in view of Non-Patent Literature IEEE-Simevski et al.)-“NMR Voter”-(2012) [herein “IEEE”].
Regarding claim 23 –
The combination of Feeley and Cullen teaches all the limitations of claim 21 above.
The combination of Feeley and Cullen does not teach wherein the at least one processing device is further configured to vary a number of the multiple copies accessed based on a type of the data being accessed.
IEEE, however teaches wherein the at least one processing device is further configured to vary a number of the multiple copies accessed based on a type of the data being accessed, “Here, we present a design method for an NMR voter which along with the voting result, outputs the state of its inputs. It also makes self-checks of the consistency of its operation and signals errors. At last, the voter allows for each of its inputs to be defined whether the input takes part in voting or not i.e., the voter is programmable” (Abstract).
Feeley, Cullen and IEEE are analogous art because they are all directed to advanced methods of operating high-reliability memory based systems. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the memory architecture of Feeley with the voting mechanisms of Cullen and the flexible programmability of IEEE, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to provide higher reliability and more flexible memory capabilities.
Regarding claim 28 –
The combination of Feeley and Cullen teaches all the limitations of claim 27 above.
The combination of Feeley and Cullen does not teach wherein the at least one processing device is further configured to vary a number of the copies accessed based on a type of the data being accessed.
IEEE, however teaches wherein the processing device is further configured to vary a number of the copies accessed based on a type of the data being accessed, “Here, we present a design method for an NMR voter which along with the voting result, outputs the state of its inputs. It also makes self-checks of the consistency of its operation and signals errors. At last, the voter allows for each of its inputs to be defined whether the input takes part in voting or not i.e., the voter is programmable” (Abstract).
Feeley, Cullen and IEEE are analogous art because they are all directed to advanced methods of operating high-reliability memory based systems. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the memory architecture of Feeley with the voting mechanisms of Cullen and the flexible programmability of IEEE, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to provide higher reliability and more flexible memory capabilities.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/M.W.W./Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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