DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant argues that element 44 of Huang is not a wiring layer because it is described as a dielectric. However, the layer is clearly a part of the redistribution layer (140) which includes conductive features (145-147). Applicant argues that Huang’s conductive line 143 is not a via. However, both the wide and narrow portions of element 143 can be broadly interpreted to be a via since they at least partially penetrate the dielectric layer (142). Applicant’s amendments to claims 1 and 12 overcome the current rejection, and therefore new grounds for rejection are set forth below in view of Chen et al. (US Publication No. 2021/0057363). Regarding claim 19, elements 145, 119, 143, and 147 all vertically overlap (Figure 4).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US Publication No. 2019/0164783).
Regarding claim 19, Huang discloses a semiconductor package comprising:
a lower package (1100)
an upper package (160) disposed on the lower package and including an upper semiconductor chip (162), wherein the lower package includes:
a lower redistribution layer (140) including a lower insulating layer (144), a seed pattern (paragraph 25), a lower via (145), and a lower wiring (144)
a lower semiconductor chip (120) on the lower redistribution layer (140)
a core layer (119) surrounding the lower semiconductor chip (120) on the lower redistribution layer (140) and including a core insulating pattern (130), a core via (119), and a core pad (148 pad)
an under bump structure (155) provided on a lower surface of the lower redistribution layer (140) and including an under bump pad (147) and a plurality of under bump vias (143)
an external terminal (155) connected on a lower surface of the under bump pad (147)
a molding layer (130) covering the lower semiconductor chip (120) and the core layer (119) on the lower redistribution layer (140)
an upper redistribution layer (110) connected to the lower redistribution layer (140) through the core layer (119) on the molding layer (130)
wherein the lower via (145), the core via (119), and the plurality of under bump vias (143) are disposed on the under bump pad (147) and vertically overlap the under bump pad (147) (Figure 4)
wherein the lower via (145), the core via (119), and the plurality of under bump vias (143) are not vertically aligned with each other
Regarding claim 20, Huang discloses a diameter of the under bump pad (147) is greater than diameters of the lower via (145), the core via (119), and the plurality of under bump vias (143).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 7-18 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US Publication No. 2019/0164783) in view of Chen et al. (US Publication No. 2021/0057363).
Regarding claim 1, Huang discloses a semiconductor package comprising:
a lower redistribution layer (140) including a lower wiring (144) and a lower via (145)
a core layer (119) on the lower redistribution layer (140) and including a core via (119)
an under bump structure including an under bump pad (147) on a lower surface of the lower redistribution layer (140) and an under bump via (143) connecting the lower wiring (144) and the under bump pad (147)
wherein the under bump pad (147) overlaps the under bump via (143), the lower via (145), and the core via (119) in a plan view
wherein the under bump via (143) is spaced apart from at least one of the lower via (145) and the core via (119) in the plan view
Huang is silent regarding a plurality of under bump vias spaced apart from each other under the bump pad. However, Chen discloses a plurality of under bump vias (vias connected to element 813) spaced apart from each other under the bump pad (809) (Figure 27). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Huang to include multiple under bump vias spaced apart, as taught by Chen, since it can improve thermal conduction and performance of the device (paragraph 79).
Regarding claim 2, Huang discloses a semiconductor chip (120) on the lower redistribution layer (40); and a molding layer (130) on the lower redistribution layer (140) between the core layer (119) and the semiconductor chip (120).
Regarding claim 3, Huang discloses a passivation layer (142) between the lower redistribution layer (140) and the under bump structure; and an external terminal (155) connected to the under bump pad (147).
Regarding claim 4, Huang discloses a width of the lower via (145) of the lower redistribution layer (140) is narrower from a lower surface to an upper surface of the lower via (tapered up vias – Figure 4).
Regarding claim 5, Huang discloses the under bump via (143) overlaps the core via (119), in the plan view.
Regarding claim 7, Huang discloses the plurality of under bump vias (143) and the core via (119) are disposed on the under bump pad (147) and spaced apart from each other at regular intervals (Figure 4, at least two pads are spaced apart at regular intervals).
Regarding claim 8, Huang discloses the lower via (145) and the core via (119) are disposed between the plurality of under bump vias (143) and overlap each other, in the plan view (Figure 4).
Regarding claim 9, Huang discloses the lower via (145), the core via (119), and the plurality of under bump vias (119) are spaced apart from each other, in the plan view (Figure 4).
Regarding claim 10, Huang discloses a diameter of the lower via (145) is smaller than a diameter of the core via (119), and the diameter of the lower via (145) is smaller than a diameter of the under bump via (143)
Regarding claim 11, Huang discloses a combined height of the core via (119), the lower via, and the under bump via is at least 100 um (paragraph 39).
Regarding claim 12, Huang discloses a semiconductor package comprising:
a semiconductor chip (120)
a lower redistribution layer (140) including a lower via (145) and a lower wiring (144) on a lower surface of the semiconductor chip (120)
an upper redistribution layer (1100) on an upper surface of the semiconductor chip (120)
a connection structure (119) connecting between the lower redistribution layer (140) and the upper redistribution layer (1100) and located on a side of the semiconductor chip (120)
an under bump pad (147) on a lower surface of the lower redistribution layer (140)
an under bump via (143) between the lower wiring (144) and the under bump pad (147)
wherein the lower via (145), the connection structure (119), and the under bump via (143) overlap the under bump pad (147), in a plan view
wherein the lower via (145) is spaced apart from the under bump via (143), in the plan view
Huang is silent regarding a plurality of under bump vias spaced apart from each other under the bump pad. However, Chen discloses a plurality of under bump vias (vias connected to element 813) spaced apart from each other under the bump pad (809) (Figure 27). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Huang to include multiple under bump vias spaced apart, as taught by Chen, since it can improve thermal conduction and performance of the device (paragraph 79).
Regarding claim 13, Huang discloses the semiconductor chip (120) is disposed on a center region of the lower redistribution layer (140), on a plane view (Figure 4).
Regarding claim 14, Huang discloses the semiconductor chip (120) includes a chip pad (126), and the chip pad of the semiconductor chip (120) is in direct contact with the lower redistribution layer (140 (Figures 2-4).
Regarding claim 15, Huang discloses bumps (128) between the semiconductor chip (120) and the lower redistribution layer (140) (Figure 2).
Regarding claim 16, Huang discloses the connection structure (119) includes a core insulating pattern (130) and a core via (119), and wherein the core insulating pattern (130) and the core via (119) are spaced apart from the semiconductor chip (120), in the plan view.
Regarding claim 17, Huang discloses the connection structure (119) includes a molding layer (130) and a conductive structure (119) penetrating the molding layer (130), and wherein the molding layer (130) is in contact with the semiconductor chip (120).
Regarding claim 18, Huang discloses the upper redistribution layer (1100) includes an upper via (116) and an upper wiring (163), and wherein the upper via (116) has a width that is narrower from an upper surface to a lower surface of the upper via (paragraph 56).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/N.R.P/ 9/18/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
