DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 07/17/2023,
09/22/2023, 10/23/2023, 01/16/2024, 05/03/2024, 07/10/2024, 11/26/2024, 01/23/2025, 03/27/2025, 06/24/2025, 08/25/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Double Patenting
Statutory Double Patenting Rejection
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 21 and 23 are rejected under 35 U.S.C. 101 as claiming the same invention as that of Claims 1 and 20, respectively of prior U.S. Patent No. 11762050. This is a statutory double patenting rejection. As illustrated in Table 1 below, Examiner notes all elements of instant application Claim 21 are recited in Claim 1 in Patent No. 11762050; likewise all elements of Claim 23 are recited in Claim 20 (Patent No. 11762050). Examiner further notes instant application Claim 21 carries dependency to Claim 1, also included for reference in Table 1. Examiner notes term shown in bold, below in Table 1, Application Claim 1 and Claim 22 contain the phrase “for calibrating portions of the measurement system including a measurement channel”. Examiner asserts the additional phrase simply conveys intended use and does not alter metes and bounds or scope and intent of claim limitations recited in issued patent document.
TABLE 1: Application Claims 21 and 23 compared with Claims 1 and 20 from issued Pat No. 11762050
App. Claim 21 (Claim 1 incl. for reference)
Pat. No. 11762050 Claim 1
CLAIM 1-instant application
A measurement system comprising:
a source unit configured to provide a source signal to a sample, the source unit comprising:
at least one of a voltage source and a current source;
and a memory configured to store a source calibration;
a measurement unit configured to acquire from the sample a measurement signal responsive to the source signal, the measurement unit comprising:
at least one of a voltage measuring unit, a current
measuring unit, and a capacitance measuring unit; and a memory configured to store a measurement calibration;
and a control unit comprising:
a digital signal processing unit;
a source converter connected between the digital signal processing unit and the source unit;
a measurement converter connected between the digital signal processing unit and the measurement unit;
a synchronization unit configured to synchronize clocks of the digital signal processing unit, the source converter, and the measurement converter;
a calibration unit for calibrating the system;
and a reference voltage supply configured to supply a common reference voltage for the control unit for calibrating portions of the measurement system including a measurement channel.
CLAIM 1-PAT No. 11762050
A measurement system comprising:
a source unit configured to provide a source signal to a sample, the source unit comprising:
at least one of a voltage source and a current source;
and a memory configured to store a source calibration;
a measurement unit configured to acquire from the sample a measurement signal responsive to the source signal, the measurement unit comprising:
at least one of a voltage measuring unit, a current measuring unit, and a capacitance measuring unit; and a memory configured to store a measurement calibration;
and a control unit comprising:
a digital signal processing unit;
a source converter connected between the digital signal processing unit and the source unit;
a measurement converter connected between the digital signal processing unit and the measurement unit;
a synchronization unit configured to synchronize clocks of the digital signal processing unit, the source converter, and the measurement converter;
a calibration unit for calibrating the system;
and a reference voltage supply configured to supply a common reference voltage for the control unit,
wherein the control unit is configured to:
calibrate a measurement channel against the common reference voltage;
command the source unit to apply a positive signal in place of the source signal;
measure, via the calibrated measurement channel, the commanded positive signal to yield a measured positive signal;
command the source unit to apply a negative signal in place of the source signal;
measure, via the calibrated measurement channel, the applied negative signal to yield a measured negative signal;
command the source unit to apply a zero signal in place of the source signal;
measure, via the calibrated measurement channel, the applied zero signal to yield a measured zero signal;
and generate a source unit calibration based on a difference between a first signal and a second signal,
wherein: the first signal comprises at least one of the commanded positive signal, the commanded negative signal, and the commanded zero signal;
and the second signal comprises at least one of the measured positive signal, the measured negative signal, and the measured zero signal.
CLAIM 21: The system of claim 1,
wherein the control unit is configured to:
calibrate the measurement channel against the common reference voltage;
command the source unit to apply a positive signal in place of the source signal;
measure, via the calibrated measurement channel, the commanded positive signal to yield a measured positive signal;
command the source unit to apply a negative signal in place of the source signal;
measure, via the calibrated measurement channel, the applied negative signal to yield a measured negative signal;
command the source unit to apply a zero signal in place of the source signal;
measure, via the calibrated measurement channel, the applied zero signal to yield a measured zero signal;
and generate a source unit calibration based on a difference between a first signal and a second signal,
wherein: the first signal comprises at least one of the commanded positive signal, the commanded negative signal, and the commanded zero signal;
and the second signal comprises at least one of the measured positive signal, the measured negative signal, and the measured zero signal.
App. Claim 23 (Claim 22 incl. for ref.)
Issue Pat No. 11762050 Claim 20
Instant App, Claim 22 - A method comprising:
providing a source signal to a sample via a source unit comprising:
at least one of a voltage source and a current source;
a memory configured to store a source calibration;
acquiring from the sample a measurement signal responsive to the source signal via a measurement unit,
the measurement unit comprising:
at least one of a voltage measuring unit, a current
measuring unit, and a capacitance measuring unit;
a memory configured to store a measurement calibration;
and receiving the measurement signal from the
measurement unit by a control unit,
the control unit comprising:
a digital signal processing unit; a source converter connected between the digital signal processing unit and the source unit;
a measurement converter connected between the digital signal processing unit and the measurement unit;
a synchronization unit configured to synchronize clocks of the digital signal processing unit, the source converter, and the measurement converter;
a calibration unit for calibrating aspects of the system including the control unit;
and a reference voltage supply configured to supply a common reference voltage for the control unit
for calibrating portions of the measurement
system including a measurement channel.
Instant App, Claim 23
The method of claim 22 further comprising:
calibrating, via the control unit, the measurement channel against the common reference voltage;
commanding, via the control unit, the source unit to apply a positive signal in place of the source signal;
measuring, via the calibrated measurement channel, the commanded positive signal to yield a measured positive signal;
commanding, via the control unit, the source unit to apply a negative signal in place of the source signal;
measuring, via the calibrated measurement channel, the applied negative signal to yield a measured negative signal;
commanding, via the control unit, the source unit to apply a zero signal in place of the source signal;
measuring, via the calibrated measurement channel, the applied zero signal to yield a measured zero signal; and generating, via the control unit, a source unit calibration based on a difference between a first signal and a second signal,
wherein: the first signal comprises at least one of the commanded positive signal, the commanded negative signal, and the commanded zero signal;
and the second signal comprises at least one of the measured positive signal, the measured negative signal, and the measured zero signal.
A method comprising:
providing a source signal to a sample via a source unit
comprising:
at least one of a voltage source and a current source;
a memory configured to store a source calibration;
acquiring from the sample a measurement signal responsive to the source signal via a measurement unit,
the measurement unit comprising:
at least one of a voltage measuring unit, a current measuring unit, and a capacitance measuring unit;
a memory configured to store a measurement calibration; and receiving the measurement signal from the measurement unit by a control unit,
the control unit comprising:
a digital signal processing unit; a source converter connected between the digital signal processing unit and the source unit;
a measurement converter connected between the digital signal processing unit and the measurement unit;
a synchronization unit configured to synchronize clocks of the digital signal processing unit, the source converter, and the measurement converter;
a calibration unit for calibrating aspects of the system including the control unit;
and a reference voltage supply configured to supply a common reference voltage for the control unit;
calibrating, via the control unit, a measurement channel against the common reference voltage;
commanding, via the control unit, the source unit to apply a positive signal in place of the source signal;
measuring, via the calibrated measurement channel, the commanded positive signal to yield a measured positive signal;
commanding, via the control unit, the source unit to apply a negative signal in place of the source signal;
measuring, via the calibrated measurement channel, the applied negative signal to yield a measured negative signal;
commanding, via the control unit, the source unit to apply a zero signal in place of the source signal;
measuring, via the calibrated measurement channel, the applied zero signal to yield a measured zero signal; and generating, via the control unit, a source unit calibration based on a difference between a first signal and a second signal,
wherein: the first signal comprises at least one of the commanded positive signal, the commanded negative signal, and the commanded zero signal;
and the second signal comprises at least one of the measured positive signal, the measured negative signal, and the measured zero signal.
Nonstatutory Double Patenting Rejection
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20, and 22 rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1-20 of U.S. Patent No. 1176205. Although the claims at issue are not identical, they are not patentably distinct from each other because all elements recited in application claims 1-20 and 22 are recited in patented invention. Examiner points to Table 2, below for claim-to-claim analysis used for the follow rationale supporting nonstatutory double patenting rejection:
Pointing to language emphasized in bold (column 2), Claim 1 in issued Patent 11762050 recites additional language not recited in Application Claim 1. However, the additional language recited in issued Patent claim 1 is recited in application Claim 21, as discussed above.
Pointing to term emphasized in bold (column 1), Application Claim 1 includes the language “for calibrating portions of the measurement system including a measurement channel” which is not recited in issued Patent Claim 1. However, as noted above, this language is deemed to be direction at intended use, and thus does not change metes and bounds, nor scope or intent of the recited limitations when compared with issued Patent Claim 1.
Examiner notes comparison of language recited in Application Claims 2-17 is identical claim-to-claim when compared with language in issued Patent Claims 2-17.
Pointing to term emphasized in bold in issued Patent Claim 18 (Column 2), recited as “and a configurable display that is configured to display at least one of: real time oscilloscope readings; and frequency spectrum readings” is additional language not included in Application Claim 18. However, Examiner notes the limitation is recited in Application Claim 19, as emphasized in bold (column 1). Application Claims 18 and 19 carry dependency to Claim 1, as does issued patent Claim 18.
Pointing to Application Claim 22, term emphasized in bold (column 1), “for calibrating portions of the measurement system including a measurement channel” is not recited in issued Patent Claim 22. However, as noted above, this language is deemed to be directed at intended use, and thus does not change metes and bounds, nor scope and intent of limitations recited in issued Patent Claim 22, which recites all other language recited in Application Claim 22.
Examiner points to language in issued Patent Claim 20, emphasized in bold (Column 2), where language is recited in Application Claim 23, as noted above.
Table 2: Claim-to-claim comparison analysis for nonstatutory double patenting rejection
Instant App.18/353,425
Claims patented U.S. Pat 11762050
Claim 1: A measurement system comprising:
a source unit configured to provide a source signal to a sample, the source unit comprising:
at least one of a voltage source and a current source;
and a memory configured to store a source calibration;
a measurement unit configured to acquire from the sample a measurement signal responsive to the source signal, the measurement unit comprising:
at least one of a voltage measuring unit, a current measuring unit, and a capacitance measuring unit;
and a memory configured to store a measurement calibration;
and a control unit comprising:
a digital signal processing unit;
a source converter connected between the digital signal
processing unit and the source unit;
a measurement converter connected between the digital signal processing unit and the measurement unit;
a synchronization unit configured to synchronize clocks of the digital signal processing unit, the source converter, and the measurement converter;
a calibration unit for calibrating the system;
and a reference voltage supply configured to supply a
common reference voltage for the control unit
for calibrating portions of the measurement
system including a measurement channel.
Claim 1: A measurement system comprising:
a source unit configured to provide a source signal to a sample, the source unit comprising:
at least one of a voltage source and a current source;
and a memory configured to store a source calibration;
a measurement unit configured to acquire from the sample a measurement signal responsive to the source signal, the measurement unit comprising:
at least one of a voltage measuring unit, a current measuring unit, and a capacitance measuring unit;
and a memory configured to store a measurement calibration;
and a control unit comprising:
a digital signal processing unit;
a source converter connected between the digital signal
processing unit and the source unit;
a measurement converter connected between the digital
signal processing unit and the measurement unit;
a synchronization unit configured to synchronize clocks
of the digital signal processing unit, the source converter, and the measurement converter;
a calibration unit for calibrating the system;
and a reference voltage supply configured to supply a
common reference voltage for the control unit,
wherein the control unit is configured to:
calibrate a measurement channel against the common reference voltage;
command the source unit to apply a positive signal in place of the source signal;
measure, via the calibrated measurement channel, the commanded positive signal to yield a measured positive signal;
command the source unit to apply a negative signal in place of the source signal; measure, via the calibrated measurement channel, the applied negative signal to yield a measured negative signal;
command the source unit to apply a zero signal in place of the source signal;
measure, via the calibrated measurement channel, the applied zero signal to yield a measured zero signal;
and generate a source unit calibration based on a difference between a first signal and a second signal,
wherein: the first signal comprises at least one of the
commanded positive signal, the commanded negative signal, and the commanded zero signal;
and the second signal comprises at least one of the measured positive signal, the measured negative signal, and the measured zero signal.
Claim 2: The system of claim 1,
wherein the control unit is configured to obtain at least one of:
calibration data from a self-calibration performed by the source unit and the measurement unit;
calibration data from a stored factory calibration;
calibration data from a remote source via the Internet;
calibration data from a user input;
the source calibration data from the source unit;
and the measurement calibration data from the measurement unit.
Claim 2: The system of claim 1,
wherein the control unit is configured to obtain at least one of:
calibration data from a self-calibration performed by the source unit and the measurement unit;
calibration data from a stored factory calibration;
calibration data from a remote source via the Internet;
calibration data from a user input;
the source calibration data from the source unit;
and the measurement calibration data from the measurement unit.
Claim 3: The system of claim 1,
wherein the control unit is configured to obtain at least one of:
the source calibration and the measurement calibration periodically;
the source calibration from the memory of the source unit after the source unit is controlled not to provide the source signal to the sample;
the measurement calibration from the memory of the measurement unit after the measurement unit is controlled not to acquire a measurement signal from the sample;
and the source calibration and the measurement calibration concurrently.
Claim 3: The system of claim 1,
wherein the control unit is configured to obtain at least one of:
the source calibration and the measurement calibration periodically;
the source calibration from the memory of the source unit after the source unit is controlled not to provide the source signal to the sample;
the measurement calibration from the memory of the
measurement unit after the measurement unit is controlled not to acquire a measurement signal from the sample;
and the source calibration and the measurement calibration concurrently.
Claim 4: The system of claim 1,
wherein at least one of:
the digital signal processing unit stores calibration data for at least one of the control unit, the source unit, and the measurement unit;
the measurement and the source units are remotely located from the control unit and the digital signal processing unit;
the system comprises a first cable connecting the control unit to the measurement unit and a second cable connecting the control unit to the source unit;
digital signals in at least one of the measurement unit and the source unit are isolated from the control unit;
a measurement interface between the measurement unit and the control unit and a source interface between the source unit and the control unit are isolated from one another within a cable;
the system comprises a plurality of source units;
the system comprises a plurality of measurement units;
the source unit is configured to acquire the measurement signal;
and the measurement unit is configured to provide the source signal.
Claim 4: The system of claim 1,
wherein at least one of:
the digital signal processing unit stores calibration data for at least one of the control unit, the source unit, and the measurement unit;
the measurement and the source units are remotely located from the control unit and the digital signal processing unit;
the system comprises a first cable connecting the control unit to the measurement unit and a second cable connecting the control unit to the source unit;
digital signals in at least one of the measurement unit and the source unit are isolated from the control unit;
a measurement interface between the measurement unit and the control unit and a source interface between the source unit and the control unit are isolated from one another within a cable;
the system comprises a plurality of source units;
the system comprises a plurality of measurement units;
the source unit is configured to acquire the measurement signal;
and the measurement unit is configured to provide the source signal.
Claim 5: The system of claim 1,
wherein the current source is configured to measure a source current associated with the source signal via a sensing resistor and vary a resistance range of the sensing resistor according to a magnitude of the source current.
Claim 5: The system of claim 1,
wherein the current source is configured to measure a source current associated with the source signal via a sensing resistor and vary a resistance range of the sensing resistor according to a magnitude of the source current.
Claim 6: The system of claim 5,
further comprising at least one of:
a current source protection unit configured to determine whether the source current exceeds a threshold current and when the source current exceeds the threshold current, alter a feedback element of at least one of the source unit and the measurement unit so that the source current falls below the threshold current;
and a voltage source protection unit configured to determine whether a source voltage exceeds a threshold voltage and when the source voltage exceeds the threshold voltage, alter a feedback element of at least one of the source unit and the measurement unit so that the source voltage falls below the threshold voltage.
Claim 6: The system of claim 5,
further comprising at least one of:
a current source protection unit configured to determine whether the source current exceeds a threshold current and when the source current exceeds the threshold current, alter a feedback element of at least one of the source unit and the measurement unit so that the source current falls below the threshold current;
and a voltage source protection unit configured to determine whether a source voltage exceeds a threshold voltage and when the source voltage exceeds the threshold voltage, alter a feedback element of at least one of the source unit and the measurement unit so that the source voltage falls below the threshold voltage.
Claim 7: The system of claim 1,
wherein the synchronization unit is configured to synchronize the digital signal processing unit, the source converter, and the measurement converter with respect to an internal clock signal.
Claim 7: The system of claim 1,
wherein the synchronization unit is configured to synchronize the digital signal processing unit, the source converter, and the measurement converter with respect to an internal clock signal.
Claim 8: The system of claim 1,
wherein the digital signal processing unit is configured to provide timestamps for at least one of the measurement signal and the source signal.
Claim 8: The system of claim 1,
The system of claim 1, wherein the digital signal processing unit is configured to provide timestamps for at least one of the measurement signal and the source signal.
Claim 9: The system of claim 1,
wherein at least one of: the source unit is configured to deactivate non-analog circuitry in response to the source signal being provided;
and the measurement unit is configured to deactivate non-analog circuitry in response to the measurement signal being measured.
Claim 9: The system of claim 1,
wherein at least one of: the source unit is configured to
deactivate non-analog circuitry in response to the source signal being provided;
and the measurement unit is configured to deactivate non
analog circuitry in response to the measurement signal being measured.
Claim 10: The system of claim 1,
wherein the digital signal processing unit is configured to perform at least one of the following with respect to at least one of the measurement and the source signal:
a lock-in analysis;
an Alternating Current/Direct Current (AC/DC) measurement;
an inductance (L), a capacitance (C), and a resistance (R) (LCR) measurement;
a time/scope domain presentation;
a frequency domain analysis;
a noise analysis;
an AC/DC sourcing;
a control looping;
and providing the source signal from more than one source.
Claim 10: The system of claim 1,
wherein the digital signal processing unit is configured to perform at least one of the following with respect to at least one of the measurement and the source signal:
a lock-in analysis;
an Alternating Current/Direct Current (AC/DC)
measurement;
an inductance (L), a capacitance (C), and a resistance (R) (LCR) measurement;
a time/scope domain presentation;
a frequency domain analysis;
a noise analysis;
an AC/DC sourcing;
a control looping;
and providing the source signal from more than one source.
Claim 11: The system of claim 1,
comprising at least one of:
an interface between the source unit and the control unit comprising low impedance buffered analog signals;
an interface between the measurement unit and the control unit comprising a voltage mode analog signal interface with low impedance transmitting and high impedance receiving circuitry;
and an interface between the measurement unit and the control unit comprising a current mode analog signal interface with high output impedance transmitting and low impedance receiving circuitry.
Claim 11: The system of claim 1,
comprising at least one of:
an interface between the source unit and the control unit comprising low impedance buffered analog signals;
an interface between the measurement unit and the
control unit comprising a voltage mode analog signal interface with low impedance transmitting and high impedance receiving circuitry;
and an interface between the measurement unit and the control unit comprising a current mode analog signal interface with high output impedance transmitting and low impedance receiving circuitry
Claim 12: The system of claim 1,
wherein at least one of:
the system comprises a power supply is configured to
supply power to the control unit, the source unit, and
the measurement unit referenced to a common
ground;
the system comprises a power supply filter to at least one of the measurement unit and the source unit;
and at least one of the measurement unit and the source unit is powered from at least one of an isolated power converter from the control unit, an isolated external power source, and battery power.
Claim 12: The system of claim 1,
wherein at least one of:
the system comprises a power supply is configured to supply power to the control unit, the source unit, and the measurement unit referenced to a common ground;
the system comprises a power supply filter to at least one of the measurement unit and the source unit;
and at least one of the measurement unit and the source unit is powered from at least one of an isolated power converter from the control unit, an isolated external power source, and battery power
Claim 13: The system of claim 1,
wherein at least one of the source converter and the measurement converter comprises:
a gain chain configured to amplify an analog input signal;
a range selector configured to select a gain between the analog input signal and the multiple analog-to-digital converter (ADC) outputs,
wherein each ADC output has a path, and a gain of each output path is made up of gain stages in the gain chain;
and a mixer configured to combine the multiple ADC outputs into a single mixed output.
Claim 13: The system of claim 1,
wherein at least one of the source converter and the measurement converter comprises:
a gain chain configured to amplify an analog input signal;
a range selector configured to select a gain between the analog input signal and the multiple analog-to-digital converter (ADC) outputs,
wherein each ADC output has a path, and a gain of each output path is made up of gain stages in the gain chain;
and a mixer configured to combine the multiple ADC outputs into a single mixed output.
Claim 14: The system of claim 1,
wherein the source converter comprises:
two or more digital-to-analog converters (DAC) combined to generate one or more frequency components;
a first path for generating low frequency signals, the first path comprising a first one of the DACs;
a second path for generating high frequency signals, the second path comprising a second one of the DACs;
a data processor for processing an input signal;
a combining circuit configured to combine outputs of the first path and the second path into the source signal;
a feedback portion configured to sense the source signal; and a servo loop configured to employ the feedback portion to maintain the source signal with respect to the input signal.
Claim 14: The system of claim 1,
wherein the source converter comprises:
two or more digital-to-analog converters (DAC) combined to generate one or more frequency components;
a first path for generating low frequency signals, the first path comprising a first one of the DACs;
a second path for generating high frequency signals, the second path comprising a second one of the DACs;
a data processor for processing an input signal;
a combining circuit configured to combine outputs of the first path and the second path into the source signal;
a feedback portion configured to sense the source signal;
and a servo loop configured to employ the feedback portion to maintain the source signal with respect to the input signal.
Claim 15: The system of claim 1,
wherein the digital signal processing unit is configured to perform lock-in signal processing and wherein the lock-in signal processing unit is configured to at least one of:
be synchronized with the synchronization unit;
process at least one of a fundamental frequency and a harmonic frequency;
and provide a lock-in reference for communication between the control unit and at least one of the source unit and the measurement unit.
Claim 15: The system of claim 1,
wherein the digital signal processing unit is configured to perform lock-in signal processing and wherein the lock-in signal processing unit is configured to at least one of:
be synchronized with the synchronization unit;
process at least one of a fundamental frequency and a harmonic frequency;
and provide a lock-in reference for communication between the control unit and at least one of the source unit and the measurement unit.
Claim 16: The system of claim 1,
wherein the control unit is configured to measure a parameter of the source signal using a feedback signal that is one of a DC signal and a low frequency AC signal.
Claim 16: The system of claim 1,
wherein the control unit is configured to measure a parameter of the source signal using a feedback signal that is one of a DC signal and a low frequency AC signal.
Claim 17: The system of claim 1,
wherein the control unit is configured to assess a type of at least one of the measurement unit and the source unit and configure the digital signal processing unit according to the type.
Claim 17: The system of claim 1,
wherein the control unit is configured to assess a type of at least one of the measurement unit and the source unit and configure the digital signal processing unit according to the type.
Claim 18: The system of claim 1,
further comprising
an enclosure for at least one of the source unit and the measurement unit, the enclosure comprising at least one of electrostatic shielding and magnetic shielding.
Claim 18: The system of claim 1,
further comprising at least one of:
an enclosure for at least one of the source unit and the measurement unit, the enclosure comprising at least one of electrostatic shielding and magnetic shielding;
and a configurable display that is configured to display at least one of: real time oscilloscope readings; and frequency spectrum readings.
Claim 19: The system of claim 1,
further comprising
a configurable display that is configured to display at least one of: real time oscilloscope readings; and frequency spectrum readings.
Claim 20: The system of claim 1,
wherein the control unit is configured to perform at least one of:
a voltage measure mode calibration for a measurement unit by:
measuring an offset error at the measurement unit;
storing the offset error in the memory of the measurement unit;
connecting an amplifier associated with the measurement unit to a reference voltage; measuring, via the control unit, a gain error from applying the reference voltage to the amplifier;
storing the measured gain error in the memory of the measurement unit;
reading, via the control unit, at least one of the stored gain error from the memory of the measurement unit;
and applying at least one of the offset error and the gain error to correct a voltage measurement;
and a current mode measure calibration for the
measurement unit by:
disconnecting input connectors of the control unit;
connecting input connectors of the measurement unit to ground;
configuring the measurement unit in a voltage measure mode;
measuring voltage offset errors of an amplifier via the measurement unit in voltage measure mode;
applying an analog correction to decrease the measured voltage offset errors;
switching the measurement unit to a current measure mode and floating inputs to the measurement unit;
determining, via the control unit, voltage offset errors between the measurement unit and the control unit by configuring the measurement unit in a high current range and measuring a resultant voltage at the control unit;
adjusting a leakage current until a current measurement of the measurement unit is decreased;
storing, via the control unit, at least one of the adjusted leakage current and the voltage offset errors in the memory of the measurement unit;
reading, via the control unit, at least one of the adjusted leakage current and the voltage offset errors;
and applying at least one of the adjusted leakage current and the voltage offset errors to correct a current measurement of the measurement unit.
Claim 19: The system of claim 1,
wherein the control unit is configured to perform at least one of:
a voltage measure mode calibration for a measurement unit by:
measuring an offset error at the measurement unit;
storing the offset error in the memory of the measurement unit;
connecting an amplifier associated with the measurement unit to a reference voltage; measuring, via the control unit, a gain error from applying the reference voltage to the amplifier;
storing the measured gain error in the memory of the measurement unit;
reading, via the control unit, at least one of the stored gain error from the memory of the measurement unit;
and applying at least one of the offset error and the gain error to correct a voltage measurement;
and a current mode measure calibration for the
measurement unit by:
disconnecting input connectors of the control unit;
connecting input connectors of the measurement unit to ground;
configuring the measurement unit in a voltage measure mode;
measuring voltage offset errors of an amplifier via the measurement unit in voltage measure mode;
applying an analog correction to decrease the measured voltage offset errors;
switching the measurement unit to a current measure mode and floating inputs to the measurement unit;
determining, via the control unit, voltage offset errors between the measurement unit and the control unit by configuring the measurement unit in a high current range and measuring a resultant voltage at the control unit;
adjusting a leakage current until a current measurement of the measurement unit is decreased;
storing, via the control unit, at least one of the adjusted leakage current and the voltage offset errors in the memory of the measurement unit;
reading, via the control unit, at least one of the adjusted leakage current and the voltage offset errors;
and applying at least one of the adjusted leakage current and the voltage offset errors to correct a current measurement of the measurement unit.
Claim 22: A method comprising:
providing a source signal to a sample via a source unit comprising:
at least one of a voltage source and a current source;
a memory configured to store a source calibration; acquiring from the sample a measurement signal responsive to the source signal via a measurement unit,
the measurement unit comprising:
at least one of a voltage measuring unit, a current measuring unit, and a capacitance measuring unit;
a memory configured to store a measurement calibration;
and receiving the measurement signal from the
measurement unit by a control unit,
the control unit comprising:
a digital signal processing unit;
a source converter connected between the digital signal processing unit and the source unit;
a measurement converter connected between the digital signal processing unit and the measurement unit;
a synchronization unit configured to synchronize clocks of the digital signal processing unit, the source converter, and the measurement converter;
a calibration unit for calibrating aspects of the system including the control unit; and a reference voltage supply configured to supply a common reference voltage for the control unit for calibrating portions of the measurement system including a measurement channel.
Claim 20: A method comprising:
providing a source signal to a sample via a source unit comprising:
at least one of a voltage source and a current source;
a memory configured to store a source calibration; acquiring from the sample a measurement signal responsive to the source signal via a measurement unit,
the measurement unit comprising:
at least one of a voltage measuring unit, a current measuring unit, and a capacitance measuring unit;
a memory configured to store a measurement calibration;
and receiving the measurement signal from the measurement unit by a control unit,
the control unit comprising:
a digital signal processing unit;
a source converter connected between the digital signal processing unit and the source unit;
a measurement converter connected between the digital signal processing unit and the measurement unit;
a synchronization unit configured to synchronize clocks of the digital signal processing unit, the source converter, and the measurement converter;
a calibration unit for calibrating aspects of the system including the control unit; and a reference voltage supply configured to supply a common reference voltage for the control unit;
calibrating, via the control unit, a measurement channel against the common reference voltage;
commanding, via the control unit, the source unit to apply a positive signal in place of the source signal;
measuring, via the calibrated measurement channel, the commanded positive signal to yield a measured positive signal;
commanding, via the control unit, the source unit to apply a negative signal in place of the source signal;
measuring, via the calibrated measurement channel, the applied negative signal to yield a measured negative signal;
commanding, via the control unit, the source unit to apply a zero signal in place of the source signal;
measuring, via the calibrated measurement channel, the applied zero signal to yield a measured zero signal;
and generating, via the control unit, a source unit calibration based on a difference between a first signal and a second signal, wherein:
the first signal comprises at least one of the commanded positive signal, the commanded negative signal, and the commanded zero signal;
and the second signal comprises at least one of the measured positive signal, the measured negative signal, and the measured zero signal.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 and 22 recite “at least one of a voltage source and a current source” and “at least one of a voltage measuring unit, a current measuring unit, and a capacitance measuring unit”. It is unclear from the claim language whether the claim requires at least one each of a voltage source and a current source and at least one each of a voltage measuring unit, a current measuring unit, and a capacitance measuring unit, or if the claim requires at least one of a voltage source or a current source and at least one of a voltage measuring unit, a current measuring unit, or a capacitance measuring unit. For purposes of examination, the second interpretation with or will be used. Dependent claims 2-21 and 23 are similarly rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Examiner notes application of guidance found in MPEP 2141 in determination of obviousness under 35 U.S.C. 103. Specifically, factual inquiry steps described in 2141 (II): “An invention that would have been obvious to a person of ordinary skill at the relevant time is not patentable. See 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a). As reiterated by the Supreme Court in KSR, the framework for the objective analysis for determining obviousness under 35 U.S.C. 103 is stated in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966). Obviousness is a question of law based on underlying factual inquiries.” Further, the following steps for factual inquiries were used in evaluation of prior art used for obviousness rejection:
(A) Determining the scope and content of the prior art;
(B) Ascertaining the differences between the claimed invention and the prior art; and
(C) Resolving the level of ordinary skill in the pertinent art.
Claims 1-4, 7-8, 10-12, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over WITT (US 9575105 B1) in view of PASSERINI (US 20130033947 A1).
With respect to Claim 1, WITT teaches:
A measurement system
(See WITT, Abstract: “invention enable low-power accurate measurement of complex impedance at a range of frequencies of interest to determine a frequency response of a test sample”; and refer to FIG.3: “schematic of an exemplary system”)
comprising: a source unit configured to provide a source signal to a sample,
(WITT teaches a source unit, refer to FIG. 3, element 210; and refer to FIG. 2, with description of components/function in Col. 3, lines 50-: “digital representation of an AC excitation 202…provides a stimulus to digital-to-analog converter (DAC) 204, DC blocking capacitor 206, sample under test (DUT) 210”),
the source unit comprising: at least one of a voltage source;
(WITT teaches voltage source to sample under test, refer to FIG. 3, Col. 5, lines 22-24: “sinusoidal voltage x(t)=cos(2πFc.Math.t) is applied to test load 210”; and teaches current source)
and a memory configured to store a source calibration;
(WITT teaches use of standard computational components used in a measurement system, see, for example, voltage source to sample under test, refer to FIG. 3, with Col4,lines42-43, “FIG. 3, circuit 300 comprises memory”)
a measurement unit configured to acquire from the sample a measurement signal responsive to the source signal,
(WITT teaches measurement unit, refer to FIG. 3, element 226; teaches acquiring data from sample, FIG. 3, element 226; with a signal in response to source applied, see FIG. 3, with Col3,lines65-66, “signal is passed through sample under test 210”)
the measurement unit comprising: at least one of a voltage measuring unit, a current measuring unit, and a capacitance measuring unit;
(WITT teaches at least a voltage measuring unit, refer to FIG.3, with Col3,lin67-Col4,lines 1-5: “signal is selectively input into sample under test 210 in a measurement path….operational amplifier circuit 220”; Examiner notes one of ordinary skill would identify this description of a measurements circuit.)
and a memory configured to store a measurement calibration;
(See reference above for memory component, “FIG. 3, circuit 300 comprises memory”)
and a control unit comprising:
(WITT teaches a control unit circuitry, refer to FIG. 3, with elements 204, 230, 350, 352, 354, and 360 forming a control circuitry for measurement system.)
a digital signal processing unit;
(WITT teaches digital signal processing, refer to FIG. 3, element 360, label “DIGITAL SIGNAL PROCESSING MODULE”);
a source converter connected between the digital signal processing unit and the source unit;
(WITT depicts source converter, see FIG. 3, element 204, situated in FIG. 3 between digital signal processing unit (element 360) and source unit (element 302).)
a measurement converter connected between the digital signal processing unit and the measurement unit;
(WITT depicts measurement converter in FIG. 3, element 230, situated as shown in FIG. 3 between digital signal procession module and a measurements unit.)
a synchronization unit configured to synchronize clocks of the digital signal processing unit, the source converter, and the measurement converter;
(WITT depicts synchronization unit in FIG. 3, element 354, a digital signal processing unit as above, element 360, and source converter element 204, along with measurement converter element 230; with configuration of synchronization unit described in Col5,lines10-13: “clock ensures that control signals 356, 358 synchronize the digital waveform generation by DAC 204 with the data collection and the sampling process by ADC 230”, followed by more detailed description of synchronization process in Col5,lines14-41; )
a calibration unit for calibrating the system;
(WITT teaches calibration unit, see Col2,lines 12-14: “Circuit responses of the testing circuit combined with measurements on a known calibration channel allow for the determination of the complex impedance”; and see Col4,lines62-64: “waveform is compensated, for example, by a pre-distortion calibration”; WITT teaches calibration as part of control system, refer to FIG.3.).
for calibrating portions of the measurement system including a measurement channel.
(As above, WITT teaches these components integrated into a measurements system in FIG. 3; Examiner notes interpretation of claim limitation language of “measurement channel” to be analogous to reference language of “measurement path”)
However, WITT is silent to the language of:
and a current source
a reference voltage supply configured to supply a common reference voltage for the control unit
Nevertheless, PASSERINI teaches:
and a current source
(PASSERINI is in same technical area, teaching clocks applied to a measurement system, see [0005]: “during a testing phase of an electronic device, it is often required to configure the clock period or clock phase among a range of possible values”; teaches use of a current source, refer to FIG. 3A and [0044] “reference bias generator G1 to produce a substantially constant current”)
a reference voltage supply configured to supply a common reference voltage for the control unit
(PASSERINI teaches use of reference voltage, see clocks applied to a measurement system, see Fig. 3A with [0043]: “master oscillator 110 comprises a first or left module 310 and a second or right module 320 and is connected to a common voltage reference Vref.”, i.e. provides common reference voltage”)
It would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to modify WITT to include a current source and a reference voltage supply as part of a measurement system, such as that of PASSERINI.
One of ordinary skill would be motivated to modify WITT to include a current source and a reference voltage supply as part of a measurement system, as taught by PASSERINI because it would be understood as an obvious way to expand and enhance overall functionality and sample diversity for an integrated measurements system. One of ordinary skill would know the importance of including a reference voltage in a system designed for accurate electrical measurements so that the reliability of any result would be improved.
With respect to Claim 2, WITT, in view of PASSERINI, teaches:
The system of claim 1,
(See as above, references as applied to Claim 1.)
WITT further teaches:
wherein the control unit is configured to obtain at least one of:
calibration data from a self-calibration performed by the source unit and the measurement unit; calibration data from a stored factory calibration; calibration data from a remote source via the Internet; calibration data from a user input; the source calibration data from the source unit; and the measurement calibration data from the measurement unit.
(See as above, WITT teaches use of calibration data; WITT further teaches at least calibration data obtained from source unit, refer to FIG. 3 with Col4,lines 50-65.)
With respect to Claim 3, WITT, in view of PASSERINI, teaches:
The system of claim 1,
(See as above, references as applied to Claim 1.)
WITT further teaches:
wherein the control unit is configured to obtain at least one of: the source calibration and the measurement calibration periodically; the source calibration from the memory of the source unit after the source unit is controlled not to provide the source signal to the sample; the measurement calibration from the memory of the measurement unit after the measurement unit is controlled not to acquire a measurement signal from the sample; and
the source calibration and the measurement calibration concurrently.
(WITT teaches at least obtaining calibration data from a source unit, refer to Fig 3 with Col. 4, Lines 50-65; and see Col5,lines10-21).
With respect to Claim 4, WITT, in view of PASSERINI, teaches:
The system of claim 1,
(See as above, references as applied to Claim 1.)
WITT further teaches:
wherein at least one of: the digital signal processing unit stores calibration data for at least one of the control unit, the source unit, and the measurement unit; the measurement and the source units are remotely located from the control unit and the digital signal processing unit; the system comprises a first cable connecting the control unit to the measurement unit and a second cable connecting the control unit to the source unit; digital signals in at least one of the measurement unit and the source unit are isolated from the control unit; a measurement interface between the measurement unit and the control unit and a source interface between the source unit and the control unit are isolated from one another within a cable; the system comprises a plurality of source units; the system comprises a plurality of measurement units; the source unit is configured to acquire the measurement signal; and the measurement unit is configured to provide the source signal.
(WITT teaches at least measurement and the source units are remotely located, refer to FIG. 3, depicting measurement unit and source unit located separate from other elements analogous to claim limitation language, including, elements 350, 352, 354, and 360, forming control until circuitry.)
With respect to Claim 7, WITT, in view of PASSERINI, teaches:
The system of claim 1,
(See as above, references as applied to Claim 1.)
WITT further teaches:
wherein the synchronization unit is configured to synchronize the digital signal processing unit, the source converter, and the measurement converter with respect to an internal clock signal.
(WITT teaches synchronization unit, as noted above, refer FIG.3, element 354 connected with digital signal process unit, element 360, source converter element 204 and measurement converter element 230; with synchronization function described in Col5,lines10-13, as above, and lines28-32: “Digital Baseband Quadrature Sampling (BQS), which is a digital down-conversion to DC, is implemented to synchronize ADC sampling with AC waveform generation”)
With respect to Claim 8, WITT, in view of PASSERINI, teaches:
The system of claim 1,
(See as above, references as applied to Claim 1.)
WITT further teaches:
wherein the digital signal processing unit is configured to provide timestamps for at least one of the measurement signal and the source signal.
(WITT teaches digital signal processing unit, see FIG.2,element 360, as noted above; with function including timestamping in Col4,lines66–Col5,line 9: “Timing control logic 354 comprises a timing generator that generates a clock signal 366…also generates control signals that control both DAC 204 and ADC 230. In response to clock signal 366, control signals 356 cause DAC 204 to start a digital-to-analog conversion that generates the waveform data at an output rate of Fc/N. Simultaneously, or with some time delay, ADC 230 collects data at a sample rate of Fc/4.”).
With respect to Claim 10, WITT, in view of PASSERINI, teaches:
The system of claim 1,
(See as above, references as applied to Claim 1.)
WITT further teaches:
wherein the digital signal processing unit is configured to perform at least one of the following with respect to at least one of the measurement and the source signal: a lock-in analysis; an Alternating Current/Direct Current (AC/DC) measurement; an inductance (L), a capacitance (C), and a resistance (R) (LCR) measurement; a time/scope domain presentation; a frequency domain analysis; a noise analysis; an AC/DC sourcing; a control looping; and providing the source signal from more than one source.
(WITT teaches use of digital signal processing unit, as above, FIG.3,element360; and teaches at least performing an alternating current/direct current (AC/DC) measurement with respect to source signal, see Col5,lines22-41: “a sinusoidal voltage x(t)=cos(2πFc.Math.t) is applied to test load 210. Signal 228 y(t)=V.sub.L cos(2πFc.Math.t+θ) received by ADC 230 is a scaled and phase shifted version of input signal 207…Digital Baseband Quadrature Sampling (BQS), which is a digital down-conversion to DC, is implemented to synchronize ADC sampling with AC waveform generation…ADC 230 is sampled with the same start signal and clock signal that provides timing for the sample rate such that signal 228 can be sampled at a rate that is a multiple of the generation frequency”; Examiner notes WITT also teaches AC/DC sourcing in the above citation, and control loop, see Col4,lines12-15.)
With respect to Claim 11, WITT, in view of PASSERINI, teaches:
The system of claim 1,
(See as above, references as applied to Claim 1.)
WITT further teaches:
comprising at least one of: an interface between the source unit and the control unit comprising low impedance buffered analog signals; an interface between the measurement unit and the control unit comprising a voltage mode analog signal interface with low impedance transmitting and high impedance receiving circuitry; and an interface between the measurement unit and the control unit comprising a current mode analog signal interface with high output impedance transmitting and low impedance receiving circuitry.
(WITT teaches at least interface between the source unit and the control unit comprising low impedance buffered analog signals, see Col3,lines61-63: “DAC 204, together with a DMA-based circular buffer (not shown), produces a waveform signal at a desired frequency, e.g., a sinusoidal waveform”)
With respect to Claim 12, WITT, in view of PASSERINI, teaches:
The system of claim 1,
(See as above, references as applied to Claim 1.)
WITT further teaches:
wherein at least one of:
the system comprises a power supply is configured to supply power to the control unit, the source unit, and the measurement unit referenced to a common ground;
(WITT teaches use of power supply as would be generally understood as necessary for a measurement system, see FIG.3, power source for instruments there in is implicitly disclosed. Moreover, WITT discloses a goal of overall power use/reduction in a measurement system.)
the system comprises a power supply filter to at least one of the measurement unit and the source unit;
(WITT teaches a filter in at least a measurement unit, see FIG.3 with Col4,lines3-6: “operational amplifier circuit 226 low-pass filters signal 223 that is then input to ADC 230 for digital conversion”, as noted above operational amplified is part of a measurement path.)
and at least one of the measurement unit and the source unit is powered from at least one of an isolated power converter from the control unit, an isolated external power source, and battery power.
(As above, power supply for a measurement system is implicit as would be understood by one of ordinary skill, and overall power management is recited as a goal in invention claimed by WITT.)
With respect to Claim 22, WITT teaches:
A method comprising:
providing a source signal to a sample via a source unit
(WITT teaches a time dependent voltage signal applied to a sample, as above, see FIG. 3, Col. 5, lines 22-24: “sinusoidal voltage x(t)=cos(2πFc.Math.t) is applied to test load 210”; and teaches source unit depicted in FIG. 3 and described in Col3,lines 29-60;
comprising: at least one of a voltage source
(As above WITT teaches time dependent voltage source refer to FIG. 3, Col. 5, lines 22-24.)
a memory configured to store a source calibration;
(As above, WITT teaches use of standard computational components used in a measurement system, see, for example, voltage source to sample under test, refer to FIG. 3, with Col4,lines42-43)
acquiring from the sample a measurement signal responsive to the source signal via a measurement unit,
(As above, WITT teaches acquiring data from sample, FIG. 3, element 226; with a signal in response to source applied, see FIG. 3, with Col3,lines65-66, “signal is passed through sample under test 210”)
the measurement unit
(WITT teaches measurement unit, refer to FIG. 3, element 226.)
comprising: at least one of a voltage measuring unit, a current measuring unit, and a capacitance measuring unit; a memory configured to store a measurement calibration;
(As above, WITT teaches at least a voltage measuring unit, refer to FIG.3, with Col3,lin67-Col4,lines 1-5: “signal is selectively input into sample under test 210 in a measurement path….operational amplifier circuit 220”; Examiner notes one of ordinary skill would identify this description of a measurements circuit.)
and receiving the measurement signal from the measurement unit by a control unit,
(WITT teaches a control unit circuitry, refer to FIG. 3, with elements 204, 230, 350, 352, 354, and 360 forming a control circuitry for measurement system.)
the control unit comprising:
(As above, WITT teaches a control unit circuitry, refer to FIG. 3, with elements 204, 230, 350, 352, 354, and 360 forming a control circuitry for measurement system.)
a digital signal processing unit;
(WITT teaches digital signal processing, refer to FIG. 3, element 360, label “DIGITAL SIGNAL PROCESSING MODULE”);
a source converter connected between the digital signal processing unit and the source unit;
(WITT depicts source converter, see FIG. 3, element 204, situated in FIG. 3 between digital signal processing unit (element 360) and source unit (element 302).)
a measurement converter connected between the digital signal processing unit and the measurement unit;
(WITT depicts measurement converter in FIG. 3, element 230, situated as shown in FIG. 3 between digital signal procession module and a measurements unit.)
a synchronization unit configured to synchronize clocks of the digital signal processing unit, the source converter, and the measurement converter;
(WITT depicts synchronization unit in FIG. 3, element 354, a digital signal processing unit as above, element 360, and source converter element 204, along with measurement converter element 230; with configuration of synchronization unit described in Col5,lines10-13: “clock ensures that control signals 356, 358 synchronize the digital waveform generation by DAC 204 with the data collection and the sampling process by ADC 230”, followed by more detailed description of synchronization process in Col5,lines14-41; )
a calibration unit for calibrating aspects of the system including the control unit; and
(WITT teaches calibration unit, see Col2,lines 12-14: “Circuit responses of the testing circuit combined with measurements on a known calibration channel allow for the determination of the complex impedance”; and see Col4,lines62-64: “waveform is compensated, for example, by a pre-distortion calibration”; WITT teaches calibration as part of control system, refer to FIG.3.).
for calibrating portions of the measurement system including a measurement channel.
(As above, WITT teaches these components integrated into a measurements system in FIG. 3; Examiner notes interpretation of claim limitation language of “measurement channel” to be analogous to reference language of “measurement path”)
However WITT is silent to the language of:
and a current source;
a reference voltage supply configured to supply a common reference voltage for the control unit
PASSERINI teaches:
and a current source
(PASSERINI is in same technical area, teaching clocks applied to a measurement system, see [0005]: “during a testing phase of an electronic device, it is often required to configure the clock period or clock phase among a range of possible values”; teaches use of a current source, refer to FIG. 3A and [0044] “reference bias generator G1 to produce a substantially constant current”)
a reference voltage supply configured to supply a common reference voltage for the control unit
(PASSERINI teaches use of reference voltage, see clocks applied to a measurement system, see Fig. 3A with [0043]: “master oscillator 110 comprises a first or left module 310 and a second or right module 320 and is connected to a common voltage reference Vref.”, i.e. provides common reference voltage”)
It would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to modify WITT to include a current source and a reference voltage supply as part of a measurement system, such as that of PASSERINI.
One of ordinary skill would be motivated to modify WITT to include a current source and a reference voltage supply as part of a measurement system, as taught by PASSERINI because it would be understood as an obvious way to expand and enhance overall functionality and sample diversity for an integrated measurements system. One of ordinary skill would know the importance of including a reference voltage in a system designed for accurate electrical measurements so that the reliability of any result would be improved.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over WITT (US 9575105 B1) in view of PASSERINI (US 20130033947 A1), as applied to Claim 1 above, and further in view of BANASKA (US 5144154 A).
With respect to Claim 5, WITT, in view of PASSERINI, teaches:
The system of claim 1,
(See as above, references as applied to Claim 1.)
However, WITT, as modified by PASSERINI, as taught above, is silent to the language of:
wherein the current source is configured to measure a source current associated with the source signal via a sensing resistor and vary a resistance range of the sensing resistor according to a magnitude of the source current.
Nevertheless, BANASKA teaches:
wherein the current source is configured to measure a source current associated with the source signal via a sensing resistor and vary a resistance range of the sensing resistor according to a magnitude of the source current.
(For context, see Col1,lines6-7: “invention relates to range changing in a measuring device”, thus BANASKA is in same technical field; BANASKA teaches measuring current, see Col1,lines17-19: “To measure current through the load, a resistor or other impedance, is added between the amplifier output and the load”; and variable resistance, see Col. 1, Lines 27-31: “to measure a wide range of currents…common to provide several different values of these current-sensing resistors”; and source current, see FIG. 1 and Col3,lines40-44: “current flowing through the resistor 14 results in a voltage that is measured by the voltage measuring device 34…voltage is directly related to the output current of the circuit 10 according to the resistance of the resistor 14.”)
It would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to further modify WITT, as modified by PASSERINI, as taught above, to include wherein the current source is configured to measure a source current associated with the source signal via a sensing resistor and vary a resistance range of the sensing resistor according to a magnitude of the source current, such as that of BANASKA.
One of ordinary skill would be motivated to further modify WITT, as modified by PASSERINI, as taught above, to include wherein the current source is configured to measure a source current associated with the source signal via a sensing resistor and vary a resistance range of the sensing resistor according to a magnitude of the source current, as taught by BANASKA because it would be understood as an obvious way to enhance a measurement system to allow for a wider range of current values that could be accurately measures. One of ordinary skill would realize the disclosure of BANASKA as an obvious improvement on the system of WITT as modified by PASSERINI because a larger range of current sources and sample signals would be possible for accurate and reliable measurements.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over WITT (US 9575105 B1) in view of PASSERINI (US 20130033947 A1) and BANASKA (US 5144154 A), as applied to Claim 5 above, and further in view of SEONG (US 5687051 A).
With respect to Claim 6, WITT, in view of PASSERINI and BANASKA, teaches:
The system of claim 5,
(See as above, references as applied to Claim 5.)
However, WITT, as modified by PASSERINI and further modified by BANASKA is silent to the language of:
a current source protection unit configured to determine whether the source current exceeds a threshold current and when the source current exceeds the threshold current, alter a feedback element of at least one of the source unit and the measurement unit so that the source current falls below the threshold current; and
a voltage source protection unit configured to determine whether a source voltage exceeds a threshold voltage and when the source voltage exceeds the threshold voltage, alter a feedback element of at least one of the source unit and the measurement unit so that the source voltage falls below the threshold voltage.
Nevertheless, SEONG teaches:
a current source protection unit configured to determine whether the source current exceeds a threshold current and when the source current exceeds the threshold current, alter a feedback element of at least one of the source unit and the measurement unit so that the source current falls below the threshold current;
(For context, see Abstract: “provided which includes a control circuit formed on an integrated circuit. The control circuit controls an operation of a device. The circuitry further includes a feedback circuit and a protection circuit.”, thus SEONG is in same technical field, teaching a feedback circuit for protection; SEONG teaches current source with threshold-based protection, see Col1,lines32-56: “Control circuit 540 is formed substantially on integrated circuit 550, with the exception of a capacitor G connected to external pin #7 of integrated circuit 550, and comprises an oscillator 60, an undervoltage lock out circuit (UVLO) 70, a current limiting circuit 50, and a pulse amplitude modulation circuit 40.”; and see Col3,lines17-25: “second voltage regulator is provided having a cathode connected to the output of the first current source and an anode connected to an input of the protection circuit…serves to prevent a voltage higher than a certain second threshold from being formed across the second voltage regulator”; Examiner notes one of ordinary skill would understand current limiting properties of described circuit.)
a voltage source protection unit configured to determine whether a source voltage exceeds a threshold voltage and when the source voltage exceeds the threshold voltage, alter a feedback element of at least one of the source unit and the measurement unit so that the source voltage falls below the threshold voltage.
(As above, SEONG teaches voltage regulation, and see Col2,lines14-19: “Under voltage lock-out circuit 70 overrides the operation of control circuit 540 by providing a high level input to NOR gate 42 if the input power voltage being provided to integrated circuit 550 (i.e., Vcc), is less than a predetermined voltage value.”)
It would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to further modify WITT, as modified by PASSERINI and BANASKA, as taught above, to include a current source protection unit as described above, and a voltage source protection unit as described above, such as that of SEONG.
One of ordinary skill would be motivated to further modify WITT, as modified by PASSERINI and BANASKA, as taught above, to include a current source protection unit as described above, and a voltage source protection unit as described above, as taught by SEONG because it would be understood as an improved feature to a measurements system that would serve to prevent damage to a sample and also keep an integrated measurement system from being damaged by undesired overcurrent, overvoltage, and/or reverse voltage conditions. One of ordinary skill would be familiar with the need for safety, along with the improved ability to achieve accurate and reliable measurements because it would be understood as a way to prevent a system from performing measurements during a fault condition. The features disclosed by SEONG would be understood as an efficient and effective way to prevent sensitive electronic components from damage that could be caused by current or voltage spikes during transient measurement events, thereby ensuring measurement integrity, and more importantly providing an added layer of safety for an operator of the measurement system.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over WITT (US 9575105 B1) in view of PASSERINI (US 20130033947 A1), as applied to Claim 1 above, and further in view of HUTCHISON (US 4564018 A).
With respect to Claim 9, WITT, in view of PASSERINI, teaches:
The system of claim 1,
(See as above, references as applied to Claim 1.)
However, WITT as modified by PASSERINI, as taught above, is silent to the language of:
wherein at least one of: the source unit is configured to deactivate non-analog circuitry in response to the source signal being provided; and the measurement unit is configured to deactivate non-analog circuitry in response to the measurement signal being measured.
Nevertheless, HUTCHISON teaches:
(For context, see Col1,lines7-9: “invention relates generally to systems for obtaining ocular measurements, and particularly to an ultrasonic diagnostic scanner”, thus HUTCHISON is in same technical field; HUTCHISON teaches at least measurement unit analog deactivation when measuring, see Col13,lines52-58: “transmit command signal is also sent to the "shut down" port of the switching voltage regulator U26. Thus, the transmit command signal will cause the switching voltage regulator U25 to turn off during a measurement to insure that no high voltage pulse interferes with the accuracy of the measurement.”; Examiner notes interpretation of “deactivation” in claim limitation as analogous to reference language of “shut down”.)
It would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to further modify WITT, as modified by PASSERINI, as taught above, to include wherein at least one of: the source unit is configured to deactivate non-analog circuitry in response to the source signal being provided; and the measurement unit is configured to deactivate non-analog circuitry in response to the measurement signal being measured, such as that of HUTCHISON.
One of ordinary skill would be motivated to further modify WITT, as modified by PASSERINI, as taught above, to include wherein at least one of: the source unit is configured to deactivate non-analog circuitry in response to the source signal being provided; and the measurement unit is configured to deactivate non-analog circuitry in response to the measurement signal being measured, as taught by HUTCHISON because it would be understood as an efficient and effective way to achieve improved accuracy and reliability in measurements by eliminating potential interference due to electromagnetic noise that is known in the art as a corruptive influence on sensitive measurements. One of ordinary skill would understand this straightforward technique as an obvious improvement to the system disclosed by WITT and modified by PASSERINI to ensure accuracy and signal integrity for measurements.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over WITT (US 9575105 B1) in view of PASSERINI (US 20130033947 A1), as applied to claim 1 above, and further in view of SCHNEIDER (US 10284217 B1).
With respect to Claim 13, WITT, in view of PASSERINI, teaches:
The system of claim 1,
(See as above, references as applied to Claim 1.)
However, WITT, as modified by PASSERINI, as taught above, is silent to the language of:
wherein at least one of the source converter and the measurement converter comprises: a gain chain configured to amplify an analog input signal; a range selector configured to select a gain between the analog input signal and the multiple analog-to-digital converter (ADC) outputs, wherein each ADC output has a path, and a gain of each output path is made up of gain stages in the gain chain; and a mixer configured to combine the multiple ADC outputs into a single mixed output.
Nevertheless, SCHNEIDER teaches:
wherein at least one of the source converter and the measurement converter
(For context, see Col1,lines23-25: “relates in general to signal processing systems, and more particularly, to multiple path signal processing systems”, thus SCHNEIDER is in same technical field; SCHNEIDER teaches at least a measurement converter, see Col2,lines18-24: “first processing path comprises a first analog front end and a first digital processing subsystem having a first analog-to-digital converter, wherein the first analog front end is configured to amplify an analog input signal in order to generate a first amplified analog signal”)
[measurement converter] comprises: a gain chain configured to amplify an analog input signal;
(SCHNEIDER teaches amplification, see FIG.3, and Col6,lines37-43: “analog front end 203b of processing path 201b may include an inverting amplifier 306 which may amplify analog input signal”)
a range selector configured to select a gain between the analog input signal and the multiple analog-to-digital converter (ADC) outputs,
(SCHNEIDER teaches gain ranging for signal detection, see Col6,lines27-30: “Non-inverting amplifier 304 may amplify analog input signal…by a non-inverting gain and communicate such amplified analog signal to ADC 215a.” and see FIG. 3 with Col6,lines37-48: “analog front end 203b…may include an inverting amplifier 306 which may amplify analog input signal…greater dynamic range for analog input signal ANALOG_IN may be achieved”; and SCHNEIDER teaches ADC outputs, see Col. 9, Lines 14-17: “to constrain the additional gain and compensate for any cumulative (e.g., over multiple switching events between digital signals of ADCs 215) bias”)
wherein each ADC output has a path, and a gain of each output path is made up of gain stages in the gain chain;
(SCHNEIDER teaches multiple path with custom gain features, see Col9,line12-24: “additional gain, once applied to a path gain of a processing path 201, may be allowed over a period of time to approach or “leak” to a factor of 1…Without undertaking this step to allow the additional gain to leak to unity, multiple switching events between paths may cause the gain factor to increase or decrease in an unconstrained…affects the outputs of the multiple paths and thus affects the calculation of the scaling factor.”)
and a mixer configured to combine the multiple ADC outputs into a single mixed output.
(SCHNEIDER teaches mixing multiple outputs, see Col11,lines59-64: “multiplexer 227 may operate as a mixer, mixing appropriate weighted amounts of the digital signal output by processing path 201a and the digital signal output by processing path 201b to generate digital output signal DIGITAL_OUT.”).
It would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to further modify WITT, as modified by PASSERINI, as taught above, to include wherein at least one of the source converter and the measurement converter comprises: a gain chain configured to amplify an analog input signal; a range selector configured to select a gain between the analog input signal and the multiple analog-to-digital converter (ADC) outputs, wherein each ADC output has a path, and a gain of each output path is made up of gain stages in the gain chain; and a mixer configured to combine the multiple ADC outputs into a single mixed output, such as that of SCHNEIDER.
One of ordinary skill would be motivated to further modify WITT, as modified by PASSERINI, as taught above, to include wherein at least one of the source converter and the measurement converter comprises: a gain chain configured to amplify an analog input signal; a range selector configured to select a gain between the analog input signal and the multiple analog-to-digital converter (ADC) outputs, wherein each ADC output has a path, and a gain of each output path is made up of gain stages in the gain chain; and a mixer configured to combine the multiple ADC outputs into a single mixed output, as taught by SCHNEIDER because it would be understood as an efficient and effective way to expand the dynamic range of measurement capacity in a measurement system. One of ordinary skill would understand this as an obvious improvement to the system disclosed by WITT as modified by PASSERINI because this technique would enhance signal-to-noise ratios and allow for improved capacity to discern signa over internal or external noise floor. One of ordinary skill would be motivated to include customized gain chain as taught by SHNEIDER as a reliable way to accurately combine multiple ADC data into a single data stream and thereby enhance system efficiency.
Claims 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over WITT (US 9575105 B1) in view of PASSERINI (US 20130033947 A1), as applied to claim 1 above, and further in view of BAUMGARTNER (US 5382956 A).
With respect to Claim 14, WITT in view of PASSERINI, teaches:
The system of claim 1,
(See as above, references as applied to Claim 1.)
However, , WITT, as modified by PASSERINI, as taught above, is silent to the language of:
wherein the source converter comprises:
two or more digital-to-analog converters (DAC) combined to generate one or more frequency components;
a first path for generating low frequency signals, the first path comprising a first one of the DACs;
a second path for generating high frequency signals, the second path comprising a second one of the DACs;
a data processor for processing an input signal;
a combining circuit configured to combine outputs of the first path and the second path into the source signal;
a feedback portion configured to sense the source signal; and
a servo loop configured to employ the feedback portion to maintain the source signal with respect to the input signal.
Nevertheless, BAUMGARTNER teaches:
wherein the source converter comprises: two or more digital-to-analog converters (DAC) combined to generate one or more frequency components;
(For context, see Col1,lines19-24: “relates generally to biomedical instrumentation and more particularly to a mixed analog and digital integrated circuit for the front end of physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs”, thus BAUMGARTNER is in same technical field; BAUMGARTNER teaches source converter with at least two DAC converters, see Col3,lines35-38: “Chip has 5 signal channels. Each channel has input protection circuitry, channel input selection switches, an analog preamp with selectable gain and a continuous analog to digital converter.”; and teaches multiple frequencies, see Co 22,lines58-60: “AC impedance measurement (which is at a relatively high frequency) and low frequency signal measurement can occur simultaneously.”)
a first path for generating low frequency signals, the first path comprising a first one of the DACs; a second path for generating high frequency signals, the second path comprising a second one of the DACs;
(BAUMGARTNER teaches at least two paths, see Col23,line 5: “the low frequency voltage signal path”; and see Col23,lines6-7: “the high frequency signal path” )
a data processor for processing an input signal;
(BAUMGARTNER teaches standard computational components for measurement system, see Col2,lines55-58: “typical physiological signal instrumentation will include analog to digital conversion for further processing by an internal microprocessor or an external computer”)
a combining circuit configured to combine outputs of the first path and the second path into the source signal;
(BAUMGARTNER teaches combining output signals, see Col7,lines45-47: “Each A/D converter 346 output goes to a single output data controller 348 for combined digital serial data output 350.”)
a feedback portion configured to sense the source signal;
(BAUMGARTNER teaches feedback technique for source signal management, see Col3,lines53-57: “Chip incorporates extensive noise reduction measures, including chopper stabilization in all amplifiers…common mode feedback circuitry”; and see Col7,lines36-39: “common mode feedback to the source (right leg drive) removes some DC offset”)
and a servo loop configured to employ the feedback portion to maintain the source signal with respect to the input signal.
(BAUMGARTNER teaches use of servo loop, Refer to FIG. 4A, with Col10,lines9-16: “electronic switch 422 selects a fraction of the second output 418 for negative feedback signal 424 which controls the overall preamp closed loop gain…resistor values as shown in FIG. 4A, the gain can be selected to values of 2, 4, 16, and 32…results in a closed loop gain”; and see Col10,lines 40-48: “components are chosen to provide the dominant pole (approximately 3 Hz) for the overall preamp frequency response to ensure overall closed loop preamp stability”)
It would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to further modify WITT, as modified by PASSERINI, as taught above, to include the characteristics as recited above for a source converter, such as that of BAUMGARTNER.
One of ordinary skill would be motivated to further modify WITT, as modified by PASSERINI, as taught above, to include the characteristics as recited above for a source converter, as taught by BAUMGARTNER because the components and functions would bring about a reasonable expectation of achieving wider bandwidth and improved accuracy. One of ordinary skill would be motivated to combine the techniques disclosed by BAUMGARTNER into the system as taught by WITT and modified by PASSERINI to provide improved frequency response and take advantage of the method of using multiple DAC instruments to split up and customize frequency response with the increase in detectable bandwidth, and reasonable expectation of success in further reducing noise.
With respect to Claim 16, WITT in view of PASSERINI, teaches:
The system of claim 1,
(See as above, references as applied to Claim 1.)
However, , WITT, as modified by PASSERINI, as taught above, is silent to the language of:
wherein the control unit is configured to measure a parameter of the source signal using a feedback signal that is one of a DC signal and a low frequency AC signal.
Nevertheless, BAUMGARTNER teaches:
wherein the control unit is configured to measure a parameter of the source signal using a feedback signal that is one of a DC signal and a low frequency AC signal.
(BAUMGARTNER teaches control unit using feedback, see Col7,lines37-40: “common mode feedback to the source (right leg drive) removes some DC offset. After DC amplification, additional offset subtraction is accomplished within the analog to digital conversion process”).
It would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to further modify WITT, as modified by PASSERINI, as taught above, to wherein the control unit is configured to measure a parameter of the source signal using a feedback signal that is one of a DC signal and a low frequency AC signal, such as that of BAUMGARTNER.
One of ordinary skill would be motivated to further modify WITT, as modified by PASSERINI, as taught above, to wherein the control unit is configured to measure a parameter of the source signal using a feedback signal that is one of a DC signal and a low frequency AC signal, as taught by BAUMGARTNER because it would be understood as a way to improve measurement accuracy by reducing noise, and simplifying acquisition of signal. One of ordinary skill would understand that having options in source signal feedback has a reasonable expectation of success when used in a complex measurement system.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over WITT (US 9575105 B1) in view of PASSERINI (US 20130033947 A1) as applied to Claim 1 above, and further in view of GOODRICH (US 4807146 A).
With respect to Claim 15, WITT in view of PASSERINI, teaches:
The system of claim 1,
(See as above, references as applied to Claim 1.)
However, , WITT, as modified by PASSERINI, as taught above, is silent to the language of:
wherein the digital signal processing unit is configured to perform lock-in signal processing and wherein the lock-in signal processing unit is configured to at least one of:
be synchronized with the synchronization unit; process at least one of a fundamental frequency and a harmonic frequency; and provide a lock-in reference for communication between the control unit and at least one of the source unit and the measurement unit.
Nevertheless, GOODRICH teaches:
wherein the digital signal processing unit is configured to perform lock-in signal processing
(For context, see, Abstract: “digital lock-in amplifier has a digital-to-analog converter connected between a central processing unit and a source of a signal to be detected or measured”, thus GOODRICH is in same technical field and teaches using digital signal processing unit with lock-in.)
and wherein the lock-in signal processing unit is configured to at least one of: be synchronized with the synchronization unit; process at least one of a fundamental frequency and a harmonic frequency; and provide a lock-in reference for communication between the control unit and at least one of the source unit and the measurement unit.
(GOODRICH teaches at least a lock-in reference for communication, see Col3,lines51-59 “able to measure the in phase and in quadrature components of the fundamental reference frequency and harmonics produced by the measurement device”)
It would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to further modify WITT, as modified by PASSERINI, as taught above, to include wherein the digital signal processing unit is configured to perform lock-in signal processing and wherein the lock-in signal processing unit is configured to at least one of: be synchronized with the synchronization unit; process at least one of a fundamental frequency and a harmonic frequency; and provide a lock-in reference for communication between the control unit and at least one of the source unit and the measurement unit, such as that of GOODRICH.
One of ordinary skill would be motivated to further modify WITT, as modified by PASSERINI, as taught above, to include wherein the digital signal processing unit is configured to perform lock-in signal processing and wherein the lock-in signal processing unit is configured to at least one of: be synchronized with the synchronization unit; process at least one of a fundamental frequency and a harmonic frequency; and provide a lock-in reference for communication between the control unit and at least one of the source unit and the measurement unit, as taught by GOODRICH because it would be understood as a way to take advantage of lock-in amplification techniques to measure weak and/or noisy signals with filtering and careful selection of frequencies. One of ordinary skill would see the advantage of combining the method taught by GOODRICH with the system of WITT as modified by PASSERINI to improve the ability to better synchronize measured signals with other system components way to improve measurement accuracy by reducing noise, and simplifying acquisition of signal.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over WITT (US 9575105 B1) in view of PASSERINI (US 20130033947 A1) as applied to Claim 1 above, and further in view of MEHLKOPF (US 5023552 A).
With respect to Claim 17, WITT in view of PASSERINI, teaches:
The system of claim 1,
(See as above, references as applied to Claim 1.)
However, WITT, as modified by PASSERINI, as taught above, is silent to the language of:
wherein the control unit is configured to assess a type of at least one of the measurement unit and the source unit and configure the digital signal processing unit according to the type.
Nevertheless, MEHLKOPF teaches:
wherein the control unit is configured to assess a type of at least one of the measurement unit and the source unit and configure the digital signal processing unit according to the type.
(For context, see Abstract: “magnetic resonance imaging device and method are disclosed in which, during acquisition of measuring data the receiver gain is switched over in dependence of the signal strength”, MEHLKOPF is in same technical field; MEHLKOPF teaches a control unit, see Col1,lines 10-36, describing invention, particularly lines 27-29, “(f) control means for controlling at least the means specified sub (b) to (e)”; and teaches configuration for control, see Col5,lined5-10: “parameter in the form of an estimate of the object in the examination space being used for selecting the gain factor for the various data sets to be measured which factor is adjusted under the control of the control unit 18B.” and see Col4,lines1-8: “central processor unit 18 comprises a central processing and control device 18B which controls a modulator 20 for the RF source 12 and the power supply source 8 for the gradient magnet coils 4 and which adjusts the gain factor of the signal amplifier 14. The amplifier 14 may be actively controlled or may consist of a fixed amplifier with an adjustable attenuator in the amplification path.”).
It would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to further modify WITT, as modified by PASSERINI, as taught above, to include wherein the control unit is configured to assess a type of at least one of the measurement unit and the source unit and configure the digital signal processing unit according to the type, such as that of MEHLKOPF.
One of ordinary skill would be motivated to further modify WITT, as modified by PASSERINI, as taught above, to include wherein the control unit is configured to assess a type of at least one of the measurement unit and the source unit and configure the digital signal processing unit according to the type, as taught by MEHLKOPF because it would be understood as a way add functionality to a measurement system, including an option for automated measurement. One of ordinary skill would appreciate the advantage of improving the system of WITT as modified by PASSERINI with multiple components to expand measurement capacity and a controller capable of identifying various components in the measurement system.
Claims 18 and 19 is rejected under 35 U.S.C. 103 as being unpatentable over WITT (US 9575105 B1) in view of PASSERINI (US 20130033947 A1) as applied to Claim 1 above, and further in view of FREIDHOF (US 20200200821 A1).
With respect to Claim 18, WITT in view of PASSERINI, teaches:
The system of claim 1,
(See as above, references as applied to Claim 1.)
However, WITT, as modified by PASSERINI, as taught above, is silent to the language of:
further comprising an enclosure for at least one of the source unit and the measurement unit, the enclosure comprising at least one of electrostatic shielding and magnetic shielding.
Nevertheless, FREIDHOF teaches:
further comprising an enclosure for at least one of the source unit and the measurement unit
(For context, see [0001]: “relates to an oscilloscope having an integrated signal generator. Moreover, the invention relates to the use of such an oscilloscope for testing a device under test and a method for testing a device under test”, FREIDHOF is in same technical field; FREIDHOF teaches an enclosure with components, see Abstract: “A digital sampling oscilloscope (DSO) includes a housing, an analog measurement input interface arranged in a housing wall of the housing and a measurement acquisition system having a digitizer and an acquisition memory coupled to the digitizer.”)
the enclosure comprising at least one of electrostatic shielding and magnetic shielding.
(FREIDHOF teaches shielded enclosure, see [0024]: “The housing 11 may be configured to shield the internal components from external electromagnetic waves.”)
It would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to further modify WITT, as modified by PASSERINI, as taught above, to include an enclosure for at least one of the source unit and the measurement unit, the enclosure comprising at least one of electrostatic shielding and magnetic shielding, such as that of FREIDHOF.
One of ordinary skill would be motivated to further modify WITT, as modified by PASSERINI, as taught above, to include an enclosure for at least one of the source unit and the measurement unit, the enclosure comprising at least one of electrostatic shielding and magnetic shielding, as taught by FREIDHOF because it would be understood as a way ensure accurate and reliable signal detection with reduced electromagnetic noise.
With respect to Claim 19, WITT in view of PASSERINI, teaches:
The system of claim 1,
(See as above, references as applied to Claim 1.)
However, WITT, as modified by PASSERINI, as taught above, is silent to the language of:
further comprising a configurable display that is configured to display at least one of: real time oscilloscope readings; and frequency spectrum readings.
Nevertheless, FREIDHOF teaches:
further comprising a configurable display
(FRIEDHOF teaches a configurable display for display real time oscilloscope readings, see [0026]: “All or portions of the data from the acquisition record in the acquisition memory A may be displayed as bitmapped image rendered on a display of the DSO [Digital Sampling Oscilloscope]”)
that is configured to display at least one of: real time oscilloscope readings; and frequency spectrum readings.
(FRIEDHOF teaches at least display of frequency spectrum readings from DSO, see [0026]: “DSO 10 may include a measurement value output interface 17 over which data from the acquisition record in the acquisition memory A may be output”)
It would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to further modify WITT, as modified by PASSERINI, as taught above, to include a configurable display that is configured to display at least one of: real time oscilloscope readings; and frequency spectrum readings, such as that of FREIDHOF.
One of ordinary skill would be motivated to further modify WITT, as modified by PASSERINI, as taught above, to include a configurable display that is configured to display at least one of: real time oscilloscope readings; and frequency spectrum readings, as taught by FREIDHOF because it would be understood as a way to improve comprehensive signal analysis. One of ordinary skill would also be motivated to include the technique of FREIDHOF in the system as disclosed by WITT, modified by PASSERINI as a way to increase flexibility for trouble shooting potential problems with a measured value or the measurement system.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over WITT (US 9575105 B1) in view of PASSERINI (US 20130033947 A1) as applied to Claim 1 above, and further in view of GOOKIN (US 4127811 A).
With respect to Claim 20, WITT in view of PASSERINI, teaches:
The system of claim 1,
(See as above, references as applied to Claim 1.)
However, WITT, as modified by PASSERINI, as taught above, is silent to the language of:
wherein the control unit is configured to perform at least one of:
a voltage measure mode calibration for a measurement unit by:
measuring an offset error at the measurement unit; storing the offset error in the memory of the measurement unit; connecting an amplifier associated with the measurement unit to a reference voltage; measuring, via the control unit, a gain error from applying the reference voltage to the amplifier; storing the measured gain error in the memory of the measurement unit; reading, via the control unit, at least one of the stored gain error from the memory of the measurement unit; and applying at least one of the offset error and the gain error to correct a voltage measurement;
and a current mode measure calibration for the measurement unit by:
disconnecting input connectors of the control unit; connecting input connectors of the measurement unit to ground; configuring the measurement unit in a voltage measure mode; measuring voltage offset errors of an amplifier via the measurement unit in voltage measure mode; applying an analog correction to decrease the measured voltage offset errors; switching the measurement unit to a current measure mode and floating inputs to the measurement unit; determining, via the control unit, voltage offset errors between the measurement unit and the control unit by configuring the measurement unit in a high current range and measuring a resultant voltage at the control unit; adjusting a leakage current until a current measurement of the measurement unit is decreased; storing, via the control unit, at least one of the adjusted leakage current and the voltage offset errors in the memory of the measurement unit; reading, via the control unit, at least one of the adjusted leakage current and the voltage offset errors; and applying at least one of the adjusted leakage current and the voltage offset errors to correct a current measurement of the measurement unit.
Nevertheless, GOOKIN teaches:
wherein the control unit is configured to perform at least one of:
a voltage measure mode calibration for a measurement unit by: measuring an offset error at the measurement unit; storing the offset error in the memory of the measurement unit; connecting an amplifier associated with the measurement unit to a reference voltage; measuring, via the control unit, a gain error from applying the reference voltage to the amplifier; storing the measured gain error in the memory of the measurement unit; reading, via the control unit, at least one of the stored gain error from the memory of the measurement unit; and applying at least one of the offset error and the gain error to correct a voltage measurement;
and a current mode measure calibration for the measurement unit by: disconnecting input connectors of the control unit; connecting input connectors of the measurement unit to ground; configuring the measurement unit in a voltage measure mode; measuring voltage offset errors of an amplifier via the measurement unit in voltage measure mode; applying an analog correction to decrease the measured voltage offset errors; switching the measurement unit to a current measure mode and floating inputs to the measurement unit; determining, via the control unit, voltage offset errors between the measurement unit and the control unit by configuring the measurement unit in a high current range and measuring a resultant voltage at the control unit; adjusting a leakage current until a current measurement of the measurement unit is decreased; storing, via the control unit, at least one of the adjusted leakage current and the voltage offset errors in the memory of the measurement unit; reading, via the control unit, at least one of the adjusted leakage current and the voltage offset errors; and applying at least one of the adjusted leakage current and the voltage offset errors to correct a current measurement of the measurement unit.
(For context, see Abstract: “voltmeter having multiple voltage ranges comprises substantially linear elements such that the transfer functions of the elements can be independently measured and logically combined”, thus GOOKIN is in same technical field; GOOKIN teaches a control unit to perform at least a voltage measurement, see Col1,lines20-22: “object of the present invention to calibrate a voltmeter having multiple ranges without the need for a separate reference voltage for each range”; and teaches measuring and storing offset, see FIG.3 with Col2,lines56-58: “offset error measurements (Xo,n) for the first three voltage ranges are made with the input of the D.C. Preamplifier 10” and Col4,lines32-34: “detector 10, responsive to the output of the selected configuration, SC, loads selected outputs into a memory M.”; use of amplifier associated with a reference voltage, refer to FIG.1, element 10 (“PREAMP”), with Col2,lines51-53: “the present invention calibrates five voltage ranges with only a single reference voltage”; measuring gain error, refer to FIG. 5 and FIG. 6, with Col3,lines7-9: “gain error measurement for the third (10V) range is made by applying the internal precision reference voltage, VREF, (+10 VDC) to the input of D.C.” and lines19-24: “gain error measurement for the second (1V) range is made by applying the internal precision reference voltage, VREF, (+10 VDC) to the precision ten-to-one divider”; storing gain error, see Col4,lines28-33: “input voltage and the reference voltages are selectively applied to the input of a selected configuration of circuit elements SC. A detector 10…loads selected outputs into a memory M.”); retrieving gain error, see Claim 1: “processor means responsive to the selectively stored contents of said memory and to the output of said second amplifier for producing an output representative of the amplitude of the input signal normalized to correct for the offset and gain errors”; and applying error for signal correction, see Col4,lines47-54: “processor periodically sample the correction factors during measurements and applying the corrective transfer functions to the output obtained from a measurement of an unknown voltage, an extremely accurate mode of voltage determination is accomplished, which constantly corrects for drifting components and requires a minimum amount of operator intervention for calibration.”)
It would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to further modify WITT, as modified by PASSERINI, as taught above, to include a control unit configured to perform at least one of: a voltage measure mode calibration for a measurement (to include steps as described above), and a current mode measure calibration for the measurement unit (to include steps as described above), such as that of GOOKIN.
One of ordinary skill would be motivated to further modify WITT, as modified by PASSERINI, as taught above, to include a control unit configured to perform at least one of: a voltage measure mode calibration for a measurement (to include steps as described above), and a current mode measure calibration for the measurement unit (to include steps as described above), as taught by GOOKIN because it would be understood as an improved way to ensure accuracy, maintain precision for measured values, and better achieve reliability for measurements over time. One of ordinary skill would be motivated to include the calibration technique of GOOKIN in the system as disclosed by WITT, modified by PASSERINI to improve the ability to account for system drift and ensure that measured values are aligned with specifications and reference values as part of overall quality assurance for a measurement system.
Allowable Subject Matter
Claims 21 and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure was included in Applicant’s submitted Information Disclosure Statements.
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/TONI D SAUNCY/Examiner, Art Unit 2863
/Catherine T. Rastovski/Supervisory Primary Examiner, Art Unit 2863
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