DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Examiner acknowledges the amendment to the title filed on December 16, 2025. The objection to specification in the previous Office Action filed on October 01, 2025 is hereby withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 7-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al. (US PG-Pub No.: 2022/0208911, hereinafter, “Cho”), prior art of record.
Regarding claim 1, Cho discloses a light emitting display device (see Cho, FIG. 2), comprising:
a first thin film transistor (130, FIG. 2), the first thin film transistor (130) comprising a first semiconductor pattern (131, FIG. 2), a first gate electrode (132, FIG. 2), a first source electrode (134, FIG. 2; source and drain are interchangeable), and a first drain electrode (133, FIG. 2);
a second thin film transistor (160, FIG. 2), the second thin film transistor (160) comprising a second semiconductor pattern (161, FIG. 2), a second gate electrode (162, FIG. 2), a second source electrode (top layer of 164, FIG. 2; ¶ [0081] discloses that 164 can be a multilayer), and a second drain electrode (170, FIG. 2); and
a light emitting element layer (182, ¶ [0097]) electrically connected to the second thin film transistor (160, FIG. 2),
wherein the second thin film transistor (160) further comprises a plurality of auxiliary metal layers (163 and bottom layer of 164), wherein the plurality of auxiliary metal layers (163 and bottom layer of 164) are in contact with a lower portion of each of the second source electrode (top layer of 164) and the second drain electrode (170, FIG. 2).
Regarding claim 2, Cho discloses the light emitting display device of claim 1, wherein the plurality of auxiliary metal layers (163 and bottom layer of 164) comprise molybdenum (¶ [0081]).
Regarding claim 3, Cho discloses the light emitting display device of claim 1, wherein at least one or more insulating layers (117+118a, FIG. 2) having a contact hole (hole for 163, 164, and 170, FIG. 2) are interposed among the second semiconductor pattern (161), the second source electrode (top layer of 164) and the second drain electrode (170), and the plurality of auxiliary metal layers (163 and bottom layer of 164) are in the contact hole (hole for 163 and bottom layer of 164 in 117, FIG. 2).
Regarding claim 4, Cho discloses the light emitting display device of claim 1, wherein the second semiconductor pattern (161), the second source electrode (top layer of 164), and the second drain electrode (170) are electrically connected through the plurality of auxiliary metal layers (163 and bottom layer of 164, FIG. 2).
Regarding claim 5, Cho discloses the light emitting display device of claim 1, wherein the first semiconductor pattern (131) is made of low-temperature polysilicon (¶ [0066]), and the second semiconductor pattern (161) is made of oxide (¶ [0077]).
Regarding claim 7, Cho discloses the light emitting display device of claim 1, further comprising: a first blocking layer (121a+122, FIG. 2) under the first semiconductor pattern (131) and a second blocking layer (152, FIG. 2) under the second semiconductor pattern (161, FIG. 2).
Regarding claim 8, Cho discloses the light emitting display device of claim 7, wherein at least one or more buffer layers (112-114, FIG. 2) are interposed between the first blocking layer (121a+122) and the second blocking layer (152, FIG. 2).
Regarding claim 9, Cho discloses the light emitting display device of claim 7, wherein a vertical length of the first blocking layer (121a+122) and the first semiconductor pattern (131) is different from a vertical length of the second blocking layer (152) and the second semiconductor pattern (161, FIG. 2).
Regarding claim 11, Cho discloses the light emitting display device of claim 1, wherein a material of the first semiconductor pattern (131) and a material of the second semiconductor pattern (161) are different from each other (¶¶ [0066] and [0077]).
Regarding claim 12, Cho discloses the light emitting display device of claim 1, wherein a material of the first source electrode (134) and the first drain electrode (133) is different from a material of the plurality of auxiliary metal layers (163 and bottom layer of 164, ¶ [0081]; 133 and 134 can be made of Al and 163 and bottom layer of 164 can be made of Mo).
Regarding claim 13, Cho discloses the light emitting display device of claim 1, wherein a material of the second source electrode (top layer of 164) and the second drain electrode (170) is different from a material of the plurality of auxiliary metal layers (163 and bottom layer of 164, ¶¶ [0081] and [0095]; 170 and top layer of 164 can be made of Al and 163 and bottom layer of 164 can be made of Mo).
Regarding claim 14, Cho discloses the light emitting display device of claim 1, wherein a material of the first source electrode (134) and the first drain electrode (133) is same as a material of the second source electrode (top layer of 164) and the second drain electrode (170; Al, ¶¶ [0081] and [0095]), and wherein a material of the plurality of auxiliary metal layers (163 and bottom layer of 164; Mo, ¶ [0081]) is different from materials (Al) of the first source electrode (134), the first drain electrode (133), the second source electrode (top layer of 164), and the second drain electrode (170).
Note: Claims 1 and 7 are rejected below using different mapping in order to reject claim 10.
Regarding claim 1, Cho discloses a light emitting display device (see Cho, FIG. 2), comprising:
a first thin film transistor (160, FIG. 2), the first thin film transistor (160) comprising a first semiconductor pattern (161, FIG. 2), a first gate electrode (162, FIG. 2), a first source electrode (163, FIG. 2), and a first drain electrode (164, FIG. 2);
a second thin film transistor (130, FIG. 2), the second thin film transistor (130) comprising a second semiconductor pattern (131, FIG. 2), a second gate electrode (132, FIG. 2), a second source electrode (top layer of 133, FIG. 2; ¶ [0081] discloses that 133 can be a multilayer), and a second drain electrode (170, FIG. 2); and
a light emitting element layer (182, ¶ [0097]) electrically connected to the second thin film transistor (130, FIG. 2),
wherein the second thin film transistor (130) further comprises a plurality of auxiliary metal layers (134 and bottom layer of 133), wherein the plurality of auxiliary metal layers (134 and bottom layer of 133) are in contact with a lower portion of each of the second source electrode (top layer of 133) and the second drain electrode (170, FIG. 2).
Regarding claim 7, Cho discloses the light emitting display device of claim 1, further comprising: a first blocking layer (152, FIG. 2) under the first semiconductor pattern (161) and a second blocking layer (121a+122, FIG. 2) under the second semiconductor pattern (131, FIG. 2).
Regarding claim 10, Cho discloses the light emitting display device of claim 7, wherein a vertical length of the second blocking layer (121a+122) and the second semiconductor pattern (131) is smaller than a vertical length of the first blocking layer (152) and the first semiconductor pattern (161, FIG. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US PG-Pub No.: 2022/0208911, hereinafter, “Cho”), prior art of record, as applied to claim 1 above, in view of UM et al. (US PG-Pub No.: 2020/0185428 A1, hereinafter, “UM”), prior art of record.
Regarding claim 6, Cho discloses the light emitting display device of claim 1.
Cho is silent regarding that the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode comprise at least three metal layers.
However, Cho discloses that the first source electrode (134), the first drain electrode (133), the second source electrode (164), and the second drain electrode (170) comprise a multilayer structure (¶¶ [0081] and [0095]). And UM discloses a light emitting display device (see UM, FIG. 2), wherein source and drain electrodes (122/123) have three metal layers (¶ [0065]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form Cho’s first source electrode, first drain electrode, second source electrode, and second drain electrode comprising at least three (can be four or five) metal layers, as taught by UM, since the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination. See MPEP $2144.07.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection with new mapping of prior art of record does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. To be more specific, with current mapping, a second source electrode is Cho’s top layer of 164, and a plurality of auxiliary metal layers are Cho’s 163 and bottom layer of 164.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIA L. CROSS whose telephone number is (571)270-3273. The examiner can normally be reached 9 am-5:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/XIA L CROSS/Primary Examiner, Art Unit 2892