DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/27/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 9-10, 13, 18, 21 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Peterson (US 2007/0285134) in view of Kim et al. (US 2020/0274546 and Kim hereinafter) further in view of Montoye et al (US 5541528 and Montoye hereinafter).
Regarding claim 1, Peterson discloses an apparatus [see figs. 1-4] comprising: an input circuit [fig. 2] configured to level-shift an input signal [IN] and generate an output signal [OUT] having a voltage range [0 ~2.6V, par. 18] different than a voltage range [e.g. 0~5 V, par. 18] of the input signal, the input circuit comprising: a blocking gate [202] configured to level shift the input signal; and a first inverter or buffer [106] configured to generate the output signal [OUT] based on an output of the blocking gate [output 202] received at an output of the first inverter or buffer [OUT from 202]; a second inverter [214] or buffer coupled across the first inverter or buffer and configured to provide feedback [feedback to 106], the second inverter [214] or buffer having an input [input 214] coupled directly to an output of the first inverter or buffer [output 106] and an output [output 214] coupled to an input of the first inverter or buffer [input 106, fig. 1] wherein the input circuit is configured to generate the output signal such that the voltage range of the output signal spans between a first voltage [3.3V, par. 18] provided to the first inverter or buffer and a second voltage [2.5V, par. 18] provided to the first inverter or buffer and the first inverter or buffer transitions the output of the first inverter or buffer from zero to the first voltage or from the first voltage to zero [see fig. 4]. Peterson does not explicitly disclose wherein the first voltage is a core voltage and wherein the second inverter or buffer is configured to increase a speed.
However, Kim discloses wherein a buffer circuit [110] operate in a core voltage range [par. 0056]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Peterson by incorporating the core voltage in order to a reduction of the power consumption required for the operation of the buffer. Peterson in view of Kim does not explicitly disclose wherein the second inverter or buffer is configured to increase a speed.
However, Montoye discloses buffer circuits having increased switching speed. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Peterson and Kim as taught in Montoye in order to provide increase switching speed.
Regarding claim 2, Peterson in view of Kim further in view of Montoye discloses [see figs. 1-4] wherein: the blocking gate comprises a transistor [302, fig. 3]; and a source or a drain of the transistor is configured to receive the input signal.
Regarding claim 4, Peterson in view of Kim further in view of Montoye discloses [see figs.1-4] wherein the core voltage is generated by an integrated circuit device [external to input buffer].
Regarding claim 5, Peterson in view of Kim further in view of Montoye discloses [see figs.1-4] wherein the gate of the transistor is not configured to receive the input signal and lacks a conductive pad, the gate of the transistor configured to receive the first voltage without using any conductive pads.
Regarding claim 9, Peterson discloses a system [see figs. 1-4] comprising: an integrated circuit device [see fig. 1] comprising one or more input/output (I/O) pads [102]; and at least one input circuit associated with at least one of the one or more I/O pads [106], each input circuit configured to level-shift an input signal [IN, fig. 2] received at the associated I/O pad and generate an output signal [OUT, fig. 2] having a voltage range [0 ~2.6V, par. 18] different than a voltage range [e.g. 0~5 V, par. 18] of the input signal, each input circuit comprising: a blocking gate [202, fig. 2] configured to level shift the input signal received at the associated I/O pad; and a first inverter or buffer [106] configured to generate the output signal based on an output of the blocking gate [output 202]; received at an output of the first inverter or buffer; a second inverter [214] or buffer coupled across the first inverter or buffer and configured to provide feedback [feedback to 106], the second inverter or buffer having an input [input 214] coupled directly to an output of the first inverter or buffer [output 106] and an output coupled to an input of the first inverter or buffer [input 106, fig. 1] wherein the input circuit is configured to generate the output signal such that the voltage range of the output signal spans between a first voltage [3.3V, par. 18] provided to the first inverter or buffer and a second voltage [2.5V, par. 18] provided to the first inverter or buffer and the first inverter or buffer transitions the output of the first inverter or buffer from zero to the first voltage or from the first voltage to zero [see fig. 4]. Peterson does not explicitly disclose wherein the first voltage is a core voltage and wherein the second inverter or buffer is configured to increase a speed.
However, Kim discloses wherein a buffer circuit [110] operate in a core voltage range [par. 0056]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Peterson by incorporating the core voltage in order to a reduction of the power consumption required for the operation of the buffer. Peterson in view of Kim does not explicitly disclose wherein the second inverter or buffer is configured to increase a speed.
However, Montoye discloses buffer circuits having increased switching speed. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Peterson and Kim as taught in Montoye in order to provide increase switching speed.
Regarding claim 10, Peterson in view of Kim further in view of Montoye discloses wherein, for each input circuit: the blocking gate comprises a transistor [302, fig. 3]; and a source or a drain of the transistor is configured to receive the input signal.
Regarding claim 13, Peterson in view of Kim further in view of Montoye discloses [see figs.1-4] the gate of the transistor is not configured to receive the input signal and lacks a conductive pad, the gate of the transistor configured to receive the first voltage without using any conductive pads.
Regarding claim 18, Peterson discloses a method [see figs. 1-4] comprising: receiving an input signal [IN, fig. 2]; and level-shifting the input signal to generate an output signal [OUT] having a voltage range [e.g. 0~5 V, par. 18] different than a voltage range [e.g. 0~5 V, par. 18] of the input signal using an input circuit [fig. 2]; wherein the input circuit comprises: a blocking gate [202, fig. 2] that level shifts the input signal; and a first inverter or buffer [106] that generates the output signal based on an output of the blocking gate [OUT 202] received at an output of the first inverter or buffer [input 106]; a second inverter [214] or buffer coupled across the first inverter or buffer and configured to provide feedback, the second inverter or buffer having an input [input 214] coupled directly to an output of the first inverter or buffer [106] and an output [output 214] coupled to an input of the first inverter or buffer [input 106] and wherein the input circuit generates the output signal such that the voltage range of the output signal spans between a first voltage [3.3V, par. 18] provided to the first inverter or buffer and a second voltage [2.5V, par. 18] provided to the inverter or buffer and the first inverter or buffer transitions the output of the first inverter or buffer from zero to the first voltage or from the first voltage to zero [see fig. 4]. Peterson does not explicitly disclose wherein the first voltage is a core voltage, and wherein the second inverter or buffer is configured to increase a speed.
However, Kim discloses wherein a buffer circuit [110] operate in a core voltage range [par. 0056]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Peterson by incorporating the core voltage in order to a reduction of the power consumption required for the operation of the buffer. Peterson in view of Kim does not explicitly disclose wherein the second inverter or buffer is configured to increase a speed.
However, Montoye discloses buffer circuits having increased switching speed. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Peterson and Kim as taught in Montoye in order to provide increase switching speed.
Regarding claim 21, Peterson in view of Kim further in view of Montoye discloses [see fig. 2] wherein the second inverter or buffer [214] cannot override [passes the signal forward; an inherent feature of buffer circuit] an input signal from the output of the blocking gate [output 202] received at the input of the first inverter or buffer.
Regarding claim 23, Peterson in view of Kim further in view of Montoye discloses [see fig. 2] wherein the input of the second inverter or buffer [214] is directly coupled to the output of the first inverter or buffer [106] without any intervening inverter or delay element [output 106 directly connected to 214].
Claims 3, 11 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Peterson in view of Kim and Montoye further in view of Tran et al. (US 12394451 and Tran hereinafter).
Regarding claims 3, 11 and 19, Peterson in view of Kim and Montoye discloses all the features with respect to claims 1, 10 and 18 as outlined above. Peterson in view of Kim further in view of Montoye further discloses wherein the blocking gate comprises a transistor [transistor 202], and wherein a gate of the transistor [gate 202] and the first inverter or buffer are configured to receive the same voltage as a power supply voltage for their operation [par. 18]. Peterson in view of Kim and Montoye does not explicitly disclose wherein a gate of the transistor and the first inverter or buffer are configured to receive the same core voltage.
However, Tran discloses [fig. 2] wherein a gate of the transistor [gate T2] and a first inverter or buffer [T4 and T5] are configured to receive a same voltage [VDDC, cl. 5, ln 3-50] ], and wherein the core voltage is generated by integrated circuit device [104]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Peterson in view of Kim and Montoye by incorporating the core voltage as taught in Tran in order to utilize core voltage required for the operation of the buffer/inverter.
Regarding claim 20, Peterson in view of Kim and Montoye further in view of Tran discloses [see fig. 2] wherein the core voltage is generated by an integrated circuit device [104].
Claims 6-7 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Peterson in view of Kim and Montoye further in view of Sanchez et al. (US 7183817 and Sanchez hereinafter).
Regarding claims 6 and 14, Peterson in view of Kim and Montoye discloses all the features with respect to claims 2 and 10 as outlined above. Peterson in view of Kim and Montoye does not explicitly disclose wherein the transistor comprises a native thick-gate or low threshold voltage thick-gate device and supports receipt of different input signals having different input voltage ranges.
However, Sanchez discloses [cl. 1, ln. 15-59] a transistor comprises a thick-gate and supports receipt of different input signals having different input voltage ranges. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Peterson in view of Kim and Montoye by incorporating the thick-gate device in order to implement output drivers for safe operation.
Regarding claims 7 and 15, Peterson in view of Kim and Montoye discloses all the features with respect to claims 1 and 9 as outlined above. Peterson in view of Kim and Montoye does not explicitly disclose wherein the inverter or buffer comprises a thin-oxide device.
However, Sanchez discloses [cl. 1, ln. 15-59] a buffers with a combination of thin gate-oxide. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Peterson in view of Kim and Montoye by incorporating the thin-gate device in order to provide an output buffer that interfaces multiple voltage levels while operating at the desired limits of the I/O speed.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Peterson in view of Kim and Montoye further in view of Shibata et al. (US 4683384 and Shibata hereinafter).
Regarding claim 17, Peterson in view of Kim and Montoye discloses all the features with respect to claim 9 as outlined above. Peterson in view of Kim and Montoye does not explicitly disclose wherein the integrated circuit device comprises a semiconductor chip having multiple I/O pads.
However, Shibata discloses [figs. 2-3] an integrated circuit device [IC, fig. 3] comprises a semiconductor chip having multiple I/O pads [3]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Peterson in view of Kim and Montoye by incorporating multiple I/O pads in order to use selectively the signal transmission function of the input or output circuits.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Peterson in view of Kim and Montoye and Shibata et al. further in view of Ker et al. (US 2003/0139024 and Ker hereinafter).
Regarding claim 22, Peterson in view of Kim and Montoye further in view of Shibata discloses all the features with respect to claim 17 as outlined above. Peterson in view of Kim and Montoye further in view of Shibata does not explicitly disclose further comprising: one or more diodes coupled between at least one of the one or more I/O pads and the blocking gate.
However, Ker discloses [fig. 12] one or more diodes [D1,D2/D3,D4] coupled between at least one of the one or more I/O pads [320]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Peterson in view of Kim and Montoye further in view of Shibata by incorporating one or more diodes in order to provide electrostatic discharge (ESD) protection circuit [abstract].
Response to Arguments
Applicant’s arguments with respect to claims 1, 9 and 18 have been considered but are moot because the new ground of rejection.
Conclusion
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/METASEBIA T RETEBO/Primary Examiner, Art Unit 2836
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