DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 18, 2023 and January 4, 2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Claim Objections
Claims 9 and 19 are objected to because of the following informalities:
Claim 9, line 1: insert –of—before “memory”.
Claim 19, line 3: insert –more—before “memories”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 4, 19, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 3 and 4 recite the limitation "physically most adjacent" in lines 3 and 2-3, respectively. It is unclear to the Examiner as to what constitutes “most adjacent”, and whether this phrase constitutes two groups being directly adjacent to each other, whether one of a plurality of groups is more adjacent to a third group than other groups, or some other interpretation.
Claims 19 recites the limitation "the plurality of processor device-memory groups" in line 10. There is insufficient antecedent basis for this limitation in the claim. A plurality of processor device-memory groups had not been previously recited.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7, 9-11, 13, and 15-26 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Purcell et al. (US# 6,836,815).
Regarding claim 1, Purcell et al. teaches an electronic apparatus comprising: a plurality of processor device-memory device groups, and each of the plurality of processor device-memory device groups [PG+Region R] comprising a plurality of memory devices respectively comprising one or more memories [C5, L56-63], a plurality of processor devices respectively comprising one or more processors[C5,L38-40], and a plurality of switches [PSW or MSW or PXB or SXB], wherein each of the plurality of switches comprises a plurality of ports, and each of first memory devices included in a first processor device-memory device group of the plurality of processor device-memory device groups is connected to a first subset of ports of one switch of first switches included in the first processor device-memory device group, and to a first subset of ports of one switch of second switches of the plurality of switches included in a second processor device-memory device group of the plurality of processor device-memory device groups [Fig. 7; C5,L46-55].
Regarding claim 2, Purcell et al. teaches wherein the first memory devices are connected to a first switch of the first switches [and a first switch of the second switches [each PG comprises switches, which are connected to SG switches, which are connected to the memories; Fig. 7].
Regarding claim 3, Purcell et al. teaches wherein the first processor device-memory device group and the second processor device-memory device group are disposed to be physically most adjacent to each other [PG0+R0 & PG1+R0].
Regarding claim 4, Purcell et al. teaches wherein the first processor device-memory device group and the second processor device-memory device group are not physically most adjacent to each other but are logically adjacent to each other [PG0+R0 & PG2+R0].
Regarding claim 5 Purcell et al. teaches, wherein the first processor device-memory device group and the second processor device-memory device group are disposed to transmit electrical signals between each other [by way of read and write access to shared memory group].
Regarding claim 6, Purcell et al. teaches, wherein, in each of the plurality of processor device-memory device groups, an equal number of connections exist between a corresponding plurality of memory devices and a corresponding plurality of switches [Fig. 7, at least between SG0 and MG0].
Regarding claim 7, Purcell et al. teaches wherein any of the plurality of switches is not (directly8) connected to another of the plurality of switches [Fig. 7, PXB not directly connected to MXB].
Regarding claim 9, Purcell et al. teaches, wherein numbers of the plurality memory devices in each of the plurality of processor device-memory device groups is equal [equal due to sharing; fig. 7].
Regarding claim 10, Purcell et al. teaches wherein numbers of the plurality of switches in each of the plurality of processor device-memory device groups is equal [fig. 7; groups mirror each other].
Regarding claim 11, Purcell et al. teaches, wherein a second subset of ports of the one switch of the first switches is connected to a corresponding processor device of the plurality of processor devices [at least PXB is connected to Pn].
Regarding claim 13, Purcell et al. teaches wherein a number of the plurality of processor devices is a multiple of a predetermined integer number [Fig. 7; no constraint on integer or multiple values].
Regarding claim 15, Purcell et al. teaches wherein each of the plurality of switches is a single-stage switch [ crossbar switches read upon interpretation of single state switch as seen in Spec. 0058].
Regarding claim 16, Purcell et al. teaches wherein each of the plurality of processor devices comprises a plurality of ports, and each of first processor devices of the plurality of processor devices in the first processor device-memory device group is connected to a second subset of ports of the one switch of the first switches, and a second subset of ports of the one switch of the second switches included in the second processor device-memory device group [claim language does not require direct connection; see figure 7].
Regarding claim 17, Purcell et al. teaches wherein the electronic apparatus is a storage device [PG +R includes memory devices; Fig. 7].
Regarding claim 18, Purcell et al. teaches electronic apparatus comprising: a plurality of processor device-memory device groups, and each of the plurality of processor device-memory device groups comprising a plurality of memory devices respectively comprising one or more memories, a plurality of processor devices respectively comprising one or more processors, and a plurality of switches, wherein each of the plurality of processor devices comprises a plurality of ports, and each of first processor devices included in a first processor device-memory device group of the plurality of processor device-memory device groups is connected to a first subset of one of first switches of the plurality of switches included in the first processor device-memory device group and to a first subset of ports of one switch of second switches of the plurality of switches included in a second processor device-memory device group of the plurality of processor device-memory device groups [Claim language similar to that of claim 1 and associated citations, and is rejected for the same reasons as claim 1 as seen in Figure 7 and C5,L29-67].
Regarding claim 19, Purcell et al. teaches electronic apparatus comprising: a plurality of memory device groups, and each of the plurality of memory device groups comprising a plurality of memory devices respectively comprising one or memories and a plurality of switches, wherein each of the plurality of memory devices comprises a plurality of ports, and each of first memory devices included in a first memory device group of the plurality of memory device groups is connected to a first subset of ports of one switch of first switches included in the first memory device group, and to a first subset of ports of one switch of second switches of the plurality of switches included in a second processor device-memory device group of the plurality of processor device-memory device groups [Claim language similar to that of claim 1 and associated citations without associated processor devices, and is rejected for the same reasons as claim 1 as seen in Figure 7 and C5,L29-67].
Regarding claim 20, Purcell et al. teaches wherein the first memory devices are connected to a first switch of the first switches and a first switch of the second switches [contains similar language to that of claim 2, and is rejected for the same reasons as claim 2].
Regarding claim 21, Purcell et al. teaches electronic apparatus comprising: a plurality of processor device groups, and each of the plurality of processor device groups comprising a plurality of processor devices respectively comprising one or more processors and a plurality of switches, wherein each of the plurality of processor devices comprises a plurality of ports, and each of first processor devices included in a first processor device group of the plurality of processor devices groups is connected to a first subset of one of first switches of the plurality of switches included in the first processor device group, and to a first subset of one switch of second switches of the plurality of switches included in a second processor device of the plurality of processor device groups [Claim language similar to that of claims 1 and 2 and associated citations without associated memories, and is rejected for the same reasons as claim 1 as seen in Figure 7 and C5,L29-67].
Regarding claim 22, Purcell et al. teaches electronic apparatus comprising: a plurality of processor device-memory device groups, and each of the plurality of processor device-memory device groups comprising a plurality of memory devices respectively comprising one or more memories, a plurality of processor devices respectively comprising one or more processors, and a plurality of switches, wherein each of the plurality of switches comprises a plurality of ports, and the plurality of memory devices in one processor device-memory device group of the plurality of processor device-memory device groups is connected to first subsets of ports of each of the plurality of switches in the one processor device-memory device group and another one processor device-memory device group of the plurality of processor device-memory device groups. [Claim language similar to that of claim 1 and associated citations and included within the scope of claim 1, and is rejected for the same reasons as claim 1 as seen in Figure 7 and C5,L29-67].
Regarding claim 23, Purcell et al. teaches wherein the plurality of memory devices in the other one processor device-memory device group is connected to second subsets of ports of each of the plurality of switches in the other one processor device-memory device group and a third processor device-memory device group of the plurality of processor device-memory device groups [fig. 7; memory devices connected to each processor group by way of sharing].
Regarding claim 24, Purcell et al. teaches wherein the plurality of processor devices in the one processor device-memory device group is connected to third subsets of ports of each of the plurality of switches in the one processor device-memory device group and the other one processor device-memory device group [PG0 (not directly) connected to any number of ports in other PGn and R0 as seen in Figure 7].
Regarding claim 25, Purcell et al. teaches wherein each of the plurality of processor device-memory device groups further comprises a plurality of network device connected to fourth subsets of ports of each of the plurality of switches in the one processor device-memory device group [as network devices is not defined, any PGn,PSWn, Pn, SXBn, etc. may be connected to a single port to comprise a subset not previously found within any other subset (although overlapping subsets may exist as the claim language does not prohibit this teaching); Fig. 7].
Regarding claim 26, Purcell et al. teaches wherein the electronic apparatus is a storage device [PG +R includes memory devices; Fig. 7].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Purcell et al. in view of OFFICIAL NOTICE.
Purcell et al. teaches a plurality of switches and crossbar switches in different location of the prior art, but fail to teach what type or protocols the switches may employ. One of ordinary skill in the art would recognize that a crossbar switch incorporated within a CXL fabric would include improved bandwidth allocation within the shared memory system. The Examiner takes OFFICIAL NOTICE of this teaching. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Purcell et al. to include the CXL switch system and fabric because of the benefit disclosed supra.
Allowable Subject Matter
Claims 8 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Brian R. Peugh whose telephone number is (571) 272-4199. The examiner can normally be reached on Monday-Friday from 7:30am to 3:30pm.
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/BRIAN R PEUGH/ Primary Examiner, Art Unit 2133