Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/06/2026 has been entered.
Response to Amendment
The amendments filed on 01/06/2026 have been fully considered and are made of record.
Claims 1, 8 and 15 have been amended.
Claims 13 has been cancelled.
Response to Arguments
Regarding 102 rejection, applicant’s arguments filed on 01/06/2026 with respect to claim(s) 1, 8 and 15 have been considered but are moot because the new ground of rejection has been applied to amended limitations.
Regarding 101 and 112 rejection, applicant’s arguments filed on 01/06/2026 have been considered and are persuasive. Therefore the rejection sent on Office Action mailed on 09/09/2025 is withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7, 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ross et al. (NPL; A COMPARISON OF MILLIMETER WAVE AND EDDY CURRENT DETECTION OF SURFACE BREAKING DEFECTS IN CONDUCTING MATERIALS; translation attached) in view of Grata et al. (Pub NO. US 2021/0088968 A1; hereinafter Grata).
Regarding Claim 1, Ross teaches a computing device (device for imaging; See page 630), comprising:
circuitry (eddy coil; See page 629-630) configured to:
capture electromagnetic image data of a sample (eddy coil captures electromagnetic image of sample; See page 630-631); and
assess the sample by reviewing the multi-layer rasterized image (assess crack of sample by reviewing/comparing multi-layer rasterized image in Fig. 5; See page 633-634).
Ross teaches converting electromagnetic image data (C-Scan image in Fig. 5(a) is multi-layer rasterized image; See page 631-633),
However Ross is silent about convert the image data to a multi-layer rasterized image, wherein the multi-layer rasterized image represents multiple depth image planes of the sample.
Grata teaches convert the image data to a multi-layer rasterized image (generating multi-depth image sequence by rastering is multi-layer rasterized image; See [0015]), wherein the multi-layer rasterized image represents multiple depth image planes of the sample (See [0018]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Ross by converting the image data to a multi-layer rasterized image, wherein the multi-layer rasterized image represents multiple depth image planes of the sample, as taught by Grata in order to generate multi-depth image sequences by rastering a plurality of voxels at different depths on the one or more image depth planes (Grata; [0015]).
Regarding Claim 7, Ross in view of Grata teaches the computing device of claim 1. Ross further teaches wherein assessing the sample comprises at least one of: validating that no malicious circuitry has been injected in the sample; detecting evidence of infringement of intellectual property; detecting a defect in the sample (See page 629-633); or performing silicon validation of the sample.
Regarding Claim 15, Ross teaches a computer-implemented method comprising:
capturing, by at least one processor, electromagnetic image data of a sample (eddy coil is part of processor that generates/processes graph in Fig. 1-Fg. 5 and coil captures electromagnetic image of sample; See page 630-631); and
assessing the sample by reviewing the multi-layer rasterized image (assess crack of sample by reviewing/comparing multi-layer rasterized image in Fig. 5; See page 633-634).
Ross teaches converting electromagnetic image data (C-Scan image in Fig. 5(a) is multi-layer rasterized image; See page 631-633),
However Ross is silent about convert the image data to a multi-layer rasterized image, wherein the multi-layer rasterized image represents multiple depth image planes of the sample.
Grata teaches convert the image data to a multi-layer rasterized image (generating multi-depth image sequence by rastering is multi-layer rasterized image; See [0015]), wherein the multi-layer rasterized image represents multiple depth image planes of the sample (See [0018]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Ross by converting the image data to a multi-layer rasterized image, wherein the multi-layer rasterized image represents multiple depth image planes of the sample, as taught by Grata in order to generate multi-depth image sequences by rastering a plurality of voxels at different depths on the one or more image depth planes (Grata; [0015]).
Regarding Claim 20, Ross in view of Grata teaches the computer-implemented method of claim 15. Ross further teaches wherein assessing the sample comprises at least one of:
validating that no malicious circuitry has been injected in the sample;
detecting evidence of infringement, of intellectual property;
detecting a defect in the sample (See page 629-633); or
performing silicon validation of the sample.
Claim(s) 2-3, 8-10, 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ross in view of Grata further in view of Littlefield et al. (Pub NO. US 2023/0129831 A1; hereinafter Littlefield).
Regarding Claim 2, Ross in view of Grata teaches the computing device of claim 1. Ross further teaches wherein circuitry is configured to capture the electromagnetic image data (See page 629-631).
Ross in view of Grata is silent about using a gradiometer.
Littlefield teaches using a gradiometer (capture image using gradiometer; See [0026]-[0029]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Ross by capturing image by gradiometer, as taught by Littlefield in order to order to achieve maximum signal strength (Littlefield; [0022]).
Regarding Claim 3, Ross in view of Grata further in view of Littlefield teaches the computing device of claim 2. Littlefield teaches wherein the gradiometer is a linear polyaxial fluxgate gradiometer (it is inherent property of multi-element gradiometers are linear polyaxial fluxgate gradiometer; See [0027]).
Regarding Claim 8, Ross teaches a system (system for imaging; See page 630) comprising:
an electromagnetic imaging device (eddy coil captures electromagnetic image of sample; See page 630-631);
when executed by the at least one physical processor (processor generate image in Fig. 1-Fig. 5; See page 629-633), cause the at least one physical processor to:
capture electromagnetic image data of a sample by using the electromagnetic imaging device (eddy coil captures electromagnetic image of sample; See page 630-631);
convert the electromagnetic image data to a multi-layer rasterized image (C-Scan image in Fig. 5(a) is multi-layer rasterized image; See page 631-633); and
assess the sample by reviewing the multi-layer rasterized image (assess crack of sample by reviewing/comparing multi-layer rasterized image in Fig. 5; See page 633-634).
Ross teaches converting electromagnetic image data (C-Scan image in Fig. 5(a) is multi-layer rasterized image; See page 631-633),
However Ross is silent about convert the image data to a multi-layer rasterized image, wherein the multi-layer rasterized image represents multiple depth image planes of the sample; and at least one physical processor coupled to the electromagnetic imaging device; and physical memory comprising computer-executable instructions.
Grata teaches convert the image data to a multi-layer rasterized image (generating multi-depth image sequence by rastering is multi-layer rasterized image; See [0015]), wherein the multi-layer rasterized image represents multiple depth image planes of the sample (See [0018]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Ross by converting the image data to a multi-layer rasterized image, wherein the multi-layer rasterized image represents multiple depth image planes of the sample, as taught by Grata in order to generate multi-depth image sequences by rastering a plurality of voxels at different depths on the one or more image depth planes (Grata; [0015]).
Ross in view of Grata is silent about at least one physical processor coupled to the electromagnetic imaging device; and physical memory comprising computer-executable instructions.
Littlefield teaches regarding image capturing (See [0022], [0026], [0029]) at least one physical processor coupled to the electromagnetic imaging device (See [0041]); and physical memory comprising computer-executable instructions (it is inherent property that software has memory; See [0041]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Ross and Grata by capturing image by gradiometer, as taught by Littlefield in order to order to achieve maximum signal strength (Littlefield; [0022]).
Regarding Claim 9, Ross in view of Grata in view of Littlefield teaches the system of claim 8. Littlefield teaches wherein the electromagnetic imaging device includes a gradiometer (capture image using gradiometer; See [0026]-[0029]).
Regarding Claim 10, Ross in view of Grata in view of Littlefield teaches the system of claim 9. Littlefield teaches wherein the gradiometer is a linear polyaxial fluxgate gradiometer (it is inherent property of multi-element gradiometers are linear polyaxial fluxgate gradiometer; See [0027]).
Regarding Claim 14, Ross in view of Grata in view of Littlefield teaches the system of claim 8. Ross further teaches wherein assessing the sample comprises at least one of:
validating that no malicious circuitry has been injected in the sample;
detecting evidence of infringement, of intellectual property;
detecting a defect in the sample (See page 629-633); or
performing silicon validation of the sample.
K teaches wherein the sample corresponds to at least one of: a fabricated monolithic chip; a chiplet on wafer semiconductor device; a loose cut semiconductor device; or an on package semiconductor device (sample 202 is semiconductor package device in Fig. 2; See [0046]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system Ross and Grata by using sample corresponds to at least one of: a fabricated monolithic chip; a chiplet on wafer semiconductor device; a loose cut semiconductor device; or an on package semiconductor device, as taught by K in order to monitor health of sample (K; [0004]).
Regarding Claim 16, Ross in view of Grata teaches the computer-implemented method of claim 15. Ross further teaches wherein the at least one processor is configured to capture the electromagnetic image data (See page 630-633]).
Ross in view of Grata is silent about using an array of magnetometers configured as a linear polyaxial fluxgate gradiometer.
Littlefield teaches using an array of magnetometers configured as a linear polyaxial fluxgate gradiometer (it is inherent property of multi-element gradiometers are linear polyaxial fluxgate gradiometer; See [0027]; See [0026]-[0029]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Ross and Grata by using an array of magnetometers configured as a linear polyaxial fluxgate gradiometer, as taught by Littlefield in order to order to achieve maximum signal strength (Littlefield; [0022]).
Claim(s) 4-5, 11-12, 17-18 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Ross in view of Grata further in view of Ratliff et al. (Pub NO. US 2022/0371184 A1; hereinafter Ratliff).
Regarding Claim 4, Ross in view of Grata teaches the computing device of claim 1. Ross in view of Grata is silent about wherein the circuitry is configured to assess the sample using a vector processing engine that includes a machine learning model trained on a design file.
Ratliff further teaches regarding rasterized image wherein the circuitry is configured to assess the sample using a vector processing engine (See [0375]-[0376]) that includes a machine learning model trained on a design file (See [0330], [0438]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Ross by using circuitry is configured to assess the sample using a vector processing engine that includes a machine learning model trained on a design file, as taught by Ratliff in order to order to achieve multiple tasks to be performed in organized way (Ratliff; [0371-0372]]).
Regarding Claim 5, Ross in view of Grata in view of Ratliff teaches the computing device of claim 4. Ratliff further teaches wherein the vector processing engine is configured to generate a filtered vector point list (See [0536], [0553]) and the machine learning model is further trained on the filtered vector point list (See [0414], [0683]).
Regarding Claim 11, Ross in view of Grata teaches the system of claim 8. Ross further teaches wherein the computer-executable instructions cause the at least one physical processor to convert the electromagnetic image data to the multi-layer rasterized image (See page 630-633).
Ross in view of Grata is silent about using a vector processing engine that includes a machine learning model.
Ratliff further teaches regarding rasterized image using a vector processing engine (See [0375]-[0376]) that includes a machine learning model (See [0330], [0438]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Ross and Grata by using circuitry is configured to assess the sample using a vector processing engine that includes a machine learning model, as taught by Ratliff in order to order to achieve multiple tasks to be performed in organized way (Ratliff; [0371-0372]]).
Regarding Claim 12, Ross in view of Grata in view of Ratliff teaches the system of claim 11. Ratliff further teaches wherein the computer-executable instructions cause the at least one physical processor to generate a filtered vector point list (See [0536], [0553]) and the machine learning model is further trained on the filtered vector point list (See [0414], [0683]).
Regarding Claim 17, Ross in view of Grata teaches the computer-implemented method of claim 15. Ross further teaches wherein the at least one processor is configured to convert the electromagnetic image data to the multi-layer rasterized image (See page 630-633)
Ross in view of Grata is silent about using a vector processing engine that includes a machine learning model.
Ratliff further teaches regarding rasterized image using a vector processing engine (See [0375]-[0376]) that includes a machine learning model (See [0330], [0438]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Ross and Grata by using a vector processing engine that includes a machine learning model, as taught by Ratliff in order to order to achieve multiple tasks to be performed in organized way (Ratliff; [0371-0372]).
Regarding Claim 18, Ross in view of Grata in view of Ratliff teaches the computer-implemented method of claim 17. Ratliff further teaches wherein the vector processing engine is configured to generate a filtered vector point list (See [0536], [0553]) and the machine learning model is trained on the filtered vector point list (See [0414], [0683]).
Regarding Claim 21, Ross in view of Grata teaches the computing device of claim 1. Ross in view of Grata is silent about further comprising circuitry configured to compare the multi-layer rasterized image to a design file.
Ratliff further teaches regarding rasterized image comprising circuitry configured to compare the multi-layer rasterized image to a design file (See [0330], [0438]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Ross and Grata by using circuitry configured to compare the multi-layer rasterized image to a design file, as taught by Ratliff in order to order to achieve multiple tasks to be performed in organized way (Ratliff; [0371-0372]]).
Claim(s) 6 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ross in view of Grata further in view of K et al. (Pub NO. US 2023/0260332 A1; hereinafter K).
Regarding Claim 6, Ross in view of Grata teaches the computing device of claim 1. Ross in view of Grata is silent about wherein the sample corresponds to at least one of: a fabricated monolithic chip; a chiplet on wafer semiconductor device; a loose cut semiconductor device; or an on package semiconductor device.
K teaches wherein the sample corresponds to at least one of: a fabricated monolithic chip; a chiplet on wafer semiconductor device; a loose cut semiconductor device; or an on package semiconductor device (sample 202 is semiconductor package device in Fig. 2; See [0046]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Ratliff and Grata by using sample corresponds to at least one of: a fabricated monolithic chip; a chiplet on wafer semiconductor device; a loose cut semiconductor device; or an on package semiconductor device, as taught by K in order to monitor health of sample (K; [0004]).
Regarding Claim 19, Ross in view of Grata teaches the computer-implemented method of claim 15. Ross in view of Grata is silent about wherein the sample corresponds to at least one of: a fabricated monolithic chip; a chiplet on wafer semiconductor device; a loose cut semiconductor device; or an on package semiconductor device.
K teaches wherein the sample corresponds to at least one of: a fabricated monolithic chip; a chiplet on wafer semiconductor device; a loose cut semiconductor device; or an on package semiconductor device (sample 202 is semiconductor package device in Fig. 2; See [0046]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Ross and Grata by using sample corresponds to at least one of: a fabricated monolithic chip; a chiplet on wafer semiconductor device; a loose cut semiconductor device; or an on package semiconductor device, as taught by K in order to monitor health of sample (K; [0004]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZANNATUL FERDOUS whose telephone number is (571)270-0399. The examiner can normally be reached Monday through Friday 8am to 5pm (PST).
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/ZANNATUL FERDOUS/Examiner, Art Unit 2858
/LEE E RODAK/ Supervisory Patent Examiner, Art Unit 2858