Prosecution Insights
Last updated: May 29, 2026
Application No. 18/354,559

METHODS OF PACKAGING MICROELECTRONIC DEVICES UTILIZING PANELS AND RELATED TEMPORARY STRUCTURES

Non-Final OA §102§103
Filed
Jul 18, 2023
Priority
Apr 19, 2023 — provisional 63/497,134
Examiner
KIM, PAUL D
Art Unit
3729
Tech Center
3700 — Mechanical Engineering & Manufacturing
Assignee
Microchip Technology Inc.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
1357 granted / 1548 resolved
+17.7% vs TC avg
Moderate +7% lift
Without
With
+6.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
48 currently pending
Career history
1598
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
52.7%
+12.7% vs TC avg
§102
18.1%
-21.9% vs TC avg
§112
26.4%
-13.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1548 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This office action is a response to the election of species filed on 12/23/2025. Election/Restrictions Applicant’s election without traverse of Group II in the reply filed on 12/23/2025 is acknowledged. It is noted that the elected Group II is drawn to Fig. 2, which is appears to be the claims 21 and 23-26. Group I, drawn to Fig. 1, does not require a redistribution layer on a printed circuit panel, wherein the redistribution layer is electrically connected to vias of the printed circuit panel, and supporting a plurality of microelectronic dice on the redistribution layer. The requirement is still deemed proper and is therefore made FINAL. Claims 1-14, 22 and 27 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/23/2025. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: --METHOD OF PACKAGING MICROELECTRONIC DEVICES--. Claim Objections Claim 25 is objected to because of the following informalities: The phrase “comprising” as recited in line 1 appears to be –further comprising--. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 21, 22 and 25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lopez et al. (PGPub 2023/0411262 A1). Lopez et al. teach a process of packaging microelectronic devices, comprising steps of: forming a redistribution layer (779, Fig. 7B) on a printed circuit panel (773, Fig. 7A and 7B), wherein the redistribution layer electrically is connected to vias (777, Fig. 7B) of the printed circuit panel; supporting a plurality of microelectronic dice on the redistribution layer (paragraphs [0068]-[0071]); electrically connecting respective microelectronic dice (702) of the plurality of microelectronic dice to the redistribution layer as shown in Fig. 7D (paragraphs [0073]-[0074]); and singulating microelectronic device packages from the printed circuit panel, respective microelectronic device packages comprising at least one microelectronic die (700, Figs. 7F-7G) of the plurality of microelectronic dice and a portion of the printed circuit panel (paragraphs [0077]-[0078]). Re. claim 23: Electrically connecting respective microelectronic dice of the plurality of microelectronic dice to the redistribution layer comprises reflowing electrically conductive material extending from respective microelectronic dice of the plurality of microelectronic dice to the redistribution layer (see also paragraph [0074]). Re. claim 25: The plurality of microelectronic dice is placed in flip-chip orientations when supporting the plurality of microelectronic dice on the redistribution layer (see paragraph [0073]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 24 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Lopez et al. as applied to claim 21 above, and further in view of Koopmans (US PAT. 6,845,901). Lopez et al. teach all limitations as set forth above, but silent a laser toward the electrically conductive material to reflow the electrically conductive material (as per claim 23). Koopmans teaches a process of packaging microelectronic devices including a process of a laser toward a solder paste (equivalent with an electrically conductive material) to reflow the solder paste in order to deposit the solder paste (equivalent with an electrically conductive material) to the microelectronic devices (see also col. 2, lines 41-59). Therefore, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the claimed invention was made, to a person having ordinary skill in the art to modify a process of packaging microelectronic devices of Lopez et al. by reflowing electrically conductive material as taught by Koopmans in order to deposit the solder paste (equivalent with an electrically conductive material) to the microelectronic devices. Re. claim 26: Lopez et al. silent at least one via of the vias of the printed circuit panel is at least partially hollow. In light of the specification (paragraph [0085], The at least partially hollow vias 1906, and the associated tenting material 1912, may be formed utilizing any of the techniques and materials known in the art for such structures), it is generally known to the person skilled in the art that since such a modification would have been an obvious design consideration that is within the purview of one having ordinary skill in the art to provide the well-known benefit of obtaining a desirable microelectronic device. Since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable rangers involves only routine skill in the art. MPEP 2144.04 (il-A). The Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Tang et al. (PGPub 2023/0352850 A1), Haba et al. (US PAT. 10,211,160), and Chen et al. (PGPub 224/0120297 A1) are cited to further show the state of the art with respect to a process of packaging microelectronic devices. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL D KIM whose telephone number is (571)272-4565. The examiner can normally be reached Monday-Friday: 6:00 AM-2:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hong can be reached at 571-272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PAUL D KIM/Primary Examiner, Art Unit 3729
Read full office action

Prosecution Timeline

Jul 18, 2023
Application Filed
Mar 27, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
94%
With Interview (+6.6%)
2y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1548 resolved cases by this examiner. Grant probability derived from career allowance rate.

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