DETAILED ACTION
PLEASE NOTE: A new examiner, Amar Movva, has been assigned to this case. Applicant is advised to note the revised contact information in the Conclusion section of this office action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 8 and 10-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. US 2019/0371888 in view of Lee et al. US 12,156,395 and further in view of Yeong US 2021/0202758 .
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Regarding claim 1, Zhang et al. in Fig. 19 discloses a semiconductor device, comprising:
a plurality of first nanosheets 280 in a first region B;
a plurality of second nanosheets 270 in a second region A; and
a gate structure 219, 218 wrapping the first nanosheets 280 and the second nanosheets 270, wherein a first thickness of at least one of the first nanosheets 280 [0079] is smaller than a second thickness of at least one of the second nanosheets 270 [0069].
Zhang et al. does not expressly disclose a plurality of first nanosheets of a first conductive type and a plurality of second nanosheets of a second conductive type.
However, Lee et al. in Fig. 1 discloses nanosheet logic and SRAM devices that include a plurality of first nanosheets 108 of a first conductivity type, n-type and a plurality of second nanosheets 108 of a second conductive type, p-type. Lee et al. in col. 1, lines 5-45 further teaches that nanosheet devices reduce device footprint and improved control of channel current flow.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lee et al. in the device of Zhang et al. in order to provide increased device density and performance.
Furthermore, Zhang does not expressly disclose that the first and nanosheets are over a first and second fin wherein a top surface of the first fin is lower than a top surface of the second fin.
However, Yeong et al. in Fig. 16, a discloses nanosheet transistor with source/drain configuration with air gaps (133, fig. 16) between the source/drains and the nanosheets that forms a fin (90, fig. 16) underneath each nanosheet transistor (fig. 16, 1), wherein each fin has three top surfaces, one curved top surface bordering one source/drain (112, fig. 16), another curved top surface bordering the other source/drain (112, fig. 16), and flat top surface connecting the two curved top surfaces such that the first and nanosheets are over a first and second fin wherein a top surface of the first fin (curved top surface of one fin, fig. 16) is lower than a top surface of the second fin (flat top middle surface of another fin, 16).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lee et al. and Yeong et al. in the device of Zhang et al. in order to reduce parasitic capacitance ([0059] of Yeong).
Regarding claim 2, Zhang et al. in view of Lee et al. teaches the semiconductor device of claim 1. Zhang et al. teaches wherein the first thickness of each of the first nanosheets 280 [0079] is smaller than the second thickness of each of the second nanosheets 270 [0069].
Regarding claim 3, Zhang et al. in view of Lee et al. teaches the semiconductor device of claim 1. Zhang et al. teaches wherein a thickness difference between the first thickness [0079] and the second thickness [0069] is larger than 0.5 nm.
Regarding claim 4, Zhang et al. in view of Lee et al. teaches the semiconductor device of claim 1. Zhang et al. teaches wherein the at least one of the first nanosheets 280 is the topmost first nanosheet, and the at least one of the second nanosheets 270 is the topmost second nanosheet.
Regarding claim 5, Zhang et al. in view of Lee et al. teaches the semiconductor device of claim 1. Zhang et al. teaches wherein the at least one of the first nanosheets 280 is under the topmost first nanosheet, and the at least one of the second nanosheets 270 is under the topmost second nanosheet.
Regarding claim 6, Zhang et al. in view of Lee et al. teaches the semiconductor device of claim 1. Zhang et al. teaches wherein the at least one of the first nanosheets 280 comprises a first main portion having the first thickness and a first extension portion aside the first main portion and having a third thickness larger than the first thickness, and the at least one of the second nanosheets 270 comprises a second main portion having the second thickness and a second extension portion aside the second main portion and having a fourth thickness larger than the second thickness.
Regarding claim 8, Zhang et al. in Fig. 19 discloses a semiconductor device, comprising:
a plurality of first nanosheets 280 in a first region B, at least one of the first nanosheets comprising a first main portion and a first extension portion;
a plurality of second nanosheets 270 in a second region A, at least one of the second nanosheets comprising a second main portion and a second extension portion; and
a gate structure 218, 219 wrapping the first nanosheets 280 and the second nanosheets 270, wherein the first main portion has a first thickness, the second main portion has a second thickness, the first extension portion has a third thickness larger than the first thickness, and the second extension portion has a fourth thickness larger than the second thickness, wherein a first difference between the third thickness and the first thickness is larger than a second difference between the fourth thickness and the second thickness.
Zhang et al. does not expressly disclose a plurality of first nanosheets of a first conductive type and a plurality of second nanosheets of a second conductive type.
However, Lee et al. in Fig. 1 discloses nanosheet logic and SRAM devices that include a plurality of first nanosheets 108 of a first conductivity type, n-type and a plurality of second nanosheets 108 of a second conductive type, p-type. Lee et al. in col. 1, lines 5-45 further teaches that nanosheet devices reduce device footprint and improved control of channel current flow.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lee et al. in the device of Zhang et al. in order to provide increased device density and performance.
Furthermore, Zhang does not expressly disclose that the first and nanosheets are over a first and second fin wherein a top surface of the first fin is lower than a top surface of the second fin.
However, Yeong et al. in Fig. 16, a discloses nanosheet transistor with source/drain configuration with air gaps (133, fig. 16) between the source/drains and the nanosheets that forms a fin (90, fig. 16) underneath each nanosheet transistor (fig. 16, 1), wherein each fin has three top surfaces, one curved top surface bordering one source/drain (112, fig. 16), another curved top surface bordering the other source/drain (112, fig. 16), and flat top surface connecting the two curved top surfaces such that the first and nanosheets are over a first and second fin wherein a top surface of the first fin (curved top surface of one fin, fig. 16) is lower than a top surface of the second fin (flat top middle surface of another fin, 16).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lee et al. and Yeong et al. in the device of Zhang et al. in order to reduce parasitic capacitance ([0059] of Yeong).
Regarding claim 10, Zhang et al. in view of Lee et al. teaches the semiconductor device of claim 8. Zhang et al. teaches wherein the at least one of the first nanosheets 280 is the topmost first nanosheet, and the at least one of the second nanosheets 270 is the topmost second nanosheet.
Regarding claim 11, Zhang et al. in view of Lee et al. teaches the semiconductor device of claim 8. Zhang et al. teaches wherein the at least one of the first nanosheets 280 is the topmost first nanosheet, and the at least one of the second nanosheets 270 is the topmost second nanosheet.
Regarding claim 12, Zhang et al. in view of Lee et al. teaches the semiconductor device of claim 8. Zhang et al. teaches wherein the at least one of the first nanosheets 280 is under the topmost first nanosheet, and the at least one of the second nanosheets 270 is under the topmost second nanosheet.
Regarding claim 13, Zhang et al. in view of Lee et al. teaches the semiconductor device of claim 8. Zhang et al. teaches wherein the semiconductor device of claim 8 further comprising:
first spacers 206,205 on a sidewall of the gate structure wrapping the first nanosheets 280, wherein the first extension portion of the at least one of the first nanosheets is disposed between the first spacers; and
second spacers 206,205 on a sidewall of the gate structure wrapping the second nanosheets 270, wherein the second extension portion of the at least one of the second nanosheets is disposed between the second spacers, wherein one of the first spacers is a single element, an inner sidewall of the one of the first spacers is substantially flush with an interface between the first main portion and the first extension portion (205 is flush with the interface between the thinner and thicker portions of the nanosheet), and an outer sidewall of the one of the first spacers is substantially flush with an outer sidewall of the first extension portion (205 is flush with the interface between the thinner and thicker portions of the nanosheet).
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. US 2019/0371888 in view of Lee et al. US 12,156,395 and further in view of Yeong US 2021/0202758 and further in view of Chang US 2022/0238385 .
Regarding claim 27, Zhang/Lee/Chang discloses the semiconductor device of claim 1 but does not disclose an insulating region between the first fin and the second fin, wherein a top surface of the insulating region is lower than the top surface of the first fin and the top surface of the second fin.
Chang, however, discloses a semiconductor device (fig. 6C) with an insulating region (222, fig. 6C) between the first fin and the second fin (fins extending from 202, fig. 6C) , wherein a top surface of the insulating region is lower than the top surface of the first fin and the top surface of the second fin (fig. 6C)
It would have been obvious to one of ordinary skill in the art before the time of filing to have used Chang’s insulating layer in Zhang’s device in order to provide a means to isolate one fin from another to avoid cross-talk.
Claim(s) 7, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. in view of Lee et al. ‘395 as applied to claims 1 and 8 above, and further in view of Lee et al. 2019/0378911 and further in view of Yeong US 2021/0202758.
Regarding claim 7, Zhang et al. in view of Lee et al. teaches the semiconductor device of claim 1 but does not expressly teach wherein the semiconductor device further comprising a cap layer and an interlayer respectively surrounding the at least one of the first nanosheets, wherein the cap layer is disposed between the at least one of the first nanosheets and the interlayer, and the interlayer is disposed between the cap layer and the gate structure.
However, Lee et al. ‘911 in Fig. 3 teaches a semiconductor device that includes multiple layers that are used to control the threshold voltage of the semiconductor device comprising a layer 137 (e.g. cap layer) and an interlayer 130 respectively surrounding at least one of a first nanosheets 210, wherein the cap layer 137 is disposed between the at least one of the first nanosheets 210 and the interlayer 130, and the interlayer 130 is disposed between the cap layer 137 and the gate structure 122.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lee et al. ‘911 in the device of Zhang et al. and Lee et al. ‘395 in order to increase device performance.
Regarding claim 14, Zhang et al. in view of Lee et al. teaches the semiconductor device of claim 8 but does not expressly teach wherein the semiconductor device further comprising a cap layer and an interlayer respectively surrounding the at least one of the first nanosheets, wherein the cap layer is disposed between the at least one of the first nanosheets and the interlayer, and the interlayer is disposed between the cap layer and the gate structure.
However, Lee et al. ‘911 in Fig. 3 teaches a semiconductor device that includes multiple layers that are used to control the threshold voltage of the semiconductor device comprising a layer 137 (e.g. cap layer) and an interlayer 130 respectively surrounding at least one of a first nanosheets 210, wherein the cap layer 137 is disposed between the at least one of the first nanosheets 210 and the interlayer 130, and the interlayer 130 is disposed between the cap layer 137 and the gate structure 122.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lee et al. ‘911 in the device of Zhang et al. and Lee et al. ‘395 in order to increase device performance.
Claim(s) 21-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. US 2019/0371888 in view of Lee et al. US 12,156,395, and further in view of Lee et al. 2019/0378911 and further in view of Yeong US 2021/0202758.
Regarding claim 21, Zhang et al. in Fig. 19 discloses a semiconductor device, comprising:
a plurality of first nanosheets 280 in a first region B;
a plurality of second nanosheets 270 in a second region A;
a gate structure 218, 219 wrapping the first nanosheets 280 and the second nanosheets 270.
Zhang et al. does not expressly disclose a plurality of first nanosheets of a first conductive type and a plurality of second nanosheets of a second conductive type.
However, Lee et al. ‘395 in Fig. 1 discloses nanosheet logic and SRAM devices that include a plurality of first nanosheets 108 of a first conductivity type, n-type and a plurality of second nanosheets 108 of a second conductive type, p-type. Lee et al. ‘395 in col. 1, lines 5-45 further teaches that nanosheet devices reduce device footprint and improved control of channel current flow.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lee et al. ‘395 in the device of Zhang et al. in order to provide increased device density and performance.
Zhang et al. in view of Lee et al. ‘395 does not expressly teach wherein the semiconductor device further comprising a cap layer and an interlayer respectively surrounding the at least one of the first nanosheets, wherein the cap layer is disposed between the at least one of the first nanosheets and the interlayer, and the interlayer is disposed between the cap layer and the gate structure; and a second interlayer disposed between the cap layer and the second nanosheets, wherein the second interlayer interfaces with the at least one of the second nanosheets and the gate structure.
However, Lee et al. ‘911 in Fig. 3 teaches a semiconductor device that includes multiple layers that are used to control the threshold voltage of the semiconductor device comprising a layer 137,136 (e.g. cap layer) and a first interlayer 130 respectively surrounding at least one of a first nanosheets 210, wherein the cap layer 137,136 is disposed between the at least one of the first nanosheets 210 and the first interlayer 130, and the first interlayer 130 is disposed between the cap layer 137,136 and the gate structure 120, and a second interlayer 130 disposed between the cap layer 137,136 and a second nanosheets 210, wherein the second interlayer 130 interfaces with the at least one of the second nanosheets 210 and the gate structure 120.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lee et al. ‘911 in the device of Zhang et al. and Lee et al. ‘395 in order to increase device performance.
However, Yeong et al. in Fig. 16, a discloses nanosheet transistor with source/drain configuration with air gaps (133, fig. 16) between the source/drains and the nanosheets that forms a fin (90, fig. 16) underneath each nanosheet transistor (fig. 16, 1), wherein each fin has three top surfaces, one curved top surface bordering one source/drain (112, fig. 16), another curved top surface bordering the other source/drain (112, fig. 16), and flat top surface connecting the two curved top surfaces such that the first and nanosheets are over a first and second fin wherein a top surface of the first fin (curved top surface of one fin, fig. 16) is lower than a top surface of the second fin (flat top middle surface of another fin, 16).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lee et al. and Yeong et al. in the device of Zhang et al. in order to reduce parasitic capacitance ([0059] of Yeong).
Regarding claim 22, Zhang et al. in view of Lee et al. ‘395 and further in view of Lee et al. ‘911 teaches the semiconductor device of claim 21. Zhang et al. teaches wherein the first thickness of each of the first nanosheets 280 [0079] is smaller than the second thickness of each of the second nanosheets 270 [0069].
Regarding claim 23, Zhang et al. in view of Lee et al. ‘395 and further in view of Lee et al. ‘911 teaches the semiconductor device of claim 21. Lee et al. ‘911 in Fig. 3 teaches wherein the interlayer 130 interfaces with the cap layer 137,136 and the gate structure 120, in a cross- sectional view, the first cap layer 137,136 interfaces with the at least one of the first nanosheets 110/210 and the first interlayer, the first interlayer 130 interfaces with the first cap layer 136,137 and the gate structure 121, the second interlayer 137,136 interfaces with the at least one of the second nanosheets and the gate structure 1212, and the gate structure continuously wraps the first nanosheets and the second nanosheets (fig. 2).
Regarding claim 24, Zhang et al. in view of Lee et al. ‘395 and further in view of Lee et al. ‘911 teaches the semiconductor device of claim 21. Lee et al. ‘911 in Fig. 3 teaches wherein the gate structure 120 includes a gate dielectric layer 136 and a gate electrode 122, and the first interlayer 137 and the second interlayer 137 interface with the gate dielectric layer 136 respectively.
Regarding claim 25, Zhang et al. in view of Lee et al. ‘395 and further in view of Lee et al. ‘911 teaches the semiconductor device of claim 21. Zhang et al. teaches the semiconductor device further comprising: first spacers 206 on a sidewall of the gate structure wrapping the first nanosheets. Zhang et al. in view of Lee et al. ‘395 and further in view of Lee et al. ‘911 do not expressly teach wherein the at least one of the first nanosheets has a first thickness, the first cap layer has a second thickness, the first interlayer has a third thickness, and a vertical distance between the first spacers is larger than a total thickness of the first thickness, twice the second thickness and twice the third thickness.
Notwithstanding, one of ordinary skill in the art before the effective filing date of the claimed invention would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(IV)(B).
Regarding claim 26, Zhang et al. in view of Lee et al. ‘395 and further in view of Lee et al. ‘911 teaches the semiconductor device of claim 21. Zhang et al. in Fig. 19 teaches wherein an interface between the gate structure 219 and the at least one of the first nanosheets 280 is at a height between adjacent two first spacers 206 vertically stacked.
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference combination (not the inclusion of new prior art, e.g. Yeong) with respect to applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMAR MOVVA whose telephone number is (571)272-9009. The examiner can normally be reached Monday-Friday 9AM-5PM.
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/AMAR MOVVA/Primary Examiner, Art Unit 2898
