Non-Final Rejection
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-10 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 8-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0200233 (“Noda”).
It is noted that Noda was published less than one year prior to the effective filing date and has a common inventor and assignee with the present application. However, the reference has an additional inventor that is not shared with this application, therefore it is not apparent at this time that any 102(b)(1) exception applies. See MPEP 2153.01(a).
Regarding claim 1, Noda discloses in Fig. 1 and the discussion thereof starting at [0020] a light-emitting device 100, comprising:
a light-emitting unit 80 including a first semiconductor layer 86, a second semiconductor layer 88 having a conductivity type different from a conductivity type of the first semiconductor layer, and a light-emitting layer 87 provided between the first semiconductor layer and the second semiconductor layer (e.g. [0046]);
an insulating layer 50,60 that covers the light-emitting unit; and
a conductive layer 52,54 to which a predetermined potential is applied, the conductive layer being provided in the insulating layer and electrically separated from the light-emitting unit (particularly the center one, which is attached to the gate 36. It is understood that in a transistor the gate is electrically separate from the source and drain and therefore is not electrically connected to the light emitting unit 80).
Regarding claim 8, the Noda device may be a projector. [0002].
Regarding claims 9-10, the Noda device may be part of a display, or part of a display in smart glasses (i.e. head mounted display). [0106].
Claims 1, 8, and 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2023/0369828 (“Hong”).
Regarding claim 1, Hong discloses in Fig. 1 and the discussion thereof a light-emitting device 100, comprising: a light-emitting unit 10 including a first semiconductor layer 14, a second semiconductor layer 16 having a conductivity type different from a conductivity type of the first semiconductor layer, and a light-emitting layer 15 provided between the first semiconductor layer and the second semiconductor layer (Fig. 2, [0041]); an insulating layer 8 that covers the light-emitting unit; and a conductive layer 6 to which a predetermined potential is applied, the conductive layer being provided in the insulating layer and electrically separated from the light-emitting unit (separated by insulators 5,8, and it is a gate electrode which is known to be separate from the drain 4 that drives the light emitting unit).
Regarding claims 8-9, the device may be in a projector, or a display. [0036].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Noda.
Regarding claim 2, Noda further discloses a substrate 10;
a first electrode that is provided at the substrate and electrically coupled to the first semiconductor layer (either 70/32, or the bottom part of the rightmost interconnector 52 that is connected to that side just above 32);
a second electrode 89 that is provided on a side of the light-emitting unit opposite to the substrate, and electrically coupled to the second semiconductor layer; and a wiring 90 that is provided at the insulating layer and electrically coupled to the second electrode,
wherein the first semiconductor layer 86 is provided between the substrate 10 and the light-emitting layer 87,
the conductive layer is provided between the substrate and the wiring (here we can consider the center interconnection 52 as the conductive layer, it is above the substrate and below the wiring),
It is not disclosed that the predetermined potential is a potential between a potential applied to the first electrode and a potential applied to the wiring, same as the potential applied to the first electrode, or same as the potential applied to the wiring. But basically, these values are completely within the ability of the skilled artisan to choose as a routine optimization within the prior art conditions. See MPEP 2144.05 II. The amounts of potential are result effective variables, as the potential at the conductor is the gate potential of the driving transistor, and the potential at the electrodes affects the actual potential that goes into the light emitting device, directly impacting the light output. These can be adjusted as needed to change the light output, to get the transistor over or under threshold as warranted, change the saturation, etc. Even getting more specific, there are times when a person skilled in the art might want the gate to be the same as the drain, i.e. make it the same as the first electrode, to force saturation. Accordingly, the designer may determine what levels to make the potential at these electrodes, and routine optimization could reasonably yield results within/at the claimed ranges or values.
Regarding claim 3, the light emitting unit has a plurality of columnar portions 85, each of the plurality of columnar portions includes the first semiconductor layer, the second semiconductor layer, and the light-emitting layer.
Regarding claim 4, the conductive layer 52 is at the top of layer 50, and so is the wiring layer 90. It is not at the bottom right adjacent to the substrate. So, a distance between the conductive layer and the wiring is shorter than a distance between the conductive layer and the substrate.
Regarding claim 5, as seen in Fig. 1 the conductive layer, even if 52, is on the opposite side of light emitting layer 87 from substrate 10 in the stacking direction, i.e. at least part of it is above layer 87.
Regarding claim 7, one can additionally say that the insulting layer includes a first layer 40 between the between substrate and conductive layer, and second layer 50/60 between conductive layer and wiring. The dielectric constant of the second layer 50/60 (which is silcon oxide, [0030]) is smaller than a dielectric constant of the first layer 40 (which may be silicon nitride, [0028]).
Claims 2-5, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Hong.
Regarding claim 2, Hong discloses a substrate 2; a first electrode 4 that is provided at the substrate and electrically coupled to the first semiconductor layer; a second electrode 30 that is provided on a side of the light-emitting unit opposite to the substrate, and electrically coupled to the second semiconductor layer; and a wiring 40 that is provided at the insulating layer and electrically coupled to the second electrode, wherein the first semiconductor layer 14 is provided between the substrate 2 and the light-emitting layer 15 (see Fig. 2), the conductive layer 6 is provided between the substrate 2 and the wiring 40 (as it goes far lower that wiring 40),
It is not disclosed that the predetermined potential is a potential between a potential applied to the first electrode and a potential applied to the wiring, same as the potential applied to the first electrode, or same as the potential applied to the wiring. But basically, these values are completely within the ability of the skilled artisan to choose as a routine optimization within the prior art conditions. See MPEP 2144.05 II. The amounts of potential are result effective variables, as the potential at the conductor is the gate potential of the driving transistor, and the potential at the electrodes affects the actual potential that goes into the light emitting device, directly impacting the light output. These can be adjusted as needed to change the light output, to get the transistor over or under threshold as warranted, change the saturation, etc. Even getting more specific, there are times when a person skilled in the art might want the gate to be the same as the drain, i.e. make it the same as the first electrode, to force saturation. Accordingly, the designer may determine what levels to make the potential at these electrodes, and routine optimization could reasonably yield results within/at the claimed ranges or values.
Regarding claim 3, as seen in Fig. 2 the light-emitting unit includes a plurality of columnar portions, and each of the plurality of columnar portions includes the first semiconductor layer, the second semiconductor layer, and the light-emitting layer.
Regarding claim 4, the conductive layer 6 is at the top of layer 8, and so is the wiring layer 40. It is not at the bottom right adjacent to the substrate. So, a distance between the conductive layer and the wiring is shorter than a distance between the conductive layer and the substrate.
Regarding claim 5, the conductive layer 6 is above the light emitting layer in the device, so it is provided on an opposite side of the light-emitting layer from the substrate, when viewed in a stacking direction of the first semiconductor layer and the light-emitting layer.
Regarding claim 10, Hong does not explicitly say that the device may be in a head-mounted display. It does disclose it may be in a wearable display device such as augmented or virtual reality device. [0036]. It would have been obvious to a person of ordinary skill in the art that these are generally head mounted to easily allow the display to be located directly in front of the user’s eyes.
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
There is not taught or disclosed in the prior art the light emitting device of claim 2, wherein the conductive layer surrounds the light-emitting unit when viewed in a stacking direction of the first semiconductor layer and the light-emitting layer. Given what these layers do in Hong and Noda there is no reason to make them surround the light-emitting unit.
Conclusion
Two other references with general similarities are cited, but do not have the claimed conductive layer.
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/JAMES A MENEFEE/Primary Examiner, Art Unit 2828