DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1 and 14.
Pending: 1-20.
Withdrawn: 4-7 and 14-20.
Information Disclosure Statement
Applicant’s IDS(s) submitted on 7/19/2023, 2/20/2024,4/25/2024,6/17/2025, and 7/14/2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record.
Election/Restrictions
Applicant’s election without traverse of Group 1 Species 2 (fig. 28A-28B) claim 1-3 and 8-13 in the reply filed on 1/28/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 and 8-11 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Nagata et al., US patent 10615172 B2.
Re: Independent Claim 1, Nagata discloses an alternating stack (132/232 and 146/246, fig. 26C) of insulating layers and composite layers, wherein each of the composite layers comprises a respective laterally alternating sequence of electrically conductive layers (146/246, fig. 26C) and dielectric material strips (132/232, fig. 26C), wherein the dielectric material strips (132/232, fig. 26C) laterally extend along a first horizontal direction (hd1, fig. 26B);
memory openings (149, fig. 23D) vertically extending through the alternating stack (132/232 and 146/246, fig. 26C); and
memory opening fill structures (58, fig. 26c) located in the respective memory openings (149, fig. 23D), wherein each memory opening fill structure (58, fig. 26c) includes a respective vertical stack of memory elements and a respective vertical semiconductor channel (60, fig. 25C);
wherein:
each of the electrically conductive layers (146/246, fig. 26C) comprises a respective laterally-extending seam (146 and 246 in contact with 58, fig. 26C);
a first subset (first set of 58 bottom right corner, as shown in fig. 26B) of the memory opening fill structures (58, fig. 26c) is in direct contact with a respective subset of the seams (146/246 in between two fill structure 58) of the electrically conductive layers (146/246, fig. 26C); and
a second subset (second set of 58 above first set separated by 76, as shown in fig. 26B) of the memory opening fill structures (58, fig. 26c) is not in direct contact with any of the seams (146/246 in between two fill structure 58) of the electrically conductive layers (146/246, fig. 26C).
Re: Claim 2, Nagata disclose(s) all the limitations of claim 1 on which this claim depends. Nagata further discloses: the first subset (first set of 58 bottom right corner, as shown in fig. 26B) of the memory opening fill structures (58, fig. 26c) is located within first rows of the memory openings (149, fig. 23D) that laterally extend along the first horizontal direction (hd1, fig. 26B);
the second subset (second set of 58 above first set separated by 76, as shown in fig. 26B) of the memory opening fill structures (58, fig. 26c) is located within second rows of the memory openings (149, fig. 23D) that laterally extend along the first horizontal direction (hd1, fig. 26B); and
the first rows and the second rows are interlaced along a second horizontal direction (hd2, fig. 26B) that is perpendicular to the first horizontal direction (hd1, fig. 26B).
Re: Claim 3, Nagata disclose(s) all the limitations of claim 1 on which this claim depends. Nagata further discloses: wherein a subset of the memory openings (149, fig. 23D) comprises isolation openings (76, fig. 26A-26D) which are adjoined to a vertical stack of a respective subset of the dielectric material strips (132/232, fig. 26C).
Re: Claim 8, Nagata disclose(s) all the limitations of claim 2 on which this claim depends. Nagata further discloses: finned dielectric wall structures (76, fig. 26B).
Re: Claim 9, Nagata disclose(s) all the limitations of claim 8 on which this claim depends. Nagata further discloses: wherein each laterally neighboring pair of the electrically conductive layers (146/246, fig. 26C) is laterally spaced apart from each other along a second horizontal direction (hd2, fig. 26B) that is perpendicular to the first horizontal direction (hd1, fig. 26B) by a respective one of the finned dielectric wall (76, fig. 26B) structures, and adjacent memory blocks are laterally isolated from each other by the respective one of the finned dielectric wall (76, fig. 26B) structures.
Re: Claim 10, Nagata disclose(s) all the limitations of claim 8 on which this claim depends. Nagata further discloses: each of the finned dielectric wall (76, fig. 26B) structures comprises dielectric pillars (79, fig. 25C; column 42, lines 62-64) containing laterally protruding fins that are separated from each other along a vertical direction;
the dielectric material strips (132/232, fig. 26C) are formed by the fins of adjacent ones of the dielectric pillars (79, fig. 25C; column 42, lines 62-64) that laterally contact each other; and
each of the dielectric material strips (132/232, fig. 26C) comprises a respective row of vertically-straight and laterally-convex surface segments (shown in laterally view 76 has a convex corner from the circular pattern) that are adjoined to each other and contact a set of vertically-straight and laterally-concave (shown in laterally view 76 has a concave from the circular pattern) surface segments of a respective one of the electrically conductive layers (146/246, fig. 26C).
Re: Claim 11, Nagata disclose(s) all the limitations of claim 8 on which this claim depends. Nagata further discloses: each of the finned dielectric wall (76, fig. 26B) structures continuously extends from a bottommost surface of the alternating stack (132/232 and 146/246, fig. 26C) to a topmost surface of the alternating stack (132/232 and 146/246, fig. 26C); and
each of finned dielectric wall (76, fig. 26B) structures is not in direct contact (as shown in figure 24C layer 125 is between the dielectric wall and laterally conductive seams 146 and 246) with any of the laterally-extending seams.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12 and 13 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Nagata et al., US patent 10615172 B2; in view of Hinoue et al., US PG pub. 20190287982 A1.
Re: Claim 12, Nagata discloses all the limitations of claim 8 on which this claim depends. Nagata is silent regarding: metallic barrier liner wherein each of the electrically conductive layers (146/246, fig. 26C) comprises a combination of a respective metallic barrier liner and a respective metallic fill material portion containing a respective one of the seams; and
an entirety of each interface between the electrically conductive layers (146/246, fig. 26C) and the second subset (second set of 58 above first set separated by 76, as shown in fig. 26B) of the memory opening fill structures (58, fig. 26c) consists of an interface between a respective one of the metallic barrier liners and a respective memory opening fill structure (58, fig. 26c) of the second subset (second set of 58 above first set separated by 76, as shown in fig. 26B) of the memory opening fill structures (58, fig. 26c).
Hinoue discloses the electrically conductive layer (46B, fig. 14B) comprises a metallic barrier liner (46A, fig. 14B; ¶0104).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include metallic barrier liner surround the conductive layers since the barrier liner can preventing charge leakage reducing inter-cell interference thereby improving performance and reliability.
Re: Claim 13, Nagata discloses all the limitations of claim 12 on which this claim depends. Nagata is silent regarding: metallic barrier liner wherein each interface between the electrically conductive layers (146/246, fig. 26C) and the first subset (first set of 58 bottom right corner, as shown in fig. 26B) of the memory opening fill structures (58, fig. 26c) comprises:
an interface between a respective one of the metallic barrier liners and a respective memory opening fill structure (58, fig. 26c) of the first subset (first set of 58 bottom right corner, as shown in fig. 26B) of the memory opening fill structures (58, fig. 26c); and
an interface between a respective one of the metallic fill material portions and the respective memory opening fill structure (58, fig. 26c) of the first subset (first set of 58 bottom right corner, as shown in fig. 26B) of the memory opening fill structures (58, fig. 26c).
Hinoue discloses the electrically conductive layer (46B, fig. 14B) comprises a metallic barrier liner (46A, fig. 14B; ¶0104).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include metallic barrier liner surround the conductive layers since the barrier liner can preventing charge leakage reducing inter-cell interference thereby improving performance and reliability.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Lu et al., US PG pub. 20170236896 A1”) Discloses an alternating stack of insulating layers and spacer material layers is formed over a substrate. A first insulating cap layer is formed over the alternating stack. A plurality of memory stack structures is formed through the alternating stack and the first insulating cap layer. The first insulating cap layer is vertically recessed, and a conformal material layer is formed over protruding portions of the memory stack structures. Spacer portions are formed by an anisotropic etch of the conformal material layer such that the sidewalls of the spacer portions having protruding portions. A self-aligned separator trench with non-uniform sidewalls having protruding portions is formed through an upper portion of the alternating stack by etching the upper portions of the alternating stack between the spacer portions.
* (“Ariyoshi US patent 10115681 B1”) discloses semiconductor die includes a pair of first alternating stacks of first portions of insulating layers and electrically conductive layers located over a semiconductor substrate, groups of memory stack structures vertically extending through a respective one of the pair of the first alternating stacks, a pair of second alternating stacks of second portions of the insulating layers and dielectric material layers laterally adjoined to a respective one of the first alternating stacks, such that each second portion of the insulating layers is connected to a respective one of the first portions of the insulating layers, and at least one seal ring structure laterally enclosing, and laterally spaced from, the pair of first alternating stacks, and contacting at least a first sidewall of each of the pair of second alternating stacks.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898