DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1.
Pending: 1-13 and 21-27.
Newly: 21-27.
Canceled: 14-20.
Withdrawn: 4-7.
Response to Arguments
Applicant's arguments filed 7/7/2026 have been fully considered but they are not persuasive. With regard to claim 1 Applicant argue reference Nagata et al., ‘172 fail to teach “electrically conductive layers comprises a respective laterally-extending seam”, Examiner disagree, as shown in figure 26C that the vertical via 58 is formed in trench 149M as shown in figure 23C, via forming in a trench contact that intersects an alternating stack of conductive and insulating layers create a seam, a seam which is a line along two pieces of material that formed together in this case layer 146/246 is in contact with layer 58 formed a seam. Therefore, reference Nagata et al., does teach this limitation.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 and 8-11 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Nagata et al., US patent 10615172 B2.
Re: Independent Claim 1, Nagata discloses an alternating stack (132/232 and 146/246, fig. 26C) of insulating layers and composite layers, wherein each of the composite layers comprises a respective laterally alternating sequence of electrically conductive layers (146/246, fig. 26C) and dielectric material strips (132/232, fig. 26C), wherein the dielectric material strips (132/232, fig. 26C) laterally extend along a first horizontal direction (hd1, fig. 26B);
memory openings (149, fig. 23D) vertically extending through the alternating stack (132/232 and 146/246, fig. 26C); and
memory opening fill structures (58, fig. 26c) located in the respective memory openings (149, fig. 23D), wherein each memory opening fill structure (58, fig. 26c) includes a respective vertical stack of memory elements and a respective vertical semiconductor channel (60, fig. 25C);
wherein:each of the electrically conductive layers (146/246, fig. 26C) comprises a respective laterally-extending seam (146 and 246 in contact with 58, fig. 26C);
a first subset (first set of 58 bottom right corner, as shown in fig. 26B) of the memory opening fill structures (58, fig. 26c) is in direct contact with a respective subset of the seams (146/246 in between two fill structure 58) of the electrically conductive layers (146/246, fig. 26C); and
a second subset (second set of 58 above first set separated by 76, as shown in fig. 26B) of the memory opening fill structures (58, fig. 26c) is not in direct contact with any of the seams (146/246 in between two fill structure 58) of the electrically conductive layers (146/246, fig. 26C).
Re: Claim 2, Nagata disclose(s) all the limitations of claim 1 on which this claim depends. Nagata further discloses: the first subset (first set of 58 bottom right corner, as shown in fig. 26B) of the memory opening fill structures (58, fig. 26c) is located within first rows of the memory openings (149, fig. 23D) that laterally extend along the first horizontal direction (hd1, fig. 26B);
the second subset (second set of 58 above first set separated by 76, as shown in fig. 26B) of the memory opening fill structures (58, fig. 26c) is located within second rows of the memory openings (149, fig. 23D) that laterally extend along the first horizontal direction (hd1, fig. 26B); and
the first rows and the second rows are interlaced along a second horizontal direction (hd2, fig. 26B) that is perpendicular to the first horizontal direction (hd1, fig. 26B).
Re: Claim 3, Nagata disclose(s) all the limitations of claim 1 on which this claim depends. Nagata further discloses: wherein a subset of the memory openings (149, fig. 23D) comprises isolation openings (76, fig. 26A-26D) which are adjoined to a vertical stack of a respective subset of the dielectric material strips (132/232, fig. 26C).
Re: Claim 8, Nagata disclose(s) all the limitations of claim 2 on which this claim depends. Nagata further discloses: finned dielectric wall structures (76, fig. 26B).
Re: Claim 9, Nagata disclose(s) all the limitations of claim 8 on which this claim depends. Nagata further discloses: wherein each laterally neighboring pair of the electrically conductive layers (146/246, fig. 26C) is laterally spaced apart from each other along a second horizontal direction (hd2, fig. 26B) that is perpendicular to the first horizontal direction (hd1, fig. 26B) by a respective one of the finned dielectric wall (76, fig. 26B) structures, and adjacent memory blocks are laterally isolated from each other by the respective one of the finned dielectric wall (76, fig. 26B) structures.
Re: Claim 10, Nagata disclose(s) all the limitations of claim 8 on which this claim depends. Nagata further discloses: each of the finned dielectric wall (76, fig. 26B) structures comprises dielectric pillars (79, fig. 25C; column 42, lines 62-64) containing laterally protruding fins that are separated from each other along a vertical direction;
the dielectric material strips (132/232, fig. 26C) are formed by the fins of adjacent ones of the dielectric pillars (79, fig. 25C; column 42, lines 62-64) that laterally contact each other; and
each of the dielectric material strips (132/232, fig. 26C) comprises a respective row of vertically-straight and laterally-convex surface segments (shown in laterally view 76 has a convex corner from the circular pattern) that are adjoined to each other and contact a set of vertically-straight and laterally-concave (shown in laterally view 76 has a concave from the circular pattern) surface segments of a respective one of the electrically conductive layers (146/246, fig. 26C).
Re: Claim 11, Nagata disclose(s) all the limitations of claim 8 on which this claim depends. Nagata further discloses: each of the finned dielectric wall (76, fig. 26B) structures continuously extends from a bottommost surface of the alternating stack (132/232 and 146/246, fig. 26C) to a topmost surface of the alternating stack (132/232 and 146/246, fig. 26C); and
each of finned dielectric wall (76, fig. 26B) structures is not in direct contact (as shown in figure 24C layer 125 is between the dielectric wall and laterally conductive seams 146 and 246) with any of the laterally-extending seams.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12 and 13 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Nagata et al., US patent 10615172 B2; in view of Hinoue et al., US PG pub. 20190287982 A1.
Re: Claim 12, Nagata discloses all the limitations of claim 8 on which this claim depends. Nagata is silent regarding: metallic barrier liner wherein each of the electrically conductive layers (146/246, fig. 26C) comprises a combination of a respective metallic barrier liner and a respective metallic fill material portion containing a respective one of the seams; and
an entirety of each interface between the electrically conductive layers (146/246, fig. 26C) and the second subset (second set of 58 above first set separated by 76, as shown in fig. 26B) of the memory opening fill structures (58, fig. 26c) consists of an interface between a respective one of the metallic barrier liners and a respective memory opening fill structure (58, fig. 26c) of the second subset (second set of 58 above first set separated by 76, as shown in fig. 26B) of the memory opening fill structures (58, fig. 26c).
Hinoue discloses the electrically conductive layer (46B, fig. 14B) comprises a metallic barrier liner (46A, fig. 14B; ¶0104).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include metallic barrier liner surround the conductive layers since the barrier liner can preventing charge leakage reducing inter-cell interference thereby improving performance and reliability.
Re: Claim 13, Nagata discloses all the limitations of claim 12 on which this claim depends. Nagata is silent regarding: metallic barrier liner wherein each interface between the electrically conductive layers (146/246, fig. 26C) and the first subset (first set of 58 bottom right corner, as shown in fig. 26B) of the memory opening fill structures (58, fig. 26c) comprises:
an interface between a respective one of the metallic barrier liners and a respective memory opening fill structure (58, fig. 26c) of the first subset (first set of 58 bottom right corner, as shown in fig. 26B) of the memory opening fill structures (58, fig. 26c); and
an interface between a respective one of the metallic fill material portions and the respective memory opening fill structure (58, fig. 26c) of the first subset (first set of 58 bottom right corner, as shown in fig. 26B) of the memory opening fill structures (58, fig. 26c).
Hinoue discloses the electrically conductive layer (46B, fig. 14B) comprises a metallic barrier liner (46A, fig. 14B; ¶0104).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include metallic barrier liner surround the conductive layers since the barrier liner can preventing charge leakage reducing inter-cell interference thereby improving performance and reliability.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Tsutsumi et al., US Patent 10192878 B1”) Discloses sacrificial memory opening fill structures are formed through an alternating stack of insulating layers and sacrificial material layers. A drain select level isolation trench extending through drain select level sacrificial material layers is formed employing a combination of a photoresist layer including a linear opening and a pair of rows of sacrificial memory opening fill structures as an etch mask. Sacrificial spacers are formed on sidewalls of the drain select level isolation trench. A drain select level isolation dielectric structure is formed in a remaining volume of the drain select level isolation trench. The sacrificial memory opening fill structures are replaced with memory stack structures. The sacrificial material layers and the sacrificial spacers are replaced with a conductive material to form electrically conductive layers and conductive connector spacers. The drain select level isolation dielectric structure is self-aligned to the memory stack structures and divides drain select level electrically conductive layers.
* (“Cui et al., US PG pub. 20210305384 A1”) discloses a three-dimensional memory device includes an alternating stack of word-line-isolation insulating layers and word-line-level electrically conductive layers located over a substrate, a plurality of drain-select-level electrodes that are laterally spaced apart from each other overlying the alternating stack, memory stack structures containing a respective vertical semiconductor channel laterally surrounded by a respective memory film and vertically extending through the alternating stack and the plurality of drain-select-level electrodes, inter-select-gate electrodes located between a respective neighboring pair of the drain-select-level electrodes, and inter-select-gate dielectrics located between each of the inter-select-gate electrodes and a neighboring one of the drain-select-level electrodes. The inter-select-gate electrodes are not electrically connected to the drain-select-level electrodes.
Allowable Subject Matter
Claims 22-27 are allowed.
Re: Independent Claim 22 (and its dependent claim(s) 23-27), the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: each of the electrically conductive layers comprises a combination of a respective metallic barrier liner and a respective metallic fill material portion; a first subset of the memory opening fill structures has respective first-type interfaces with the electrically conductive layers such that the metallic fill material portions of the electrically conductive layers directly contact the first subset of the memory opening fill structures; and the second subset of the memory opening fill structures has respective second-type interfaces with the electrically conductive layers such that the metallic fill material portions of the electrically conductive layers do not directly contact the second subset of the memory opening fill structures.
Claim(s) 21 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re: Claim 21, the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: wherein the respective laterally-extending seam in the respective metallic fill material portion comprises a grain boundary in the respective metallic fill material portion which is formed due to metal growth from only three sides.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at https://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached on 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights