Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regards to Claims 1, 6, and 11, the limitation “a prototype system comprising a programmable logic device configured, based on a modified circuit design, the prototype system including a circuit module …” is indefinite as it is unclear, from the claim language, what action is performed on the prototype signal because an action verb is missing.
For the purpose of a compact prosecution, the examiner treated this limitation as --a prototype system comprising a programmable logic device configured, based on a modified circuit design, generate the prototype system including a circuit module …-- as best understood by the examiner and also following the Specification [0031], as published.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, 8-12, 14-16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Aurelian Vasile Lazarut et al. (US 7376917), hereinafter ‘Lazarut’ in view of Yingtsai Chang et al. (US 20130227509), hereinafter ‘Chang’ in further view of Clemenz Portmann et al. (US 20150180484), hereinafter ‘Portmann’.
With regards to Claim 1, Lazarut discloses
A system of circuit validation (programmable logic for testing a design of a logic circuit, Abstract), comprising
a prototype system comprising a programmable logic device (the systems and methods described in the present disclosure relate to a client/server semiconductor and prototype verification system, Col.1, Lines 49-51; Although the SUT system finds particular application as a programmable logic device (PLD), the system can be applied to other semi-conductor devices, Col.2, Lines 48-50; As will be described in more detail in reference to FIGS. 3-5, the SUTs can also be dedicated adapters or prototype boards attached to the server via a test bus, Col.3, Lines 20-23) configured, based on a modified circuit design,
the prototype system including a circuit module (The test vectors are coupled to the system under test, e.g., the circuit design in the FPGA, via the test server at a step 610. An output comprising result vectors of the circuit design is received by the test server from the system under test at a step 612. Finally, the result vectors are coupled to the client device via the test server at a step 614. The result vectors from the system under test are compared to expected result vectors at the client device at a step 616. It is then determined whether the result vectors match the expected vectors at a step 618. If not, the circuit design is modified and new configuration data is generated at a step 620, Col.6, Lines 62-67),
an input generation circuit coupled to the circuit module to output input signals to the circuit module in response to a test signal (The systems of FIGS. 1 and 2 provide, in addition to its other features, systems for applying the vectors generated from the behavioral testbench onto the actual inputs of the prototype system, without modification to either testbench or design implementation. The systems provide an extra level of verification, placed between functional verification and real time evaluation testing, Col.2, Lines 56-63; the system CPU 114 of the server controls the communication between the network 106 and the systems under test 110, Col.3, Lines 39-41), and
an output acquisition circuit coupled to the circuit module (Some SUTs, such as the SUT of FIG. 3, are not "smart" devices, because they only have input vectors applied and outputs sampled, Col.5, Line 66-Col.6, Line 1; An output comprising result vectors of the circuit design is received by the test server from the system under test at a step 612, Col.6, Lines 64-66; Fig.3; It may be necessary to measure the behavior of the SUT as well as actually reading its outputs. Examples of this could be power measurement circuits, temperature measurement devices, etc. As was previously mentioned, in order to debug some internal nodes in circuits, or to bring out test signals from internal devices on the board, a logic analysis card could be connected with probes attached to the SUT, as shown for example in FIG. 5, Col.6, Lines 29-36).
and a computing device coupled to the prototype system and configured to execute a test program to generate the test signal to perform a test on the circuit module on the prototype system (Fig.2; The SUT 504 comprises a logic circuit 512 coupled to a connector 514 which is coupled to a server, such as a server of FIG. 2 or 3. Similarly, a logic analyzer card 506 comprises a logic circuit 518 coupled to a connector 520 which is also coupled to a server, Col.6, Lines 40-45).
However, Lazarut does not specifically disclose an output acquisition circuit coupled to the circuit module to store output data from the circuit module and clocking resources and a clock switch configured to generate a source clock for a source clock domain of the circuit module and a target clock for a target clock domain of the circuit module.
Chang discloses storing output data from the circuit module (A second option is to store the primary output signal values 2403 in memory 2412 disposed on the interface device using controller 2410 [0103]; Fig.15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lazarut in view of Chang to couple an output acquisition circuit to the circuit module for storing output data from the circuit module to send the data to a host workstation for future use (The stored values may be uploaded to the host workstation at the end of vector mode emulation, Chang [0103]).
Portmann discloses clocking resources (A circuit [0001]; A configuration shown as 201 in FIG. 2 is shown in FIG. 3 [0025]) and a clock switch configured to generate a source clock for a source clock domain of the circuit module and a target clock for a target clock domain of the circuit module (A clock switch signal can be received and a complement of the clock switch signal can be generated. The clock switch signal can be qualified relative to the source clock to produce a qualified source clock switch signal. The complement of the clock switch signal can be qualified relative to the target clock to produce a qualified target clock switch signal [0002]; a circuit can switch from one clock to another … An implementation can switch between two clock sources of different quality. The different quality clocks can be of the same frequency, but be of different phase [0015]; As shown in FIG. 1, a clock select signal 100 (which can be synchronous or asynchronous) can be received in a system having two clock signals, a target clock signal 101 and a source clock signal 102. As used herein, the source clock signal is the signal presently being used by the system and the target clock signal is the clock signal to which the circuit is to switch [0019]; An implementation of the disclosed subject matter can provide a glitchless clock signal that switches from a source clock signal to a target clock signal… A clock switching circuit can be provided that comprises a number of flip-flops equal [0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lazarut in view of Chang, and Portmann to generate a source clock for a source clock domain of the circuit module and a target clock for a target clock domain of the circuit module using clocking resources that include a clock switch as known in the art (Portmann) for purpose such as timing and synchronization (A circuit can utilize a clock signal for purposes such as timing and synchronization. It can be useful to switch from one clock to another to change the frequency of the clock signal used by the circuit, Portmann [0001]).
With regards to Claim 3, Lazarut disclose wherein the computing device is configured to read output data associated with the test signal from the output acquisition circuit after the computing device receives a test completion signal from the prototype system such that the computing device checks the output data associated with the test signal (Claim 3) and to check whether the test on the circuit module passed based on the output data associated with the test signal and expected results associated with the test (Claim 4)(Fig.7; An output comprising result vectors are received from the system under test at a step 712. The result vectors are coupled to a client device at a step 714. The result vectors from the system under test are then compared to the expected results vectors at a step 716. It is then determined whether the result vectors match the expected vectors at a step 718. If not, the design is modified and configuration data is generated at a step 720, Col.7, Lines 16-24).
However, Lazarut does not specifically address test completion signal from the prototype signal.
Chang discloses receiving control information that include timing of completion/processed data stop (Timing and control information can include, but is not limited to, commands and data associated with probing signals to gather time-based or state-based information associated with a device or device state. Timing information can include clock signals generated, received, or processed by controller 400. Timing signals can also include start, stop, and reset signals [0049]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lazarut in view of Chang, in a computer system, to read output data and to check the output data associated with the test signal after the computing device receives a test completion signal from the prototype system to accurately evaluate DUT performance (timing and control information sent by controller 400 can provide a basis for creating a trigger sequence, capturing data from the device under test, assigning a time reference to captured data, sampling signal values, and configuring one or more signals within FPGA 250 (at least one of 250a and 250b) to be used as a clock when performing state analysis, Chang [0049]) by checking whether the test of the circuit module is passed based on the output data associated with the test signal and expected results associated with the test (Lazarut, Step 718, Fig.7; Step 818, Fig.8).
With regards to Claim 5, Lazarut discloses the prototype system is coupled to the computing device through a signal interface, and the input generation circuit and the output acquisition circuit are coupled to the computing device through the signal interface (The test server will execute test jobs on the SUTs and sample their outputs, sending results back to the client system so that the functionality can be evaluated … SUT could be a design attached to a standard bus interface … As long as the server is capable of applying digital inputs to and sampling digital outputs from the SUT, then it can be connected using the required technology, Col.3, Lines 11-27; A test server comprising a network interface and a system under test interface is provided a step 704, Col.7, Lines 10-12).
Chang also discloses the prototype system is coupled to the computing device through a signal interface, and the input generation circuit and the output acquisition circuit are coupled to the computing device through the signal interface (Abstract, [0009, 0010, 0039, 0089, 0091], Fig.3).
With regards to Claims 6, 11, and 15, Lazarut in view of Chang, and Portmann discloses the claim limitations as discussed above with regards to Claim 1.
With regards to Claims 8, 9, and 10, Lazarut in view of Chang, and Portmann discloses the claim limitations as discussed above with regards to Claim 6 and Claims 3, 4, and 5, respectively.
With regards to Claims 12 and 14, Lazarut in view of Chang, and Portmann discloses the claim limitations as discussed above with regards to Claim 11 and Claims 3 and 4.
With regards to Claim 16 and 18, Lazarut in view of Chang, and Portmann discloses the claim limitations as discussed above with regards to Claim 15 and Claims 3 and 4.
Claims 2, 7, 13, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lazarut in view of Chang, and Portmann, and further in view of Stephen Bourassa et al. (KR 20140091719), hereinafter ‘Bourassa’.
With regards to Claim 2, Lazarut discloses computing device is configured to generate the test signal (The interactive GUI could read in the design or testbench (in HDL or Schematic) and present a waveform construction display. The user could set the values of input signals, Col.4, Lines 32-34; a circuit design may be described in Verilog and a set of test vectors created by the user, Col.6, Lines 50-51) and send the test signal to the input generation circuit to output the input signals indicating test patterns associated with the test on the circuit module (The test vectors of a predetermined test job are coupled to the system under test by way of the test server at a step 710, Col.7, Lines 15-16; the test vectors can be run at higher bandwidths, reaching "real design speeds" for the purpose of timing closure or characterization, temperature and power analysis or other environmental analysis of the system running at full speed, Col.2, Lines 62-67; One method is the extraction of test vectors from the SUT design behavioral model and testbench, Col.3, Lines 49-51; it is contemplated that the vectors can be applied close to "real" design speeds with the use of data pumps and specialized circuitry surrounding the SUT, for the purpose of timing characterization, Col.3, Line 67-Col.4, Line 3).
However, Lazarut does not specifically disclose generating the test signal including parameters and sending the test signal to the input generation circuit to output the input signals indicating test patterns associated with the parameters for the test of the DUT
Chang also discloses the computing device is configured to generate the test signal (a separate program may be written to create the cycle-by-cycle values for the primary input signals [0101]; The pre-generated, cycle-by-cycle, primary input signal values, which may be called "input vectors" … Clock signals may be "tagged" to the input vectors so that they can communicate to the controller which clock edge is to apply after the current vector is delivered to the primary input signals 2402 of the user design [0102]) and send the test signal to the input generation circuit to output the input signals indicating test patterns for the test on the circuit module (There are different ways to generate test patterns for the FPGA devices on the customer prototyping device. For example, test patterns may be delivered from a test-bench running on a workstation, or they me be fetched from a local memory [0102]).
Bourassa discloses generating the test signal in the form of parameters (the tester 302 generates test signals and generates test parameters (e.g., test signal voltage levels, test signal current levels, Digital value, etc.) (e.g., in a system processing device, an embedded processing device, or programmable logic), p.7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lazarut in view of Chang, and Portmann, and Bourassa to generate the test signal in form of parameters to control different aspects of testing.
With regards to Claim 7, Lazarut in view of Chang, and Portmann, and Bourassa discloses the claim limitations as discussed above with regards to Claims 6 and Claim 2.
With regards to Claim 13, Lazarut in view of Chang, and Portmann, and Bourassa discloses the claim limitations as discussed above with regards to Claim 11 and Claim 2.
With regards to Claim 17, Lazarut in view of Chang, and Portmann, and Bourassa discloses the claim limitations as discussed above with regards to Claim 15 and Claim 2.
Response to Arguments
35 U.S.C. 112(f)
Applicant’s arguments, see Applicant Arguments/Remarks, filed 1/15/2026, with respect to 2-4, 6-9, 12, and 16 have been fully considered and are persuasive. The claim interpretation under 112(f) has been withdrawn.
35 U.S.C. 103
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Neil Gregie et al. (US 20110026656) discloses systems having multiple potential clock sources, circuitry and methods are used for selecting from among multiple clock sources.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER SATANOVSKY whose telephone number is (571)270-5819. The examiner can normally be reached on M-F: 9 am-5 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Catherine Rastovski can be reached on (571) 270-0349. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDER SATANOVSKY/
Primary Examiner, Art Unit 2863