Prosecution Insights
Last updated: August 17, 2026
Application No. 18/355,339

ADAPTIVE ERASE VOLTAGES FOR NON-VOLATILE MEMORY

Non-Final OA §112
Filed
Jul 19, 2023
Priority
Nov 30, 2022 — provisional 63/428,830
Examiner
KING, DANIEL JOHN
Art Unit
2827
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SanDisk Technologies Inc.
OA Round
3 (Non-Final)
98%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 98% — above average
98%
Career Allowance Rate
61 granted / 62 resolved
+30.4% vs TC avg
Minimal +2% lift
Without
With
+2.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
12 currently pending
Career history
82
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
25.2%
-14.8% vs TC avg
§102
29.5%
-10.5% vs TC avg
§112
43.6%
+3.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 62 resolved cases

Office Action

§112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claims 1-12 are objected to for minor informalities. Claim 1 sets forth “declare the erase verify test as having failed,”. For purposes of compact prosecution, claim 1 is interpreted to end with a full stop “.” instead of a comma. Also, the word “initial” is misspelled twice in the claim, as “intial” and “intital”. Such misspellings are corrected in examiner’s amendment. For example, the claim is interpreted as set forth: 1. An apparatus comprising: a block of memory cells; and a control circuit coupled to the block of memory cells, the control circuit configured to perform an erase operation on the block of memory cells by: applying a first erase pulse having a first erase voltage; determining a number of memory cells in the block that have failed an erase verify test; for a number of memory cells in the block that have failed the erase verify test less than a threshold, then: determining a count of a number of times that the block of memory cells previously has been programmed and erased, determining an [[intial]] initial value of a second erase voltage by linearly increasing the [[intital]] initial value of the second erase voltage in proportion to the count, and applying the second erase pulse having the second erase voltage to the block of memory cells; and otherwise declare the erase verify test as having failed[[,]]. Claims 3-12 are objected to as dependent upon claim 1. Claims 13-14 and 16 are objected to for minor informalities. Claim 13 includes improper usage of gerunds. For example, it is incorrect to set forth that “the control circuit configured to: applying…determining”. Such incorrect grammar is interpreted as set forth in the below example claim. Also, claim 13 includes a missing conjunction in line 14-15. Therefore, claim 13, is interpreted as follows: 13. An apparatus comprising: a block of memory cells; and a control circuit coupled to the block of memory cells, the control circuit configured to: [[applying]] apply a first erase pulse having a first erase voltage; [[determining]] determine a number of memory cells in the block that have failed an erase verify test; for a number of memory cells in the block that have failed the erase verify test less than a threshold, then: perform an erase operation on the block of memory cells in a plurality of erase-verify loops; and determine an initial value of a second erase voltage by linearly increasing the initial value of the second erase voltage in proportion to the number of erase-verify loops; and otherwise declare the erase verify test as having failed. Claims 14 and 16 are objected to as dependent upon claim 13. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1 and 3-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites “the second erase pulse” in line 16. There is insufficient antecedent basis for this limitation in the claim. Appropriate correction is required. Claims 3-12 are rejected as dependent upon claim 1. Claims 3-5 and 8-10 set forth “the initial value”. This language is unclear, because it is unclear whether each reference to “the initial value” is referring to “an initial value” set forth in independent claim 1. Appropriate clarification is required. Claim 11 recites “the initial value of the second erase voltage” in line 2. It is unclear whether this limitation relates back to “an initial value” in claim 10, line 5 or claim 1, line 12. Appropriate clarification is required. Claim 12 is rejected as dependent upon claim 11. Allowable Subject Matter The prior art of record does not appear to teach the subject matter of claims 1, 3-14, and 16. However, further search and consideration is required upon resolution of indefiniteness issues and claim objections. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J KING whose telephone number is (703)756-1232. The examiner can normally be reached M-F 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL JOHN KING/Examiner, Art Unit 2827 /AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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Prosecution Timeline

Show 4 earlier events
Apr 30, 2025
Response Filed
Aug 13, 2025
Final Rejection mailed — §112
Dec 10, 2025
Response after Non-Final Action
Feb 10, 2026
Request for Continued Examination
Feb 19, 2026
Response after Non-Final Action
Mar 10, 2026
Non-Final Rejection mailed — §112
May 06, 2026
Response Filed
May 06, 2026
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

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Patent 12700459
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3y 8m to grant Granted Aug 04, 2026
Patent 12700456
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Patent 12688899
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
98%
Grant Probability
99%
With Interview (+2.3%)
2y 3m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 62 resolved cases by this examiner. Grant probability derived from career allowance rate.

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