Detailed Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Drawings 1, 2, 5, 6, 8, 11 are objected to. It is suggested to write in words the boxes in figs. 1, 2, 5, 6, 8 and 11.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 10, 12 – 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lei et al. (USPGPUB 2020/0195269).
Regarding claims 1, 5, Lei et al. disclose a non-transitory computer readable medium comprising instructions which, when executed by one or more processors, are configured to cause the one or more processors and method (fig. 2) to: generate, on a reference voltage line, an analog reference voltage (the voltage doing from the switch capacitor DAC); and connect, at a time of generating the analog reference voltage, a pre-charged capacitor of an analog-to-digital converter (ADC) to the reference voltage line to reduce a voltage error during a generation of the analog reference voltage in the ADC (paragraphs 0004, 0008).
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Regarding claims 2, 6, Lei et al. disclose a non-transitory computer readable medium and method (figs. 1, 2, 4, 5, 6), wherein the instructions further cause the one or more processors to select the pre-charged capacitor out of a plurality of pre-charged capacitors of the ADC based on the value of the analog reference voltage to be generated (figs. 1, 2, 4, 5, 6).
Regarding claim 3, Lei et al. disclose a non-transitory computer readable medium (figs. 1, 2, 4, 5, 6), wherein the ADC comprises a digital-to-analog converter (DAC) configured to receive a digital code indicative of the analog reference voltage to be generated and to generate the analog reference voltage, and wherein the pre-charged capacitor is connected to the reference voltage line at the time that the DAC generates the analog reference voltage (figs. 1, 2, 4, 5, 6).
Regarding claims 4, 7, Lei et al. disclose a non-transitory computer readable medium and method (figs. 1, 2, 4, 5, 6), wherein the instructions further cause the one or more processors to: receive a further reference voltage (the input of the inverting of the comparator) ; compare (105, fig. 1, 2, 5, 4, 6) the value of the analog reference voltage to the value of the further reference voltage; and in case the analog reference voltage value does not correspond to an expected value based on the value of the further reference voltage, adjust the analog reference voltage in accordance with the further reference voltage value (paragraph 0025).
Regarding claim 8, Lei et al. disclose an analog-to-digital converter (ADC) configured to convert an input analog voltage into a digital representation (fig. 2) , the ADC comprising: a digital-to-analog converter (DAC) (110, fig. 2) configured to generate an analog reference voltage on a reference voltage line; a pre-charged capacitor (the capacitor in block 110); and a controller (130, fig. 2) configured to: connect, during a generation of the analog reference voltage by the DAC, the pre-charged capacitor to the reference voltage line to reduce a voltage error during the generation of the analog reference voltage by the DAC (paragraphs 0004, 0008).
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Regarding claim 9, Lei et al. disclose an ADC (fig. 2), further comprising: a comparator (105) configured to compare the input analog voltage to the analog reference voltage; and a controller (130) configured to receive the result of the comparison, and to determine, based on the result of comparison, a digital code indicative of the analog reference voltage to be generated (fig. 2; paragraphs 0020 - 0021).
Regarding claim 10, Lei et al. disclose an ADC (fig. 2), further comprising: a successive-approximation register (SAR) (120) configured to store successively a plurality of digital codes, wherein each digital code stored in the SAR is indicative of the analog reference voltage to be generated, and corresponds to successive approximations of the input analog voltage to be converted by the ADC (fig. 2).
Regarding claim 12, Lei et al. disclose an ADC (fig. 2),, further comprising: a plurality of pre-charged capacitors (the capacitors in 110 off fig. 2), wherein the pre-charged capacitor connected to the reference voltage line is selected out of the plurality of pre-charged capacitors based on the value of the analog reference voltage to be generated (fig. 2).
Regarding claim 13, Lei et al. disclose an ADC (fig. 2),, wherein the plurality of pre-charged capacitors have different capacitances and/or are pre-charged to different charge levels (fig. 2).
Regarding claim 14, Lei et al. disclose an ADC (fig. 2), further configured to receive a sampling clock signal indicative of the start of the conversion of the analog input voltage by the ADC, and further comprising: a comparator (105) configured to compare the value of the analog reference voltage after the pre-charged capacitor is connected to the reference voltage line to a value of a further reference voltage; and an error correction circuit (not labeled) configured to: receive a signal indicative of the result of the comparison from the comparator; and based on the result of the comparison, adjust the analog reference voltage (paragraphs 0004, 0008).
Regarding claim 15, Lei et al. disclose an ADC (fig. 2), wherein the error correction circuit (not labeled) comprises a plurality of capacitors, and wherein, based on the result of the comparison, the error correction circuit is configured to connect, during a sampling clock cycle, one or more capacitors out of the plurality of capacitors to the reference voltage line (fig. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lei et al. (USPGPUB 2020/0195269) in view of Du et al. (US Patent Number 6,864,738).
Regarding claim 11, Lei et al. disclose all the limitations of the claim except the ADC, wherein the capacitor is pre-charged via a voltage booster. However, Du et al., in a related field, disclose a system where the capacitor is pre-charged via a voltage booster (fig. 1; col. 1, lines 55 – 67). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Lei et al.’s analog to digital converter with that of Du et al. for the purpose of improving the ADC>
Allowable Subject Matter
Claims 16 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEAN BRUNER JEANGLAUDE whose telephone number is (571)272-1804. The examiner can normally be reached Monday-Thursday 7:00 AM-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dameon Levi can be reached at 571-272-2105. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JEAN B JEANGLAUDE/Primary Examiner, Art Unit 2845
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