Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
In response to the amendment filed on 07/15/2026. Claims 1 & 20 have been amended, new claims 24-29 have been added, claims 3-4, 7, & 12-13 have been cancelled, and claims 1-29 are pending and under examination.
Response to Arguments
Applicant’s arguments filed on 07/15/2026 have been fully considered but are not persuasive.
Arguments - Independent Claim 1
Regarding the Applicant’s first argument, page 8-9, the Applicant points out that the claimed separation layer in the Non-Final Rejection was read onto Yoo’s cavity separation layer and onto Chen’s permanent passivation layer. Similarly, the claimed electrical contact element layer was read onto Yoo’s interlayer circuit and Chen’s connector. Applicant argues that one claim feature cannot be met by two different and incompatible structures.
Respectfully, the Applicant’s argument is not found to be compelling as the mapping of the single feature to two structures was used to detail the combination of Yoo and Chen. For the claimed separation layer, Yoo’s disclosure taught the limitation through the use of a separation layer 129 while Chen’s passivation layer 117 was used as a layer that could support additional layers provided on top such as a seed layer, structuring layer, electrical contact element layer, and such. In a similar manner, Chen’s disclosure was used as it taught that a conductive material, namely connector 401, could be purposely shaped though the use of a structuring layer, namely photoresist layer 301. Utilizing this shaping technique would allow a POSITA to modify Yoo’s interlayer circuit shape. Regarding whether or not the structures are found to be incompatible structures, the combination teaches the location/placement of layers and how their locations are relative to neighboring layers.
Furthermore, the instant claimed “separation layer” is not an industry standard term and therefore the Examiner has looked to the instant specification in order to determine if the phrase has been specially defined by the Applicant, as they are permitted to act as their own lexicographer in their original patent application disclosure. The instant specification broadly defines the separation layer as being intended to separate layers. This interpretation agrees with the commonly used definition of the word separation. Accordingly, the cited separation layer 129 of Yoo and passivation layer 117 of Chen both clearly disclose the limitation as currently presented.
Regarding the Applicant’s second argument, page 9, the Applicant points out that the Yoo does not teach the removal of a structuring layer and Chen does not teach a removal step of a permanent structuring layer.
Respectfully, the Applicant’s argument is not found to be compelling as the Applicant attacks the prior art references individually rather than the combination. Chen teaches that a structuring layer, identified to be located above a separation layer as well as layer location as the electrical element, may be used to shape the electrical contact element while Yoo teaches a removal step to remove a separation layer and all layers directly above the separation layer. Chen was not cited in the Non-Final to teach the argued limitation as the Examiner has clearly demonstrated that Yoo does disclose this limitation.
Regarding the Applicant’s third argument, page 9, the Applicant points out that the limitation “via the structuring layer” was not addressed in the Non-Final Rejection.
Respectfully, the Applicant appears to be reading limitations into the claim, though they are not expressly recited and are not found to be included in the claim under Broadest Reasonable Interpretation (BRI). Specifically, the term “via” in this context is not found to mean more than simply “by way of”. The claim language borders on being indefinite, as one can interpret such a word in a method claim in numerous different ways. For example, the term “via” could be interpreted to be “through”, “upon”, “on top of”, “defined shape”, “orientation with respect to a structure”, and more. Because all reasonable interpretations of the broad limitation could be read onto the limitation, the cited portion of Chen [detailed below regarding the argument] is found to teach the argued limitation as currently presented.
Regarding the argument, the Applicant’s argument is not found to be compelling as the Non-final rejection recites…
“Chen discloses the electrical contact element layer (connectors 401 in FIG. 4B, col. 4, ll. 64-67) being deposited according to the predefined structure (Figure 4B depicts the connector 401 being shaped within the defined structure of the photoresist layer 301)”
[p. 6, ll. 10 – p. 7, ll. 2]
In view of Chen, the predefined structure was mapped to opening 303, structuring layer mapped to photoresist layer 301, the electrical contact element mapped to connector 401, the basic layer mapped as seed layer 201, and FIGS. 3B & FIG. 4B disclose the relationship between all elements. A POSITA would have recognized the relationship between depositing the connector 401 in opening 303, shaped by photoresist layer 301, located above seed layer 201, could be understood as to encompass the claimed limitation “adding an electrical contact element layer by depositing electrically conductive material on the basic layer via the structuring layer according to the predefined structure”.
The Applicant also argued, page 9, that the combination rationale reflects impermissible hindsight.
Respectfully, a POSITA would have been motivated to apply the etching/cutting technique of Yoo with the shaping of an electrical contact element technique of Chen because Yoo provides a method of precisely removing unwanted material from a circuit board structure. Also, Chen recognizes the need to shape an electrical contact element. Therefore, applying both well-known techniques would provide no more than predictable results of forming desired contact geometry and surface characteristics.
Arguments - Independent Claim 20
Regarding the argument for claim 20, page 10, Applicant pointed out that independent claim 20 was rejected along with independent claim 1 over Yoo in view of Chen, and further in view of Ohhira. Applicant argues that Ohhira does not cure the aforementioned deficiencies of the combination of Yoo and Chen. Applicant also pointed out that prior art Ohhira shows a solid ground conductor, not a mesh structure.
Respectfully, as detailed above, the combination of Yoo and Chen teaches arguments 1-3.
Applicant’s arguments regarding the solid ground conductor have been fully considered and are persuasive. The Examiner agrees that the ground conductor previously mapped as the claimed mesh does not equate to a mesh. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Morimoto et al (W.O. 2006090798 A1).
Arguments – Dependent Claims 2, 5-6, 8-11, 14-19, and 21-29
Regarding the argument for claim 15, page 10, Applicant points out that the hole size and spacing are not taught and that the optimization rationale is unsupported. More specifically, Applicant argues that the rational established by the Office Action “a result-effective variable” is unsupported.
Applicant’s arguments with respect to claim 15, page 10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. A new ground of rejection is made in view of Morimoto et al (W.O. 2006090798 A1).
Regarding the argument for claim 16, page 10-11, Applicant points out that Hirasawa depicts the at least one welding section lies on the top and bottom faces of a body in a through hole, not on two opposing outer edges of the contact element.
The Examiner respectfully disagrees as the claim does not specify the range/scope at which the “outer edges” can be identified as. Under the BRI, a welding section positioned at or immediately adjacent to the outer edge of the body satisfies the limitation. Thus, Hirasawa illustrates the welding section at a location that can be under proximate to the outer edge.
Arguments - Conclusion
For the reasons explained above, amended independent claims 1 & 20 have been rejected. Furthermore, being that claims 2, 5-6, 8-11, 14-19, & new claims 21-29 are dependent on claims 1 & 20, respectively, they have been rejected as well.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2, 5-6, 8-11, 14-29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 is rejected as it recites the limitation “at least in specific sections” in line 11. The limitation renders the scope of the claim unclear because it is an instance of a hedging term. The hedging limitation “specific sections” broadens the scope of the claim, making it difficult for a POSITA to recognize how narrow the claimed subject matter actually is. In this instance, the limitation does not provide any bases on how the claimed structure is measured such that it could be interpreted to be any surface and/or volume of the electrical contact element layer.
Further, the hedging limitation “at least” is indefinite because a POSITA would be unable to determine the scope or metes and bounds of the term. Being “specific” naturally means that the sections should not be undefined, yet the term “at least” makes the purportedly “specific sections” non-specific and indefinite.
For the same reason, claim 20 which recites the limitation “specific sections”, and all dependent claims 2, 5-6, 8-11, 14-19, & 21-29, respectively, thereof are rejected as well by virtue of their dependencies.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 6, 8-11, 18-19, 24-25, & 29 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al (U.S. Patent Application Publication 20130299223 A1) hereinafter Yoo, and further in view of Chen et al (U.S. Patent Publication 9646943 B1) hereinafter Chen.
Regarding claim 1, Yoo discloses a method for manufacturing an electrical contact element (Title: Printed Circuit Board and Method for Manufacturing the Same) on a circuit structure (printed circuit board, ¶2) , the method comprising:
depositing a separation layer (separation layer 129, ¶65) on a carrier substrate (base substrate 110, ¶60), wherein the carrier substrate comprises the circuit structure (circuit patterns 125, ¶63);
adding an electrical contact element layer (interlayer circuit layer, ¶45) by depositing electrically conductive material on a basic layer (¶45, “an interlayer circuit layer (not shown) is formed between two of the first to third insulating layers 130, 140, and 150, and vias 132, 142, and 152 are formed in the first to third insulating layers 130, 140, and 150 so that the vias 132, 142, and 152 connect interlayer circuit layers to each other, FIG. 13 depicts the entire circuit structure assembled before further processing and removal of layers); and
PNG
media_image1.png
204
519
media_image1.png
Greyscale
removing the separation layer, and the structuring layer (cavity C in FIG. 3, ¶41, FIGS. 14 & 15 depict the process of removing layers to expose a predetermined layer. FIGS. 3 & 4 depict the end product after removal),
PNG
media_image2.png
280
523
media_image2.png
Greyscale
PNG
media_image3.png
211
544
media_image3.png
Greyscale
PNG
media_image4.png
216
485
media_image4.png
Greyscale
PNG
media_image5.png
221
474
media_image5.png
Greyscale
wherein removing the separation layer separates the electrical contact element layer (interlayer circuit layer) at least in specific sections (interlayer circuit layer side surfaces) from the carrier substrate while the electrical contact element layer remains attached to the circuit structure (interlayer circuit layer located between insulating layers and vias, as detailed in ¶45 and above, would have their side surfaces be separated from the base substrate 110 though exposure after the formation of cavity C).
However, Yoo fails to disclose forming a structuring layer with a predefined structure on a basic layer that is arranged between the separation layer and the structuring layer. Yoo also fails to disclose adding an electrical contact element layer by depositing electrically conductive material on a basic layer via the structuring layer according to the predefined structure.
Chen discloses a method for manufacturing an electrical contact element (Title: Connector Structure and Method of Forming Same) comprising a step of forming a structuring layer (photoresist layer 301, col. 5, ll. 18-20) with a predefined structure (patterned to form openings 303 in FIG. 3B, col. 5, ll. 18-20) on a basic layer (seed layer 201, col. 5, ll. 18-20) that is arranged between a separation layer (second passivation layer 117, col. 4, ll. 41) and the structuring layer; and
adding an electrical contact element layer (connectors 401, col. 4, ll. 64-67) by depositing electrically conductive material on the basic layer via the structuring layer according to the predefined structure (FIG. 4B depicts the connector 401 being shaped within the defined structure of photoresist layer 301, identified as opening 303);
PNG
media_image6.png
216
470
media_image6.png
Greyscale
PNG
media_image7.png
202
425
media_image7.png
Greyscale
Yoo discloses the method of manufacturing a circuit structure, featuring the steps of removing the separation layer and structuring layer to expose the circuit structure. Chen discloses the shaping of an electrical contact element layer using predefined structure of the structuring layer, namely the photoresist layer 301. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date to take the method of shaping an electrical contact element, taught by Chen, and apply it to the method of manufacturing a circuit structure with exposed circuit structure elements, taught by Yoo, would have yielded predictable results, allowing for higher quality surface finishes for greater contact and high precision geometry control between conducting layers.
Regarding claim 2, Yoo in view of Chen teaches the method according to claim 1, as detailed above, and Yoo further discloses wherein the separation layer is provided over at least part of the circuit structure (figures 3 and 4 depict the separation layer 129 formed directly on top of circuit pattern 125) and comprises at least one opening over at least a section of the circuit structure (figures 3 and 4 depict the exposed circuit pattern 125).
(Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 2 in the manner of circuit structure layer positions).
Regarding claim 6, Yoo in view of Chen teaches the method according to claim 1, as detailed above, and Chen further discloses wherein the basic layer comprises a seed layer provided on the separation layer (seed layer 201 in FIG. 3B, col. 5, ll. 18-20).
(Regarding the reason to combine references, refer to claim 1, supra, as it is applicable to the rejection of claim 6 in the manner of circuit structure layer positions).
Regarding claim 8, Yoo in view of Chen teaches the method according to claim 6, as detailed above, and Chen further discloses wherein the seed layer is formed with a thickness between 5nm and 300nm (col. 5, ll. 11-12, “the seed layer 201 may comprise a layer of copper having a thickness between about 0.05 µm and about 0.5 µm”).
(Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 8 in the manner of circuit structure layer positions).
Regarding claim 9, Yoo in view of Chen teaches the method according to claim 6, as detailed above, and Chen further discloses wherein the seed layer is formed of the same material as the electrical contact element layer (col. 5, ll. 6-7, “the seed layer 201 may comprise one or more layers of copper”; col. 5, ll. 39-40, “connectors 401 may include conductive materials such as … copper”). (Both the seed layer 201 and connector 401 may comprise of one, or more, of the listed materials given in the specs, in this case copper).
(Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 9 in the manner of circuit structure layer positions).
Regarding claim 10 Yoo in view of Chen teaches the method according to claim 6, as detailed above, and Yoo further discloses wherein the seed layer is removed at least in part with the separation layer, and the structuring layer (interlayer circuit layer, ¶45, “An interlayer circuit layer (not shown) is formed between two of the first to third insulating layers 130, 140, and 150, and vias 132, 142, and 152 are formed in the first to third insulating layers 130, 140, and 150 so that the vias 132, 142, and 152 connect interlayer circuit layers to each other”; it is understood that if the interlayer circuit layers are applied between each insulating layer, then the removal of the layers would result in the removal of the interlayer as seen in FIG. 14 and FIG. 15 below).
PNG
media_image8.png
410
481
media_image8.png
Greyscale
(Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 10 in the manner of circuit structure layer positions).
Regarding claim 11, Yoo in view of Chen teaches the method according to claim 1, as detailed above, and Chen further discloses wherein forming the structuring layer comprises:
depositing a second photoresist layer on the basic layer (col. 5, ll. 18-20, “a photoresist layer 301 is formed over the seed layer 201”);
exposing specific regions of the second photoresist layer to a light source, the specific regions being defined by the predefined structure (col. 5, ll. 32-35, “the photoresist layer 301 is irradiated (exposed) and developed to remove portions of the photoresist layer 301 and form the openings 303 in the photoresist layer 301”; Chen discloses the exposure of portions, portions being the specific regions of the photoresist layer 301); and
developing the second photoresist layer (col. 5, ll. 32-35).
(Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 11 in the manner of circuit structure layer positions).
Regarding claim 18, Yoo in view of Chen teaches the method according to claim 1, as detailed above, and Chen further discloses further comprising repeating the steps of forming a structuring layer, and adding an electrical contact element layer for creating a 2.5-dimensional electrical contact element (col. 5, ll. 46-52, “the connectors 401 may be pillars… the pillars may be solder free and have a substantially vertical sidewall. In the illustrated embodiment, the connectors 401 have first portions 401A formed of nickel and second portions 401B formed of indium”; FIG. 4B depicts significantly vertical photoresist layers 301 which constitutes for the allowance of forming a 2.5 structure. Repeating the steps of forming a structuring layer would result in said significantly vertical photoresist layers 301).
(Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 18 in the manner of circuit structure layer positions).
Regarding claim 19, Yoo in view of Chen teaches the method according to claim 1, as detailed above, and Chen further discloses further comprising repeating the steps of forming a structuring layer, and adding an electrical contact element layer for creating a bimetallic electrical contact element (FIG. 4B, col. 5, ll. 46-52, “the connectors 401 have first portions 401A formed of nickel and a second portions 401B formed of Indium”).
(Regarding the reason to combine references, refer to the rejection of claims 1 and 18, supra, as it is applicable to the rejection of claim 19 in the manner of circuit structure layer positions and the repeating step of forming a structuring layer).
Regarding claim 24, Yoo in view of Chen teaches the method according to claim 2, as detailed above, and Chen further discloses wherein depositing electrically conductive material on the basic layer (connector 401) comprises depositing the electrically conductive material (conductive material, col. 5, ll. 37-50, details formation methods such as evaporation, electroplating, printing, etc.) through the at least one opening (openings 303) onto the circuit structure such that the electrical contact element layer is brought into electrical contact with the circuit structure (FIG. 4 depicts electrical contact between connector 401 and circuit structure).
(Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 24 in the manner of circuit structure layer positions).
Regarding claim 25, Yoo in view of Chen teaches the method according to claim 1, as detailed above, and Yoo further discloses wherein removing the structuring layer comprises a lift-off process in which electrically conductive material deposited on the structuring layer is removed together with the structuring layer (¶41, a POSITA would have recognized that the interlayer circuit layer formed, where cavity C is to be formed, is removed) .
(Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 25 in the manner of circuit structure layer positions).
Regarding claim 29, Yoo in view of Chen teaches the method according to claim 1, as detailed above, and Yoo further discloses wherein the electrical contact element layer (interlayer circuit layer, ¶45) contacts a section of the circuit structure (annotated FIG. 4 below depicts a section of the circuit structure in contact with interlayer circuit layer [not shown], as detailed in ¶45); and
PNG
media_image9.png
259
444
media_image9.png
Greyscale
removing the separations layer (separation layer 129) separates the electrical contact element layer (interlayer circuit layer) from the carrier substrate (base substrate 110) outside the section of the circuit structure (¶41, formation of cavity C through the removal of separation layer 129 would separate the interlayer circuit layer from the base substrate 110, occurring from outside the section), while the electrical contact element layer remains attached to the circuit structure at the section (FIG. 4 depicts a section still present after the removing process).
(Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 29 in the manner of circuit structure layer positions).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo, in view of Chen, and in further view of Rogers et al (K.R. Patent Application Publication 20100123755 A) hereinafter Rogers.
Regarding claim 5, Yoo, in view of Chen, discloses the method according to claim 1, as detailed above.
However, both Yoo and Chen fail to disclose the method wherein the separation layer comprises a thickness between 2µm, and 50µm.
Rogers discloses the method for manufacturing (Title: Stretchable and Foldable Electronic Device) wherein the separation layer comprises a thickness between 2µm, and 50µm. (p. 7, ll. 21, “the separation layer has a thickness of 2 mm or less, 200 μm or less, 100 μm or less, or 20 μm or less”).
While both Yoo and Chen disclose the manufacturing of the electrical contact element and the circuit structure, Rogers teaches that the separation layer can be made to have a thickness of less than 200 μm. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the specified separation layer thickness and incorporate it into Yoo’s method to atone for the separation layer’s Young’s modulus and to allow for varied spatially changing positions of the neutral mechanical surface during deformation.
Claims 14, 15, 20, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo, in view of Chen, and in further view of Morimoto et al (W.O. Patent Application Publication 2006090798 A1) hereinafter Morimoto.
Regarding claim 14, Yoo, in view of Chen, discloses the method according to claim 1, as detailed above.
However, Both Yoo and Chen fail to disclose the method wherein the predefined structure comprises a mesh structure in at least a section of the structuring layer.
Morimoto discloses an apparatus and method (Title: Electromagnetic Shielding Laminate and Display using Same) comprising a mesh structure (conductive mesh film, ¶46) in at least a section of the structuring layer (protective plate, ¶46, “a conductive mesh film may be attached to the protective plate”).
PNG
media_image10.png
266
504
media_image10.png
Greyscale
Yoo, in view of Chen, discloses the method of manufacturing the electrical contact element from a circuit board through the process and removal of various layers of a circuit board. Morimoto teaches a low-cost electromagnetic shielding laminate having a conductive mesh film provided onto the protective plate. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the conductive mesh film from Morimoto’s disclosure into Yoo and Chen’s method as it is known that a conductive mesh layer enhances electromagnetic wave shielding (¶46). More specifically, it is well known to a POSITA that the addition of a mesh-like structure provides greater controlled electrical properties of an electrical structure, allowing an operator to utilize a mesh to modify resistance, impedance, capacitance, and even current distribution.
Regarding claim 15, Yoo, in view of Chen and Morimoto, teaches the method according to claim 14, as detailed above, and Morimoto further discloses wherein the distance between two holes in the mesh structure (conductive mesh film, ¶46) is between 5 μm and 15 μm (¶47, “The width of the metal part other than the opening is preferably 5 to 50 μm”) and;
Wherein the size of the holes in the mesh structure is smaller than 40µm (¶47, “The size of the opening is preferably 10 to 150 μm”).
(Regarding the reason to combine references, refer to the rejection of claim 14, supra, as it is applicable to the rejection of claim 15 in the manner of using a conductive mesh film to control electrical properties).
Regarding claim 20, Yoo discloses a measurement application device (Title: Printed Circuit Board and Method for Manufacturing the Same), as detailed above, comprising:
an electrical contact element (interlayer circuit layer, ¶45) manufactured by:
depositing a separation layer (separation layer 129 is formed in FIG. 4, ¶65) on a carrier substrate (base substrate 110, ¶60), wherein the carrier substrate comprises the circuit structure (circuit patterns 125, FIG. 3, ¶63);
adding an electrical contact element layer by depositing electrically conductive material on the basic layer (interlayer circuit layer, ¶45, “An interlayer circuit layer (not shown) is formed between two of the first to third insulating layers 130, 140, and 150, and vias 132, 142, and 152 are formed in the first to third insulating layers 130, 140, and 150 so that the vias 132, 142, and 152 connect interlayer circuit layers to each other”); and
removing the separation layer, and the structuring layer (cavity C in FIG. 3, ¶41, forming cavity C removes layers to expose the circuit pattern 125), wherein removing the separation layer separates the electrical contact element layer (interlayer circuit layer) at least in specific sections from the carrier substrate while the electrical contact element layer remains attached to the circuit structure (interlayer circuit layer located between insulating layers and vias, as detailed in ¶45 and above, would have their side surfaces be separated from the base substrate 110 though exposure after the formation of cavity C).
However, Yoo fails to disclose the device formed by a structuring layer with a predefined structure on a basic layer that is arranged between the separation layer and the structuring layer. Yoo also fails to disclose the device formed by adding an electrical contact element layer by depositing electrically conductive material on a basic layer via the structuring layer according to the predefined structure.
Chen discloses device (Title: Connector Structure and Method of Forming Same) manufactured by forming a structuring layer (photoresist layer 301, col. 5, ll. 18-20) with a predefined structure (patterned to form openings 303 in FIG. 3B, col. 5, ll. 18-20) on a basic layer (seed layer 201, col. 5, ll. 18-20) that is arranged between a separation layer (second passivation layer 117, col. 4, ll. 41) and the structuring layer; and
adding an electrical contact element layer (connectors 401, col. 4, ll. 64-67) by depositing electrically conductive material on the basic layer via the structuring layer according to the predefined structure (FIG. 4B depicts the connector 401 being shaped within the defined structure of photoresist layer 301, identified as opening 303);
(In view of the disclosure, please refer to the rejection of claim 1, supra, as it is applicable to claim 20 in the same manner of allowing for higher quality surface finishes for greater contact and high precision geometry control between conducting layers).
However, both Yoo and Chen fail to disclose the device wherein the electrical contact element comprises at least one mesh structure.
Morimoto discloses an apparatus and method (Title: Electromagnetic Shielding Laminate and Display using Same) comprising a mesh structure (conductive mesh film, ¶46).
(In view of the disclosure, please refer to the rejection of claim 14, supra, as it is applicable to claim 20 in the same manner of using a conductive mesh film to control electrical properties).
Regarding claim 23, Yoo, in view of Chen, and Morimoto teaches the measurement application device according to claim 20, and Chen further discloses wherein the electrical contact element further comprises at least one of a 2.5-dimensional structure and a bimetallic structure (col. 5, ll. 46-52, “the connectors 401 may be pillars… the pillars may be solder free and have a substantially vertical sidewall. In the illustrated embodiment, the connectors 401 have first portions 401A formed of nickel and second portions 401B formed of indium”; FIG. 4B depicts significantly vertical photoresist layers 301 which constitutes for the allowance of forming a 2.5 structure. Repeating the steps of forming a structuring layer would result in said significantly vertical photoresist layers 301).
(In view of the disclosure, please refer to the rejection of claim 1 & 14, supra, as it is applicable to claim 23 in the same manner of using a conductive mesh film to control electrical properties and utilizing coplanar line connecting signal lines).
Claims 17 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo, in view of Chen and Morimoto, and in further view of Ohhira (U.S. Patent Application Publication 20110226518 A1).
Regarding claim 17, Yoo, in view of Chen and Morimoto, teaches the method according to claim 1, as detailed above, and Morimoto further discloses the mesh structure (conductive mesh film, ¶46).
However, all fail to disclose predefined structure comprises at least one fixation section, wherein a mesh structure is provided on at least one of two opposing sides of the fixation section
Ohhira discloses (Title: Substrate of Circuit Module and Manufacturing Method Thereof) wherein the predefined structure comprises at least one fixation section (signal line 10 in FIG. 28, ¶100), wherein a structure is provided on at least one of two opposing sides of the fixation section (FIGS. 28 & 29 depict two structures located at opposing sides of the signal line 10).
PNG
media_image11.png
235
480
media_image11.png
Greyscale
PNG
media_image12.png
228
482
media_image12.png
Greyscale
Ohhira further teaches the electrical contact element having the structure shown in FIG. 28 comprising opposing structures to serve as a coplanar line connecting signal lines to dielectric layers. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the electrical contact element of Ohhira’s disclosure into Yoo’s, in view of Chen and Morimoto, method to improve reflection characteristics of a circuit module. The module’s characteristics are improved by electrically connecting an outer conductor at a coaxial connector to a conductor at the substrates terminal face (Ohhira, ¶7). Furthermore, it would have been obvious to a POSITA to implement Morimoto’s conductive mesh film into the structure of Ohhira to enhance electromagnetic wave shielding (Morimoto, ¶46).
Regarding claim 22, Yoo, in view of Chen, Morimoto, and Ohhira, teaches the measurement application device according to claim 20, and Ohhira further discloses wherein the electrical contact element further comprises at least one fixation section (signal line 10 in FIG. 28, ¶100), wherein a mesh structure is provided on at least one of two opposing sides of the fixation section (FIG. 28 depicts each structure located at opposing sides of the signal line).
(In view of the disclosure, please refer to the rejection of claims 1, 14 and 17, supra, as it is applicable to claim 22 in the same manner of using a conductive mesh film to control electrical properties and utilizing coplanar line connecting signal lines).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo, in view of Chen, and in further view of Hirasawa et al (U.S. Patent Application Publication 20190036289 A1) hereinafter Hirasawa.
Regarding claim 16, Yoo, in view of Chen, discloses the method according to claim 1, as detailed above.
However, both Yoo and Chen fail to disclose the method wherein the predefined structure comprises at least one welding section, wherein the at least one welding section is provided on at least one of two opposing outer edges of the electrical contact element.
Hirasawa discloses a method (Title: Flexible Printed Wiring Board, Electronic Device Having Flexible Printed Wiring Board, and Method for Manufacturing Electronic Device Having Flexible Printed Wiring Board) wherein the predefined structure (flexible printed wiring board 1 in FIG. 3 and FIG. 4, ¶26) comprises at least one welding section (metal body 60 in FIG. 3 and FIG. 4, ¶94), wherein the at least one welding section is provided on at least one of two opposing outer edges (end portion 61a in FIG. 3 and FIG. 4, ¶94) of the electrical contact element (flexible printed wiring board 1 in FIG. 3 and FIG. 4, ¶26).
PNG
media_image13.png
275
487
media_image13.png
Greyscale
PNG
media_image14.png
228
430
media_image14.png
Greyscale
While Yoo in view of Chen discloses the method of manufacturing an electrical contact element on a circuit structure, Hirasawa further discloses the electrical contact element containing a welding section provided at the end of the electrical contact element. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date to use the welding section from Hirasawa’s disclose and applied it to the ends of Yoo and Chen’s disclose to obtain a connecting and holding point of the electrical contact element. This could be purposed for the entire printed wiring board structure to have a naturally flexible build, allowing for bends, twists, and folds that are ideal for tight spaces and moving components.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo, in view of Chen, Morimoto, Ohhira, and Hirasawa.
Regarding claim 21, Yoo, in view of Chen, Morimoto, Ohhira, and Hirasawa, teaches the device of claim 20, as detailed above, and Hirasawa further discloses the measurement application device (electric device, ¶10) wherein the electrical contact element (flexible printed wiring board 1 in FIG. 3, ¶16) further comprises at least one welding section (metal body 60 in FIG. 3 and FIG. 4, ¶94), wherein the at least one welding section is provided on at least one of two opposing outer edges of the electrical contact element (end portion 61a in FIG. 3 and FIG. 4, ¶94),
Morimoto further discloses the at least one mesh structure (conductive mesh film, ¶46) is provided between adjacent to the at least one welding section (The combination of Morimoto Ohhira, and Hirasawa allows for a POSITA to take the welding sections from Hirasawa’s disclosure and apply it to Ohhira’s multilayered circuit substrate 40 Ohhira FIG. 28], provided with Morimoto’s conductive mesh film, to allow connections to be joined between two electric bodies or batteries (Hirasawa ¶32).
(Regarding the reason to combine references, refer to the rejection of claims 1, 14, 16, and 17, supra, as it is applicable to the rejection of claim 21 in the manner of circuit structure layer positions and welding sections).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo, in view of Chen and Hirasawa, and in further view of Bauer et al (U.S. Patent Publication 10283924 B2) hereinafter Bauer.
Regarding claim 26, Yoo, in view of Chen and Hirasawa, teaches the method according to claim 16, as detailed above, and Hirasawa further discloses welding sections at one of two opposing outer edges of the contact element.
However, all further discloses wherein the at least one welding section comprises a welding section on each of two opposing outer edges of the electrical contact element, the method further comprising winding the electrical contact element layer around a conductor such that the welding sections on the two opposing outer edges overlap, and welding the overlapping welding sections together.
Bauer discloses (Title: Method and Device for Connecting an Electrical Conductor to an Electrical Contact Part) a predefined structure comprising at least one welding section (contact part 14, col. 12, ll. 12),
wherein the at least one welding section comprises a welding section on each of two opposing outer edges of the electrical contact element (flanks 18, col. 12, ll. 23),
PNG
media_image15.png
260
421
media_image15.png
Greyscale
the method further comprising winding the electrical contact element layer around a conductor (strands 20 of a power cable 12, col. 12, ll. 27) such that the welding sections on the two opposing outer edges overlap, and welding the overlapping welding sections together (col. 13, ll. 13-16, “bending flanks 18 opposing each other such that they overlap with each other and/or contact each other”; the entire body of contact part 14 can serve as the welding section) (col. 12, ll. 11-63, Bauer details the process of using a welding laser beam 32 to bond contact part 14 with strands 20).
PNG
media_image16.png
364
574
media_image16.png
Greyscale
Yoo, in view of Chen and Hirasawa, discloses a method for manufacturing an electrical contact element utilizing steps of providing/removing layers as well as providing a welding section at two opposing outer edges of the electrical contact element. Bauer discloses a method of connecting an electrical conductor to an electrical contact part, utilizing a deformation and welding technique to shape the contact part around the electrical conductor for improved hold. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the method of Bauer’s simultaneous deformation/welding step and apply it to the electrical contact element of Yoo, in view of Chen and Hirasawa, to allow for improved manufacturing efficiency as compared to individual deformation and welding steps (Bauer, col. 13, ll. 45-60).
Claims 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo, in view of Chen, Morimoto, Ohhira, Hirasawa, and Bauer.
Regarding claim 27, Yoo, in view of Chen, Morimoto, Hirasawa, and Bauer, teaches the device according to claim 20, as detailed above, and Morimoto, Ohhira and Bauer further teach wherein the at least one mesh structure is provided in a section of the electrical contact element that is configured to be bent around a conductor (Morimoto teaches the mesh structure [conductive mesh film]. Ohhira teaches the structure [dielectric layer 40a] located at opposing ends of the electrical contact element. Bauer teaches of an electrical contact element that is configured to bend around a conductor. Thus, to a POSITA, a combination would result in an electrical contact element with a mesh structure located at edge portions configured to bend).
(Regarding the reason to combine references, refer to the rejection of claims 1, 14, 16, 17, & 26, supra, as it is applicable to the rejection of claim 27).
Regarding claim 28, Yoo, in view of Chen, Morimoto, Ohhira, Hirasawa, and Bauer, teaches the device according to claim 21, as detailed above, and Bauer further discloses wherein the at least one welding section (contact part 14, col. 12, ll. 12) comprises a welding section on each of the two opposing outer edges (flanks 18, col. 12, ll. 23), the welding sections being configured to overlap when the electrical contact element is wound around a conductor (col. 13, ll. 13-16, “bending flanks 18 opposing each other such that they overlap with each other and/or contact each other”; the entire body of contact part 14 can serve as the welding section) (col. 12, ll. 11-63, Bauer details the process of using a welding laser beam 32 to bond contact part 14 with strands 20).
(Regarding the reason to combine references, refer to the rejection of claims 1, 14, 16, 17, & 26, supra, as it is applicable to the rejection of claim 28).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE REY D LEGASPI whose telephone number is (571)272-2956. The examiner can normally be reached Monday-Friday 8-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hong can be reached at (571) 272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/E.D.L./Examiner, Art Unit 3729
/JEFFREY T CARLEY/Primary Examiner, Art Unit 3729
Prosecution Insights