DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the filling of the Response to Restriction filed on 12/23/2025. The applicant elects Species 1 (Figure 8A, first implementation of element 240 [voltage increase/decrease detection circuitry]) and sub-Species 1 (Figure 9A, first implementation of element 220 [control circuitry based on adjustment of the output current in stepwise manner]). Based on the applicant election, the claims related to this species are 1-6, 12, 15, 16, 18, 19 and 26. Claims 7-11, 13, 14 and 22 are withdrawn for consideration and claims 17, 20, 21, 23-25 were previously cancelled.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 15, 18, 19 and 26 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Hwang et al. (KR10-1790943; rejection based on English translation), hereinafter Hwang.
Regarding claim 1, Hwang discloses (see figures 1-5) a low dropout (LDO) regulator (figure 3) (paragraph [0052]; a block diagram illustrating the structure of a digital LDO regulator), comprising: comparison circuitry (figure 3, part 120) configured to generate a comparison result signal (figure 3, part 120; output Up/Down signal) by comparing a target voltage (figure 3, part Vref’) with an output voltage (figure 3, part Vout) (paragraph [0055]; The comparator 120 receives the output voltage Vout supplied to the load and compares the reference voltage Vref' with the output voltage Vout to generate an up signal or a down signal) corresponding to a voltage of an output terminal (figure 3, part Vout at output terminal connected to load) connected to an integrated circuit (figure 3, part load generated by integrated circuit of smart products including portable devices such as mobile phones and laptops) (paragraph [0005]; the use of digital LDO regulators in various smart products including portable devices such as mobile phones and laptops has become commonplace); voltage increase/decrease detection circuitry (figure 3, part voltage increase/decrease detection circuitry generated by 130) configured to generate a detection result signal (figure 3, part voltage increase/decrease detection circuitry generated by 130; output detection result signal SAR/ACC) by detecting whether the output voltage increases or decreases (figure 3, part Vout) (paragraphs [0056] and [0076]; The Boost & Lock detector 130 checks the state of the output voltage Vout and selects one of the Boost mode and the Lock mode… when an overshoot or an undershoot occurs in the output voltage Vout according to the variation of the current flowing in the load, the boost and the lock detector 130 performs an overshoot of the output voltage Vout Depending on the undershoot, the voltage range necessary to determine the operation mode of the boost mode and the lock mode can be set); control circuitry (figure 3, part control circuitry generated by 140 and 150) configured to generate a current control code (figure 3, part sw_con) having a value that is changed (figure 3, part sw_con) (paragraphs [0057] and [0058]; The SW buffer 150 drives ON / OFF of the switch array 160 composed of a binary code under the control of the controller 140), based on a control mode selected (figures 3-5, parts boost or lock mode) according to the comparison result signal (figure 3, part 120; output Up/Down signal) and the detection result signal (figure 3, part voltage increase/decrease detection circuitry generated by 130; output detection result signal SAR/ACC); and current driving circuitry (figure 3, part 160) configured to receive the current control code (figure 3, part sw_con), and generate an output current (figure 3, part output current output from 160 to Vout terminal) corresponding to the current control code (figure 3, part sw_con) (paragraphs [0052]-[0077]; The controller 140 controls the ON or OFF of each switch of the switch array 160 according to the operation mode selected by the boost and lock detector 130 and the up signal or the down signal generated by the comparator 120, (On / Off) operation).
Regarding claim 2, Hwang discloses everything claimed as applied above (see claim 1). Further, Hwang discloses (see figures 1-5) the selected control mode (figures 3-5, parts boost or lock mode) corresponds to a fast mode (figures 3-5, part boost mode), when the output voltage increases in an overshoot period (figure 5, part Vout; at Boost mode [b]) in which the output voltage mode (figures 3-5, part Vout) is higher than the target voltage (figures 3-5, part Vref’) (paragraphs [0066]-[0077]; If the Vref 'produced by the reference voltage generator 110 does not fall between the two reference voltages generated by the boost and lock detector 130, the Boost signal becomes high and the controller 140 ) Perform SAR operation. This requires only a bit cycle of the SW array 160 in response to a sudden current change of the output stage, so that a large bit for satisfying a high resolution… if Vout is greater than a predetermined value with reference to Vref ', it operates in a boost mode), and the selected control mode (figures 3-5, parts boost or lock mode) corresponds to a slow mode (figures 3-5, part lock mode), when the output voltage increases in the undershoot period (figure 5, part Vout; at Lock mode [a]) (paragraphs [0066]-[0077]; The lock detector detects the output of the lock signal when the reference voltage Vref 'is between the two reference voltages by the same principle as the boost detector in the boost and lock detector 130 High. This causes the controller 140 to operate as an accumulator. If the up / down signal is repeated while the output of the lock signal is maintained at a high level, it is determined that Vout has reached the target voltage and the reference clock is divided , The operation speed of the controller 140 is made to be slow to reduce the quiescent current… If Vout is close to Vref' within a predetermined value, it is confirmed that the operation is in a lock mode have).
Regarding claim 3, Hwang discloses everything claimed as applied above (see claim 2). Further, Hwang discloses (see figures 1-5) the control circuitry (figure 3, part control circuitry generated by 140 and 150) is further configured to generate the current control code (figure 3, part sw_con) by causing at least one of a number of bits (figure 3, part sw_con), which are changed in values (figure 3, part sw_con) at once from among a plurality of bits in the current control code (figure 3, part sw_con), to be greater in the fast mode (figures 3-5, part boost mode) than in the slow mode (figures 3-5, part lock mode) (paragraphs [0066]-[0077]; If the Vref 'produced by the reference voltage generator 110 does not fall between the two reference voltages generated by the boost and lock detector 130, the Boost signal becomes high and the controller 140 ) Perform SAR operation. This requires only a bit cycle of the SW array 160 in response to a sudden current change of the output stage, so that a large bit for satisfying a high resolution… The lock detector detects the output of the lock signal when the reference voltage Vref 'is between the two reference voltages by the same principle as the boost detector in the boost and lock detector 130 High. This causes the controller 140 to operate as an accumulator. If the up / down signal is repeated while the output of the lock signal is maintained at a high level, it is determined that Vout has reached the target voltage and the reference clock is divided , The operation speed of the controller 140 is made to be slow to reduce the quiescent current).
Regarding claim 15, Hwang discloses everything claimed as applied above (see claim 1). Further, Hwang discloses (see figures 1-5) the current driving circuitry (figure 3, part 160) comprises: a plurality of power transistors (figure 3, part 160; SW array) configured to be turned on or off (figure 3, part 160; SW array; on/off), respectively, in response to a plurality of bits in the current control code (figure 3, part sw_con) (paragraphs [0052]-[0077]; The controller 140 controls the ON or OFF of each switch of the switch array 160 according to the operation mode selected by the boost and lock detector 130 and the up signal or the down signal generated by the comparator 120, (On / Off) operation).
Regarding claim 19, claim 2 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 18, claim 1 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 26, claim 1 has the same limitations, based on this is rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (KR10-1790943; rejection based on English translation), hereinafter Hwang, in view of Yang et al. (US 2016/0173066), hereinafter Yang.
Regarding claim 12, Hwang discloses everything claimed as applied above (see claim 1). Further, Hwang discloses (see figures 1-5) the voltage increase/decrease detection circuitry (figure 3, part voltage increase/decrease detection circuitry generated by 130) comprises: the output voltage is input (figure 3, part voltage increase/decrease detection circuitry generated by 130; input Vout) and configured to output the detection result signal (figure 3, part voltage increase/decrease detection circuitry generated by 130; output detection result signal SAR/ACC) (paragraphs [0056] and [0076]; The Boost & Lock detector 130 checks the state of the output voltage Vout and selects one of the Boost mode and the Lock mode… when an overshoot or an undershoot occurs in the output voltage Vout according to the variation of the current flowing in the load, the boost and the lock detector 130 performs an overshoot of the output voltage Vout Depending on the undershoot, the voltage range necessary to determine the operation mode of the boost mode and the lock mode can be set). However, Hwang does not expressly disclose a capacitor, to which the output voltage is input; a first inverting amplifier connected in series with the capacitor; a resistor connected in parallel with the first inverting amplifier; and at least one second inverting amplifier connected in series with the first inverting amplifier.
Yang teaches (see figures 1-18) the voltage increase/decrease detection circuitry (figures 2 and 4, part 150) comprises: a capacitor (figure 4, part Cf), to which the output voltage is input (figure 4, part Cf; input Vout); a first inverting amplifier (figure 4, part INV1) connected in series with the capacitor (figure 4, part Cf); a resistor (figure 4, part Rf) connected in parallel with the first inverting amplifier (figure 4, part INV1); and at least one second inverting amplifier (figure 4, part INV2) connected in series with the first inverting amplifier (figure 4, part INV1) and configured to output the detection result signal (figures 2 and 4, part V1) (paragraph [0068]).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the voltage increase/decrease detection circuitry of Hwang with the voltage increase/decrease detection circuitry features as taught by Yang and obtain the voltage increase/decrease detection circuitry comprises: a capacitor, to which the output voltage is input; a first inverting amplifier connected in series with the capacitor; a resistor connected in parallel with the first inverting amplifier; and at least one second inverting amplifier connected in series with the first inverting amplifier and configured to output the detection result signal, because it provides more efficient and accurate transient detection (over-shoot or under-shoot) at the output in order to obtain more faster transient compensation (paragraph [0029]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (KR10-1790943; rejection based on English translation), hereinafter Hwang, in view of Wang et al. (US 2014/0266103), hereinafter Wang.
Regarding claim 16, Hwang discloses everything claimed as applied above (see claim 1). Further, Hwang discloses (see figures 1-5) change the value of the current control code (figure 3, part sw_con), each in a plurality of control modes (figures 3-5, parts boost or lock modes). However, Hwang does not expressly disclose parameter setting circuitry configured to set a value of at least one parameter used to change the value of the current control code, each in a plurality of control modes, based on an operation mode of the integrated circuit.
Wang teaches (see figures 1-5) parameter setting circuitry (figure 3, part 204) configured to set a value of at least one parameter (figure 3, part parameter inside of 204) used to change the value of the current control code (figure 3, part 228), each in a plurality of control modes (figure 3, part each in a plurality of control modes), based on an operation mode of the integrated circuit (figure 3, part operation mode of 208; through notification 218) (paragraphs [0020]-[0021]; An advance notification signal 218 is provided by the system circuit 208, such as by a processor circuit or by a finite state machine circuit that indicates a load change is to occur within a short time frame. For example, the system circuit 208 in response to a program enabling of an on chip complex function, such as a multimedia subsystem, may cause the advance notification signal 218 to be issued prior to such enabling… The transistor assembly 207 turns on in response to the advance notification signal 218 to supply voltage and current to the system circuit 208 in parallel with the LDO output device 216. For example, when the advance notification signal 218 is received, the digital controller 204 supplies control (Ctrl) signals 228 to the transistor assembly 207 that drives the transistor assembly 207 to pull the system circuit supply voltage Vdd--load 209 up toward a chip's incoming supply voltage Vddext 219. The digital controller 204 takes input from current ADC 206 that indicates how much current 216 is sourcing and controls a ramp down of the Vdd--load 209 voltage to a specified operating voltage of the system circuit 208, which for example, may be at a lower voltage than Vddext for reasons of power control. When the correct operating voltage has been reached and any undershoot problem removed, the digital controller 204 tracks the current ADC 206 output and the advance notice signal 218 to control the amount of digitally assisted current that should be supplied. In general, the digital controller 204 and the transistor assembly 207 handles static and low frequency current requirements while the LDO 205 handles high frequency dynamic current requirements).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the controller of Hwang with the control features as taught by Wang and obtain parameter setting circuitry configured to set a value of at least one parameter used to change the value of the current control code, each in a plurality of control modes, based on an operation mode of the integrated circuit, because it provides more efficient control based on the load demand in order to reduce or remove undershoot or overshoot voltage problems (paragraph [0006]).
Allowable Subject Matter
Claims 4-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The closest prior art (which has been made of record) fail to disclose (by themselves or in combination):
Regarding claim 4, the current driving circuitry is further configured to: generate the output current to increase in a stepwise manner while having a first step height, in response to a change in the value of the current control code, in the fast mode in the undershoot period; and generate the output current to increase in the stepwise manner while having a second step height that is lower than the first step height, in response to the change in the value of the current control code, in the slow mode in the undershoot period;
Claims 5 and 6 are dependent claims of claim 4, therefore, are objected for the same reason presented above;
In combination with the additionally claimed features, as are claimed by the Applicant. Thus, the Applicant’s claims are determined to be novel and non-obvious.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838