DETAILED ACTION
This correspondence is in response to the communications received 04/27/2026. Claims 12-23 have been amended. Claims 1-23 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Invention I in the reply filed on 04/27/2026 is acknowledged. The traversal is on the grounds that after amendment claims 13-23, previously drawn to a method of manufacturing a semiconductor device and now drawn to a semiconductor device, would not present a serious search and/or examination burden. However, as amended claims 13-23 now fall under elected Invention I, the traversal is moot. Claims 1-23 are therefore eligible for examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/20/2023 has been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 2 is objected to because of the following informalities: Claim 2 requires “wherein the crack energy release zone comprises at least one metal layer comprising plurality of adjacent metal structures”. It appears this limitation should be written as “wherein the crack energy release zone comprises at least one metal layer comprising a plurality of adjacent metal structures”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-4, 7, 8, and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2-4 specifically require “the crack energy release zone”. Claims 7, 8, and 10 specifically require “the crack take-off zone”. Claim 1 requires “at least one of: a crack energy release zone … or a crack take-off zone”, thus claim 1 does not require both the “crack energy release zone” and the “crack take-off zone”. Therefore claims 2-4, 7, 8, and 10 are indefinite as they include elements not necessarily required by claim 1, thus raising issues with a lack of antecedent basis. Claims 5 and 6 are rejected for their dependency on claim 4. Claim 9 is rejected for its dependency on claim 8.
Claim 6 requires “wherein the plurality of adjacent metal structures have a length longer along a second axis perpendicular to the first axis and a width along the first axis that is smaller than the length along the second axis”. It is unclear as to what the “length longer along a second axis” is being compared with. The “width along the first axis” is separately stated to be “smaller than the length along the second axis”, thus the “length longer along a second axis” appears to either be redundant or referring to an element that is not recited. For the purposes of examination, the above limitation will be interpretated as “wherein the plurality of adjacent metal structures have a length
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, an integrated circuit comprising:
an active area (76); and
a scribe lane (54) beyond the active area (see Fig. 7), wherein the scribe lane comprises at least one of:
a crack energy release zone (60) configured to dissipate fracture energy in an event that a crack were to form in the scribe lane (see [0046]); or
a crack take-off zone (64) configured to, in the event that the crack were to form in the scribe lane, guide the crack out of a surface of the integrated circuit in the crack take-off zone (see [0046]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Independent claim 1 has been interpretated in two ways. Each interpretation of claim 1 and the corresponding dependent claims are labeled in accordance.
Claims 1, 2, 4, 5-10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kaltalioglu et al. (US 8,008,750 B2, published 08/30/2011) in view of Ananiev et al. (US 20220270985 A1, filed 01/24/2022) in view of Yoshizawa et al (US 8,742,547 B2, published 06/03/2014).
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Regarding interpretation one of claim 1, Figs. 1-5 of Kaltalioglu disclose an integrated circuit (“Each die 100 comprises an integrated circuit and is also referred to herein as a semiconductor device or integrated circuit 100”, col. 3, lines 29-31) comprising:
an active area (“die 100 includes a central region 108 that comprises an active region”, col. 3, lines 53-55); and
a scribe lane (“scribe line regions 102”, col. 3, line 33) beyond the active area (as seen in Fig. 2, 102 is beyond 108, here 102 is interpretated as including “barrier structure 104”, col. 3, line 43), wherein the scribe lane comprises at least one of:
a crack energy release zone (“novel crack prevention barrier structure 104”, col. 3, line 43) configured to dissipate fracture energy in an event that a crack were to form in the scribe lane (Kaltalioglu does not specify that 104 is configured to dissipate energy, however a secondary reference will be used to teach this limitation below).
Kaltalioglu does not specifically disclose “a crack energy release zone configured to dissipate fracture energy in an event that a crack were to form in the scribe lane; or
a crack take-off zone configured to, in the event that the crack were to form in the scribe lane, guide the crack out of a surface of the integrated circuit in the crack take-off zone”.
However, in a similar field of endeavor, Ananiev teaches a crack energy release zone configured to dissipate fracture energy in an event that a crack were to form in the scribe lane (“The current approach is to introduce some Crack Stop Structures (CSS) between the chip sidewall (where cracks in most cases start) and the electrically active chip area. Current CSS aim to force the propagating crack to lose as much energy as possible before reaching the electrically active area”, [0003], thus 104 of Kaltalioglu which is a crack stop structure, functions by dissipating energy from any propagating cracks in order to protect 108).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a crack energy release zone configured to dissipate fracture energy in an event that a crack were to form in the scribe lane” as taught by Ananiev in the system of Kaltalioglu for the purpose of explaining how stop crack structures mitigate cracks.
Figs. 1-5 of Kaltalioglu in combination with Ananiev fails to disclose “a crack take-off zone configured to, in the event that the crack were to form in the scribe lane, guide the crack out of a surface of the integrated circuit in the crack take-off zone.”
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However, in a similar field of endeavor, Fig. 8 of Kaltalioglu teaches a crack take-off zone configured to, in the event that the crack were to form in the scribe lane, guide the crack out of a surface of the integrated circuit in the crack take-off zone (Fig. 8 of Kaltalioglu does not specifically disclose a crack take-off zone, however Fig. 8 of Kaltalioglu does teach a dual structure where “the barrier structure 204 comprises a plurality of substantially V-shaped regions 210 arranged in two parallel continuous lines 204a and 204b in”, col. 5, lines 53-55, therefore a secondary reference will be utilized below to substitute one of the continuous lines of Fig. 8 of Kaltalioglu for a crack take-off zone below).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a crack take-off zone configured to, in the event that the crack were to form in the scribe lane, guide the crack out of a surface of the integrated circuit in the crack take-off zone” as taught by Fig. 8 of Kaltalioglu in the system of Kaltalioglu in combination with Ananiev for the purpose of providing enhanced device protection through redundancy of the crack stop structures.
Kaltalioglu in combination with Ananiev fails to disclose “a crack take-off zone configured to, in the event that the crack were to form in the scribe lane, guide the crack out of a surface of the integrated circuit in the crack take-off zone.”
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However, in a similar field of endeavor, Figs. 1-3 of Yoshizawa teach a crack take-off zone configured to, in the event that the crack were to form in the scribe lane, guide the crack out of a surface of the integrated circuit in the crack take-off zone (“crack guard ring 105”, col. 3, line 24, is a crack take-off zone where as seen in Fig. 3, 105 guides “crack 202”, col. 9, line 23, outwards towards a surface of the device structure, thus 105 of Yoshizawa can be substituted for either 204a or 204b of Fig. 8 of Kaltalioglu in order to combine different crack protection strategies into one structure, while claim 1 only requires “a crack energy release zone” or “a crack take-off zone”, both are addressed here in order to more clearly reject the dependent claims).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a crack take-off zone configured to, in the event that the crack were to form in the scribe lane, guide the crack out of a surface of the integrated circuit in the crack take-off zone” as taught by Yoshizawa in the system of Kaltalioglu in combination with Ananiev for the purpose of improving crack protection by incorporating multiple types of crack mitigation designs alongside one another.
Regarding claim 2, Figs. 1-5 and 8 of Kaltalioglu in combination with Ananiev and Figs. 1-3 of Yoshizawa disclose the integrated circuit of interpretation one of claim 1, Fig. 8 of Kaltalioglu further discloses wherein the crack energy release zone comprises at least one metal layer (204 may be metal layers as Kaltalioglu states “In some embodiments of the present invention, the barrier structures 104, 204, 304, 404, 504, 604, and 704 are formed during the formation of metallization layers”, col. 10, lines 17-19) comprising plurality of adjacent metal structures offset from one another in a zig-zag pattern (as seen in Fig. 8, the elements denoted “MS1” and “MS2” are adjacent metal structures offset from one another in a zig-zag pattern).
Regarding claim 4, Figs. 1-5 and 8 of Kaltalioglu in combination with Ananiev and Figs. 1-3 of Yoshizawa disclose the integrated circuit of interpretation one of claim 1, Fig. 8 of Kaltalioglu further discloses wherein the crack energy release zone comprises a plurality of adjacent metal structures (as in Fig. 8, “MS1” and “MS2” are adjacent metal structures where MS1 and MS2 are portions of 204 regarding which Kaltalioglu states “In some embodiments of the present invention, the barrier structures 104, 204, 304, 404, 504, 604, and 704 are formed during the formation of metallization layers”, col. 10, lines 17-19, thus MS1 and MS2 are metal structures being formed of metallization layers) having gaps between them that are not aligned along a first axis (as seen in Fig. 8, the gaps between MS1 and MS2 are not aligned along the horizontal axis which is a first axis) to encourage the crack to propagate in a meandering path rather than straight along the first axis (as seen in Fig. 8, MS1 and MS2 will deflect cracks diagonally thereby resulting in a meandering path rather than permitting propagating along the horizontal axis).
Regarding claim 5, Figs. 1-5 and 8 of Kaltalioglu in combination with Ananiev and Figs. 1-3 of Yoshizawa disclose the integrated circuit of claim 4, Fig. 8 of Kaltalioglu further discloses wherein the first axis comprises a more direct path toward the active area than a second axis perpendicular to the first axis (as seen in Fig. 8, the horizontal axis directly points towards “central region 208 of the die 220 containing the active circuitry”, col. 6, lines 12-13, where 208 of Fig. 8 of Kaltalioglu is equivalent to 108 of Figs. 1-5 of Kaltalioglu, in comparison the vertical axis as seen in Fig. 8, is perpendicular to the horizontal axis and runs parallel to 208 thereby comprising a less direct path than the horizontal axis).
Regarding claim 6, Figs. 1-5 and 8 of Kaltalioglu in combination with Ananiev and Figs. 1-3 of Yoshizawa disclose the integrated circuit of claim 4, Fig. 8 of Kaltalioglu further discloses wherein the plurality of adjacent metal structures have a length longer along a second axis perpendicular to the first axis and a width along the first axis that is smaller than the length along the second axis (as seen in Fig. 8, MS1 and MS2 have a length along the vertical axis, which is perpendicular to the horizontal axis, that is longer than a width of MS1 and MS2 along the horizontal axis).
Regarding claim 7, Figs. 1-5 and 8 of Kaltalioglu in combination with Ananiev and Figs. 1-3 of Yoshizawa disclose the integrated circuit of interpretation one of claim 1, Figs. 1-3 of Yoshizawa further disclose wherein the crack take-off zone comprises a plurality of metal structures (together “first wiring layer … 1w”, col. 6, lines 1 and 2, and “first contact layer (lowermost metal layer) 1c”, col. 4, lines 64-65 form a first metal structure, similarly “fifth wiring layers … 5w”, col. 8, line 6, and “fifth contact layers … 5c”, col. 7, line 47, form a second metal structure, where “the moisture proof ring 104 and crack guard ring 105 are formed by using a process of forming multi-layer wirings to be connected to the transistor TR, i.e., by using a process of repetitively laminating a metal layer as a contact layer and a metal layer as a wiring layer”, col. 3, lines 59-63, thus 1w/1c and 5w/5c are a plurality of metal structures) configured to guide the crack toward the surface of the integrated circuit (as seen in Fig. 3, 105 including 1c, 1w, 5c, and 5w, guides “crack 202”, col. 9, line 23, outwards towards a surface of the device structure).
Regarding claim 8, Figs. 1-5 and 8 of Kaltalioglu in combination with Ananiev and Figs. 1-3 of Yoshizawa disclose the integrated circuit of claim 7, Figs. 1-3 of Yoshizawa further disclose wherein the crack take-off zone comprises a sacrificial crack propagation path between the plurality of metal structures (as seen in Fig. 3, 202 takes a sacrificial crack propagation path between 1c, 1w, 5c, and 5w).
Regarding claim 9, Figs. 1-5 and 8 of Kaltalioglu in combination with Ananiev and Figs. 1-3 of Yoshizawa disclose the integrated circuit of claim 8, Figs. 1-3 of Yoshizawa further disclose wherein the sacrificial crack propagation path comprises:
in a first region nearer to a separation line (“scribe area 103”, col. 3, line 19), a first sacrificial layer (“crack guard insulating film 22”, col. 3, line 40, as seen in Fig. 3, 22 is to the right of the rest of the elements in 105, and is therefore occupying a first region nearer 103) comprising a first space without one of the plurality of metal structures (as seen in Fig. 3, 22 is comprising a first space without 1c, 1w, 5c, and 5w), wherein the first sacrificial layer is beneath at least a first of the plurality of metal structures (as seen in Fig. 3, 22 is below 1c and 1w); and
in a second region farther from the separation line, a second sacrificial layer (“crack guard window 23”, col. 3, lines 41-42, as seen in Fig. 3, 23 is to the left of 22 and is therefore further from 103) comprising a second space without one of the plurality of metal structures (as seen in Fig. 3, 23 is comprising a first space without 1c, 1w, 5c, and 5w), wherein the second sacrificial layer is above at least a second of the plurality of metal structures (as seen in Fig. 3, 22 is above 5c and 5w);
wherein the first sacrificial layer is located nearer to a silicon substrate (“a silicon substrate (semiconductor substrate) 21”, col. 4, lines 14-15) than the second sacrificial layer (as seen in Fig. 3, 22 is located nearer to 21 than 23), thereby causing the sacrificial crack propagation path to traverse a slope over z- and x-directions (as seen in Fig. 3, 202 traverses a slope over vertical and horizontal directions, or z- and x- directions respectively).
Regarding claim 10, Figs. 1-5 and 8 of Kaltalioglu in combination with Ananiev and Figs. 1-3 of Yoshizawa disclose the integrated circuit of claim 7, Figs. 1-3 of Yoshizawa further disclose wherein the crack take-off zone comprises at least one air gap structure (“crack guard window 23”, col. 3, lines 41-42) to guide the crack toward the surface of the integrated circuit (as seen in Fig. 3, 23 guides the crack toward the surface of the device structure).
Regarding claim 12, Figs. 1-5 and 8 of Kaltalioglu in combination with Ananiev and Figs. 1-3 of Yoshizawa disclose the integrated circuit of interpretation one of claim 1.
Figs. 1-5 and 8 of Kaltalioglu in combination with Ananiev and Yoshizawa fail to disclose “wherein the crack energy release zone or the crack take-off zone, or both, comprise a staggered pattern of metal structures in a 45° / 135° arrangement”.
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However, in a similar field of endeavor, Fig. 6 of Kaltalioglu teaches wherein the crack energy release zone or the crack take-off zone, or both, comprise a staggered pattern of metal structures in a 45° / 135° arrangement (“One side of the substantially V-shaped region 110a extends outwardly from the central axis 115 by an angle α1, e.g., to the left in FIG. 6. The other side of the substantially V-shaped region 110a extends outwardly from the central axis 115 by an angle α2 … Angles α1 and α2 may range from greater than about zero to less than about 90 degrees, for example, although alternatively, angles α1 and α2 may also be greater than 90 degrees in some embodiments. The total or sum of angles α1 and α2 may be about 180 degrees or less”, col. 4, lines 64-67, and col. 5, lines 1-11, thus α1 and α2 may be 45° each with supplementary angles of 135°, this arrangement can be then be applied to Fig. 8 of Kaltalioglu).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the crack energy release zone or the crack take-off zone, or both, comprise a staggered pattern of metal structures in a 45° / 135° arrangement” as taught by Fig. 6 of Kaltalioglu in the system of Kaltalioglu in combination with Ananiev and Yoshizawa for the purpose of providing specific angles for the barrier structure.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kaltalioglu et al. (US 8,008,750 B2, published 08/30/2011) in view of Ananiev et al. (US 20220270985 A1, filed 01/24/2022) in view of Yoshizawa et al (US 8,742,547 B2, published 06/03/2014) in view of Sugioka et al. (US 20230090041 A1, filed 09/22/2021).
Regarding claim 11, Figs. 1-5 and 8 of Kaltalioglu in combination with Ananiev and Figs. 1-3 of Yoshizawa disclose the integrated circuit of interpretation one of claim 1.
Figs. 1-5 and 8 of Kaltalioglu in combination with Ananiev and Yoshizawa fail to disclose “wherein the scribe lane comprises test circuitry and wherein the crack energy release zone or the crack take-off zone, or both, are disposed around the test circuitry to protect the test circuitry from damage in the event that the crack were to form”.
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However, in a similar field of endeavor, Fig. 2 of Sugioka teaches wherein the scribe lane comprises test circuitry and wherein the crack energy release zone or the crack take-off zone, or both, are disposed around the test circuitry to protect the test circuitry from damage in the event that the crack were to form (“In some embodiments, the scribe region 108 within each chip 104 (e.g., pad regions 206 of FIG. 2) may include a test element group (not shown) including test circuits. Each scribe region 108 may also include a scribe center region 112 between the adjacent circuit edges 110 of adjacent chips 104. In some embodiments, a dicing line may be defined in the scribe center region 112 for separating the semiconductor wafer 100 into individual semiconductor chips 104”, [0024], where “scribe center region 112 may also include crack mitigation regions 204”, [0027], thus as seen in Fig. 2, 108 comprises test circuitry in 206 that is protected by 204 if a crack were to from in 112).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the scribe lane comprises test circuitry and wherein the crack energy release zone or the crack take-off zone, or both, are disposed around the test circuitry to protect the test circuitry from damage in the event that the crack were to form” as taught by Sugioka for the purpose of monitoring potential crack damage to adjacent chips.
Claims 1 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Kaltalioglu et al. (US 8,008,750 B2, published 08/30/2011) in view of Yoshizawa et al (US 8,742,547 B2, published 06/03/2014).
Regarding interpretation two of claim 1, Figs. 1-5 of Kaltalioglu disclose an integrated circuit (“Each die 100 comprises an integrated circuit and is also referred to herein as a semiconductor device or integrated circuit 100”, col. 3, lines 29-31) comprising:
an active area (“die 100 includes a central region 108 that comprises an active region”, col. 3, lines 53-55); and
a scribe lane (“scribe line regions 102”, col. 3, line 33) beyond the active area (as seen in Fig. 2, 102 is beyond 108, here 102 is interpretated as including “barrier structure 104”, col. 3, line 43), wherein the scribe lane comprises at least one of:
a crack energy release zone (“novel crack prevention barrier structure 104”, col. 3, line 43) configured to dissipate fracture energy in an event that a crack were to form in the scribe lane (Kaltalioglu does not specify that 104 is configured to dissipate energy, however a secondary reference will be used to teach this limitation below); or
a crack take-off zone configured to, in the event that the crack were to form in the scribe lane, guide the crack out of a surface of the integrated circuit in the crack take-off zone.
Kaltalioglu does not specifically disclose “a crack energy release zone configured to dissipate fracture energy in an event that a crack were to form in the scribe lane”.
However, in a similar field of endeavor, Figs. 1-3 of Yoshizawa teach a crack energy release zone (“crack guard ring 105”, col. 3, line 24, equivalent to 104 of Kaltalioglu) configured to dissipate fracture energy in an event that a crack were to form in the scribe lane (as seen in Fig. 3, “crack 202”, col. 9, line 23, travels to and then along 105, one having ordinary skill in the art would understand that forcing 202 to travel along 105, thereby separating adjacent layers, energy from 202 is being dissipated).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a crack energy release zone configured to dissipate fracture energy in an event that a crack were to form in the scribe lane” as taught by Yoshizawa in the system of Kaltalioglu for the purpose of identifying a specific crack propagation pathway.
Regarding claim 3, Figs. 1-5 of Kaltalioglu in combination with Figs. 1-3 of Yoshizawa disclose the integrated circuit of interpretation two of claim 1, Figs. 1-3 of Yoshizawa further disclose wherein the crack energy release zone comprises a plurality of metal and via layers (together “first wiring layer … 1w”, col. 6, lines 1 and 2, “second wiring layer… 2w”, col. 7, lines 25-26, “third and fourth wiring layers 3w and 4w”, col. 7, lines 58-59, and “fifth wiring layers … 5w”, col. 8, line 6, are metal wiring layers where “the moisture proof ring 104 and crack guard ring 105 are formed by using a process of forming multi-layer wirings to be connected to the transistor TR, i.e., by using a process of repetitively laminating a metal layer as a contact layer and a metal layer as a wiring layer”, col. 3, lines 59-63, thus 1w-5w are metal layers. Further as seen in Figs. 2C and 2F, “first contact layer (lowermost metal layer) 1c”, col. 4, lines 64-65, “second contact layer 2c”, col. 6, lines 46-47, “third to [fourth] contact layers 3c to [4c]”, col. 7, lines 52, and “fifth contact layers … 5c”, col. 7, line 47 are via layers) with varying fracture toughness or modulus (as seen in Fig. 2C, 2F, and 3, 1w-5w and 1c-5c have different cross-sectional areas and will therefore have different fracture toughness) to guide the crack through the crack energy release zone toward the surface of the integrated circuit (as seen in Fig. 3, 1w-5w and 1c-5c guide 202 out of the surface of device structure).
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kaltalioglu et al. (US 8,008,750 B2, published 08/30/2011) in view of Wu et al. (US 11,348,881 B2, published 05/31/2022).
Regarding claim 13, Figs. 1-5 of Kaltalioglu discloses integrated circuitry (“Each die 100 comprises an integrated circuit and is also referred to herein as a semiconductor device or integrated circuit 100”, col. 3, lines 29-31) comprising:
a first metal layer with a first set of staggered features (Figs. 1-5 of Kaltalioglu do not specifically disclose a first metal layer with a first set of staggered features, Figs. 1-5 of Kaltalioglu do disclose a “novel crack prevention barrier structure 104”, col. 3, line 43 which will be substituted for the structures taught by secondary references below) in a scribe lane (“scribe line regions 102”, col. 3, line 33) between two integrated circuit active areas (“die 100 includes a central region 108 that comprises an active region”, col. 3, lines 53-55, as seen in Fig. 2, 102 is between two instances of 108).
Figs. 1-5 of Kaltalioglu do not disclose “a first metal layer with a first set of staggered features;
a first via layer with a first set of staggered vias connected to at least some of the first set of staggered features of the first metal layer in the scribe lane; and
a second metal layer with a second set of staggered features in the scribe lane, at least some of which are joined to the first set of staggered vias of in the scribe lane, collectively comprising an energy release zone of the scribe lane to enable fracture energy to dissipate in an event that a crack were to form in the scribe lane”.
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However, in a similar field of endeavor, Figs. 1A-1C of Wu teach a first metal layer (as seen in Fig. 1B, the uppermost instances of “plurality of conductive wires 108”, col. 3, line 61 are a first metal layer) with a first set of staggered features (together the left and right instances of the uppermost of 108 are a first set of features, Wu does not disclose that they are staggered, however a secondary reference will be used to teach this limitation below);
a first via layer (“plurality of conductive vias 110”, col. 3, line 62) with a first set of staggered vias (together all of the vias of 110 form a first set of vias, Wu does not disclose that they are staggered, however a secondary reference will be used to teach this limitation below) connected to at least some of the first set of staggered features of the first metal layer in the scribe lane (as seen in Fig. 1B, 110 are connected to the uppermost instances of 108); and
a second metal layer (as seen in Fig. 1B, the lowermost instances of 108 are a second metal layer) with a second set of staggered features (together the left and right instances of the lowermost of 108 are a second set of features, Wu does not disclose that they are staggered, however a secondary reference will be used to teach this limitation below) in the scribe lane (after substation into the structure of Kaltalioglu, all instances of 108 will be in 102 of Kaltalioglu), at least some of which are joined to the first set of staggered vias of in the scribe lane (as seen in Fig. 1B, the lowermost instances of 108 are joined to 110), collectively comprising an energy release zone of the scribe lane to enable fracture energy to dissipate in an event that a crack were to form in the scribe lane (as seen in Fig. 1B, 108 and 110 are elements in “seal ring structure 112”, col. 5, lines 49-50, where “the seal ring structure 112 and the crack-stop structure 107 are configured to prevent damage to semiconductor devices (not shown) and/or the photodetectors disposed within the device region 109 while performing a singulation process along the first and/or second scribe lines 103, 105. This in turn may prevent and/or stop a cracking or breaking of the lattice structure of the semiconductor substrate 114, thereby increasing a process yield of the singulation process performed on the dies 101a-d”, col. 5, lines 49-58, thus one having ordinary skill in the art would recognize that in order to stop a crack, 108 and 110 will necessarily dissipate energy).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a first metal layer with a first set of staggered features;
a first via layer with a first set of staggered vias connected to at least some of the first set of staggered features of the first metal layer in the scribe lane; and
a second metal layer with a second set of staggered features in the scribe lane, at least some of which are joined to the first set of staggered vias of in the scribe lane, collectively comprising an energy release zone of the scribe lane to enable fracture energy to dissipate in an event that a crack were to form in the scribe lane” as taught by Wu in the system of Kaltalioglu for the purpose of describing the vertical arrangement of the crack stop structure.
Figs. 1-5 of Kaltalioglu in combination with Wu do not disclose “a first metal layer with a first set of staggered features;
a first via layer with a first set of staggered vias … and
a second metal layer with a second set of staggered features”.
However, in a similar field of endeavor, Fig. 8 of Kaltalioglu teaches “a first metal layer with a first set of staggered features;
a first via layer with a first set of staggered vias … and
a second metal layer with a second set of staggered features” (as seen in Fig. 8 of Kaltalioglu, “the barrier structure 204”, col. 5, line 53, has a staggered structure, therefore after substitution of 108 and 110 of Wu into Kaltalioglu, 108 and 110 will also be staggered).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a first metal layer with a first set of staggered features;
a first via layer with a first set of staggered vias … and
a second metal layer with a second set of staggered features” as taught by Fig. 8 of Kaltalioglu in the system of Kaltalioglu in combination with Wu for the purpose of increasing crack stop structure density to provide additional crack prevention.
Regarding claim 14, Figs. 1-5 and 8 of Kaltalioglu in combination with Figs. 1A-1C of Wu disclose the integrated circuit of claim 13, Figs. 1A-1C of Wu further disclose wherein the first metal layer comprises the first set of staggered features (as discussed above, the uppermost instances of 108 comprise the left and right instances of the uppermost of 108) and the second metal layer comprises the second set of staggered features (as discussed above, the lowermost instances of 108 comprise the left and right instances of the lowermost of 108), wherein the first set of staggered features and the second set of staggered features are identical (as seen in Fig. 1B, the uppermost instances of 108 and the lowermost instances of 108 are identical).
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kaltalioglu et al. (US 8,008,750 B2, published 08/30/2011) in view of Wu et al. (US 11,348,881 B2, published 05/31/2022) in view of Yeo et al. (US 8048761 B2, published 11/01/2011.
Regarding claim 16, Figs. 1-5 and 8 of Kaltalioglu in combination with Figs. 1A-1C of Wu disclose the integrated circuit of claim 14, Figs. 1A-1C of Wu further disclose wherein the first metal layer comprises the first set of staggered features (as discussed above, the uppermost instances of 108 comprise the left and right instances of the uppermost of 108) and the second metal layer comprises the second set of staggered features (as discussed above, the lowermost instances of 108 comprise the left and right instances of the lowermost of 108),
Kaltalioglu in combination with Wu fails to disclose “wherein the first set of staggered features and the second set of staggered features are different”.
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However, in a similar field of endeavor, Fig. 3B of Yeo teaches wherein the first set of staggered features and the second set of staggered features are different (as seen in Fig. 3, the “nine metal layers 314 are shown (M1-M8 and LB (metallization pad)”, col. 3, lines 35-36, where LB is a first set of features and M1 is a second set of features, LB and M1 are different).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the first set of staggered features and the second set of staggered features are different” as taught by Yeo in the system of Kaltalioglu in combination with Wu for the purpose of adding redundancy such that if one crack stop structure is damaged, a second structure is still able to provide crack protection.
Regarding claim 17, Figs. 1-5 and 8 of Kaltalioglu in combination with Figs. 1A-1C of Wu and Fig. 3B of Yeo disclose the integrated circuit of claim 16, Fig. 3B of Yeo further discloses wherein the second set of staggered features has more smaller features than the first set of staggered features (as seen in Fig. 3B, M1 has more smaller features than LB).
Claim 18-21 are rejected under 35 U.S.C. 103 as being unpatentable over Kaltalioglu et al. (US 8,008,750 B2, published 08/30/2011) in view of Yoshizawa et al (US 8,742,547 B2, published 06/03/2014) in view of Wang et al. (US 9,406,625 B2, published 08/02/2016).
Regarding claim 18, Figs. 1-5 of Kaltalioglu discloses integrated circuitry (“Each die 100 comprises an integrated circuit and is also referred to herein as a semiconductor device or integrated circuit 100”, col. 3, lines 29-31) comprising:
a first metal layer (Kaltalioglu does not teach a specific first metal layer or first metal structure, however, Kaltalioglu does disclose a “novel crack prevention barrier structure 104”, col. 3, line 43, that will be substituted for the structure taught by a secondary reference below) in a scribe lane (“scribe line regions 102”, col. 3, line 33) of a silicon wafer (“semiconductor wafer 101”, col. 3, line 23, Kaltalioglu does not specifically teach a silicon wafer, however a secondary reference will be used to teach this below) with a first metal structure.
Kaltalioglu fails to disclose “a first metal layer in a scribe lane of a silicon wafer with a first metal structure; and
a second metal layer in the scribe lane of the silicon wafer with a second metal structure, wherein the first and second metal structures are configured to guide, in an event that a crack were to form in the scribe lane, the crack out toward a surface of the silicon wafer.”
However, in a similar field of endeavor, Figs. 1-3 of Yoshizawa teach a first metal layer (“first wiring layer … 1w”, col. 6, lines 1 and 2 where “the moisture proof ring 104 and crack guard ring 105 are formed by using a process of forming multi-layer wirings to be connected to the transistor TR, i.e., by using a process of repetitively laminating a metal layer as a contact layer and a metal layer as a wiring layer”, col. 3, lines 59-63, and as seen in Fig. 2C, 1w is an element of 105 and thus a metal layer) in a scribe lane of a silicon wafer (after substitution of 105 of Yoshizawa for 104 of Kaltalioglu, 105 of Yoshizawa will be in 102 of Kaltalioglu) with a first metal structure (together 1w and “first contact layer (lowermost metal layer) 1c”, col. 4, lines 64-65, form a first metal structure); and
a second metal layer (“fifth wiring layers … 5w”, col. 8, line 6, similar to 1w and 1c, 5w is also a metal layer) in the scribe lane of the silicon wafer (as seen in Fig. 2F, 5w is also an element of 105, and will also be in 102 of Kaltalioglu after substitution) with a second metal structure (together 5w and “fifth contact layers … 5c”, col. 7, line 47, form a second metal structure), wherein the first and second metal structures are configured to guide, in an event that a crack were to form in the scribe lane, the crack out toward a surface of the silicon wafer (as seen in Fig. 3, 105 including 1c, 1w, 5c, and 5w, guides “crack 202”, col. 9, line 23, outwards towards a surface of the device structure).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a first metal layer in a scribe lane of a silicon wafer with a first metal structure; and
a second metal layer in the scribe lane of the silicon wafer with a second metal structure, wherein the first and second metal structures are configured to guide, in an event that a crack were to form in the scribe lane, the crack out toward a surface of the silicon wafer” as taught by Yoshizawa in the system of Kaltalioglu for the purpose of steering cracks entirely out of the device structure.
Kaltalioglu in combination with Yoshizawa fails to disclose “a silicon wafer”.
However, in a similar field of endeavor, Wang teaches a silicon wafer (“An individual integrated circuit or chip is usually formed from a larger, semiconductor wafer, which usually comprises primarily silicon”, col. 1, lines 10-12, thus 101 of Kaltalioglu which is a semiconductor wafer, could be formed from silicon).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a silicon wafer” as taught by Wang in the system of Kaltalioglu in combination with Yoshizawa for the purpose of identifying a specific semiconducting material for the wafer.
Regarding claim 19, Figs. 1-5 of Kaltalioglu in combination with Figs. 1-3 of Yoshizawa and Wang disclose the integrated circuitry of claim 18, Figs. 1-3 of Yoshizawa further disclose wherein the first metal layer comprises a lower metal layer (as seen in Fig. 2C, 1W is a lower metal layer) and the second metal layer comprises an upper metal layer (as seen in Fig. 2F, 5w is an upper metal layer), wherein space between the first and second metal structures comprises a sacrificial pathway to enable the crack to pass through toward the surface of the silicon wafer (as seen in Fig. 3, space between 1c/1w and 5c/5w comprises a sacrificial pathway to enable 202 to pass through toward the surface of the device structure).
Regarding claim 20, Figs. 1-5 of Kaltalioglu in combination with Figs. 1-3 of Yoshizawa and Wang disclose the integrated circuitry of claim 18, Figs. 1-3 of Yoshizawa further disclose comprising a plurality of additional metal layers (together “second wiring layer… 2w”, col. 7, lines 25-26, and “third and fourth wiring layers 3w and 4w”, col. 7, lines 58-59) comprising additional metal structures (2w, 3w, and 4w together with “second contact layer 2c”, col. 6, lines 46-47, and “third to [fourth] contact layers 3c to [4c]”, col. 7, lines 52, respectively form additional metal structures) configured to guide, in the event that the crack were to form in the scribe lane, the crack out toward a surface of the silicon wafer in concert with the first metal structure and the second metal structure (as seen in Fig. 3, 2c-4c and 2w-4w in concert with 1c/1w and 5c/5w guide 202 out toward a surface of the device structure).
Regarding claim 21, Figs. 1-5 of Kaltalioglu in combination with Figs. 1-3 of Yoshizawa and Wang disclose the integrated circuitry of claim 18, Figs. 1-3 of Yoshizawa further disclose comprising an air gap structure (“crack guard window 23”, col. 8, line 40, as seen in Fig. 3, 23 is a window) as a sacrificial pathway to enable the crack to pass through toward the surface of the silicon wafer (as seen in Fig. 3, 202 passes through 23).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Kaltalioglu et al. (US 8,008,750 B2, published 08/30/2011) in view of Yoshizawa et al (US 8,742,547 B2, published 06/03/2014) in view of Wang et al. (US 9,406,625 B2, published 08/02/2016) in view of Bao et al. (US 9,536,842 B2, published 01/03/2026).
Regarding claim 23, Figs. 1-5 of Kaltalioglu in combination with Figs. 1-3 of Yoshizawa and Wang disclose the integrated circuitry of claim 21.
Kaltalioglu in combination with Yoshizawa and Wang fails to disclose “comprising a plurality of additional air gap structures”.
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However, in a similar field of endeavor, Fig. 7 of Bao teaches comprising a plurality of additional air gap structures (as seen in Fig. 7, “line level air gaps or the crack stops 128, 142, 148”, col. 9, lines 27-28, are a plurality of additional air gaps that could be incorporated into the structure of Yoshizawa).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “comprising a plurality of additional air gap structures” as taught by Bao in the system of Kaltalioglu in combination with Yoshizawa and Wang for the purpose of incorporating additional air gaps to increase the probability of a crack terminating in an air gap.
Allowable Subject Matter
Claims 15 and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or fairly suggest the integrated circuitry as recited in the claims of the instant application.
Regarding claim 15, the prior art of Kaltalioglu et al. (US 8,008,750 B2) in view of Wu et al. (US 11,348,881 B2) discloses similar integrated circuitry but fails to disclose the specific claims of the instant application regarding the arrangement of the second via layer, the second set of staggered features of the second metal layer and the first set of staggered vias e.g. “comprising a second via layer with a second set of staggered vias connected to at least some of the second set of staggered features of the second metal layer, wherein the second set of staggered vias are offset in at least one axis from the first set of staggered vias”.
Regarding claim 22, the prior art of Kaltalioglu et al. (US 8,008,750 B2) in view of Yoshizawa et al (US 8,742,547 B2) in view of Wang et al. (US 9,406,625 B2) discloses similar integrated circuitry but fails to disclose the specific claims of the instant application regarding the arrangement of the air gap structure and a redistribution layer e.g. “wherein the air gap structure is disposed in a redistribution layer (RDL) of the scribe lane”.
Conclusion
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
