Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6, 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (CN 109817753 A) hereafter referred to as Huang
In regard to claim 1 Huang teaches a photodiode module [“a 4-quadrant silicon-based PIN photoelectric detector, the structure shown in FIG. 2”] comprising:
a submount [see “the ceramic substrate 3 fixed on the base 4”];
a photodiode chip [“PIN photodiode 1”] on the submount; and
a heating element formed [“the PIN photodiode 1 adhered to the bottom heating element 2, the heating element 2 integrated to inside bearing PIN photodiode 3 of the ceramic substrate 1, as shown in Figure 3, the PIN photodiode 1 and heating the ceramic substrate 3 fixed on the base 4”] within or on the submount vertically below the photodiode chip.
In regard to claim 6 Huang teaches wherein the heating element is formed within [see “the heating element of heating of PIN photodiode integrated into the tray (e.g., ceramic substrate) inside bearing PIN photodiodes”] a top surface of the submount.
In regard to claim 7 Huang teaches wherein the heating element is controlled by a controller [see this controller is taught implicitly “when heating the PIN photodiode to temperature fluctuation is kept at a fixed range (i.e., the PIN photodiode chip temperature rises to a certain range, the temperature fluctuation is maintained at a relatively small range) stopping heating, ensures the stability of PIN photodiode response” “using closed-loop or open-loop mode feedback and the PIN photodiode temperature control, product usage, the user can select according to the demand for open-loop or closed-loop control method realizing of PIN diode temperature constant”] to heat the photodiode chip.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shi et al. (US 20160155883 A1) hereafter referred to as Shi in view of Huang et al. (CN 109817753 A) hereafter referred to as Huang.
In regard to claim 1 Shi teaches a photodiode module [“FIG. 1 shows a conventional 6-pin TO-header solution for Ge/Si APD. (a) TO-header mounted with Ge/Si APD chip and resistor heater and (b) Ge/Si APD chip”] comprising:
a submount [see Fig. 1 see “6-pin transistor outline (TO)-header”];
a photodiode chip [see Fig. 1 see “Ge/Si APD chip”] on the submount; and
a heating element [see Fig. 1 see “Resistor heater” “a 30Ω resistor” “When a 3.3V bias voltage is applied on the resistor, the heat generated in the resistor can heat up the TO-header and increase TO temperature by about tens of degrees depending on consumption power”] formed within or on the submount
but does not teach vertically below the photodiode chip.
Huang teaches a photodiode module [“a 4-quadrant silicon-based PIN photoelectric detector, the structure shown in FIG. 2”] comprising:
a submount [see “the ceramic substrate 3 fixed on the base 4”];
a photodiode chip [“PIN photodiode 1”] on the submount; and
a heating element formed [“the PIN photodiode 1 adhered to the bottom heating element 2, the heating element 2 integrated to inside bearing PIN photodiode 3 of the ceramic substrate 1, as shown in Figure 3, the PIN photodiode 1 and heating the ceramic substrate 3 fixed on the base 4” “In order to reduce the size of the device, the heating element of heating of PIN photodiode integrated into the tray (e.g., ceramic substrate) inside bearing PIN photodiodes”] within or on the submount vertically below the photodiode chip,
see also “A method for improving the PIN photodiode responsivity, bottom heating element, the PIN photodiode bonded by heating is a PIN photodiode to improve the response degree, when heating the PIN photodiode to temperature fluctuation is kept at a fixed range (i.e., the PIN photodiode chip temperature rises to a certain range, the temperature fluctuation is maintained at a relatively small range) stopping heating, ensures the stability of PIN photodiode response” “using closed-loop or open-loop mode feedback and the PIN photodiode temperature control, product usage, the user can select according to the demand for open-loop or closed-loop control method realizing of PIN diode temperature constant”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shi to include a heating element in an insulator like Huang teaches ( see above ceramic is an example insulator), underneath the “Ge/Si APD chip” of Shi i.e. between the APD chip and the “6-pin transistor outline (TO)-header” i.e. to modify Shi to include vertically below the photodiode chip.
See in the combination of Shi and Huang, see that the ceramic substrate 3 of Huang i.e. the insulating substrate having the heater in the combination of Shi and Huang can itself be called the submount.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is better heating by applying the heater to the bottom of the Ge/Si APD chip.
In regard to claim 3 Shi and Huang as combined does not specifically teach wherein the heating element is smaller in length and width than the photodiode chip.
However see Huang teaches “In order to reduce the size of the device” see claim 5 “bottom of the PIN photodiode bonded heating element”, see that only the photodiode needs to be heated, thus the maximum size of the heater need not be larger than the photodiode, see Shi Fig. 4 the “heater 405” is shown smaller than the “Ge/Si avalanche photodiode 404”.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein the heating element is smaller in length and width than the photodiode chip”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 4 Shi and Huang as combined does not specifically teach further comprising: a first heating element contact; and a second heating element contact, wherein the first heating element contact and the second heating element contact are in electrical contact with the heating element and are positioned on the submount.
However see Shi Fig. 2, Fig. 3 see the contacts on the heater 305 “electrically-conductive pads (e.g., aluminum pads) may be formed on top of the at least one heater 205 and Ge/Si avalanche photodiode 204, respectively, after a pad open process” “apply a proper bias voltage on the at least one heater 305, i.e., to activate or turn on the at least one heater 305”, see paragraph 0041 “performing a dielectric etch process to fabricate one or more contacts; performing a salicide process; performing a metal deposition process; and performing a metal etch process”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shi to include further comprising: a first heating element contact; and a second heating element contact, wherein the first heating element contact and the second heating element contact are in electrical contact with the heating element and are positioned on the submount.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is apply a proper bias voltage on the heater i.e., to activate it and turn it on.
In regard to claim 5 Shi and Huang as combined does not state further comprising:an electrical isolator positioned between the heating element and the photodiode chip.
However see Huang “the heating element of heating of PIN photodiode integrated into the tray (e.g., ceramic substrate) inside bearing PIN photodiodes” see that ceramic is an insulator.
See Shi “As shown in FIG. 3, Ge/Si avalanche photodiode 304 includes at least one integrated heater formed on a top portion of a Si substrate layer 301 underneath a buried oxide (BOX) layer 302 of a silicon-on-insulator (S01) substrate 310”, see claim 6 “wherein the Ge/Si avalanche photodiode further comprises one or more electrodes, wherein the at least one heater comprises one or more electrodes different than and separate from the one or more electrodes of the Ge/Si avalanche photodiode”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shi to include further comprising:an electrical isolator positioned between the heating element and the photodiode chip.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to obtain electrical isolation to operate the heater independently and the photodiode independently without affecting each other.
In regard to claim 6 Shi and Huang as combined teaches [see combination, see Huang “the heating element of heating of PIN photodiode integrated into the tray (e.g., ceramic substrate) inside bearing PIN photodiodes”, See in the combination of Shi and Huang, see that the ceramic substrate 3 of Huang i.e. the insulating substrate having the heater in the combination of Shi and Huang can itself be called the submount.] wherein the heating element is formed within a top surface of the submount.
In regard to claim 7 Shi and Huang as combined teaches wherein the heating element is controlled by a controller [see this controller is taught implicitly “One approach to maintain Ge PD performance at lower temperature is to mount a 30Ω resistor on the top-surface of a 6-pin transistor outline (TO)-header, as illustrated in FIG. 1. When a 3.3V bias voltage is applied on the resistor, the heat generated in the resistor can heat up the TO-header and increase TO temperature by about tens of degrees depending on consumption power. Accordingly, the sensitivity performance of Ge/Si APDs can be improved to meet specified requirements”, see that some “controller” must be performing the act of “When a 3.3V bias voltage is applied”, thus controller is taught implicitly ] to heat the photodiode chip.
See that in Fig. 1 Shi does not mention the control loop, however see Fig. 2 “When the environmental temperature decreases to a certain point, e.g., below a threshold temperature, a temperature control loop may be automatically triggered to apply a proper bias voltage on the at least one heater 205, i.e., to activate or turn on the at least one heater 205. Accordingly, the temperature of the junction region of Ge/Si avalanche photodiode 204 may be increased efficiently and quickly. Temperature is kept within an optimized range to maintain a high level of sensitivity of Ge/Si avalanche photodiode 204 as well as a low bit-error rate level of Ge/Si avalanche photodiode 204”.
Thus although this is not claimed, the Examiner is giving a 103 combination.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shi Fig. 1 to include the control loop of Fig. 2.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to perform good control of the temperature of the photodiode.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shi and Huang as combined and further in view of Lebby et al. (US 6999644 B1) hereafter referred to as Lebby.
In regard to claim 2 Shi and Huang as combined does not teach further comprising:a fiber pigtailed package enclosing the photodiode chip.
See Shi teaches packages, see Fig. 1, Fig. 5 the “TO-header 521, a TO-cap 522” together form a package, “FIG. 5 shows a design of a 6-pin TO solution mounted with heater integrated Ge/Si APD in accordance with an embodiment of the present disclosure”, see paragraph 0003 “Avalanche photodiodes (APDs) are widely utilized for fiber-optic communications due to higher sensitivity”.
See the combination of Shi and Huang, see that the ceramic substrate 3 of Huang i.e. the insulating substrate having the heater in the combination of Shi and Huang can itself be called the submount.
See Huang base 4 has a plurality of layers.
See Lebby “Referring additionally to FIGS. 28 and 29, the optoelectric package, including optoelectric module 10 enclosed in housing 80, is illustrated in a discrete pigtail arrangement” “FIGS. 28 and 29 are two isometric views of the optoelectric package of FIG. 24 pigtailed with an optical fiber” see packaging examples “Turning now to FIGS. 18, 19, and 20, another housing 80 is illustrated for enclosing and mounting a discrete optoelectric module. Housing 80 has a substantially rectangular cross-section with a small opening 81 at one end and a larger opening or substantially hollow interior 82 accessible at the other end. A pair of mounting pins 84 extend from the lower surface for surface mounting the complete package. It will of course be understood that other shapes, both interior and exterior, may be devised for specific applications, and other or additional mounting pins or other mounting devices may be devised for specific mounting situations. (28) Turning to FIGS. 21, 22, and 23, an optoelectric module 10, with a multilayer hermetic ceramic package including a connection board (e.g., connection board 64) having outwardly extending leads 65 attached thereto, is provided. Module 10 may be, for example, similar to the optoelectric module described and illustrated in FIGS. 1 and 2. Optical fiber receiving opening 21 in receptacle 20 can best be seen in FIG. 23. (29) Referring additionally to FIGS. 24, 25, 26, and 27, module 10 of FIG. 21 is placed in housing 80 of FIG. 20 so that the end of receptacle 20 extends slightly through opening 81. Also, as can best be seen in FIG. 24 or 26, connection board 64 is positioned to seal opening 82 in housing 80. Alternatively, connection board 64 is sealed in opening 82 by some convenient means, such as epoxy or the like. In a preferred embodiment, module 10 is press fitted directly into housing 80. In some embodiments housing 80 may be lined with metal or completely formed of metal to provide EMI shielding”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shi to include further comprising:a fiber pigtailed package enclosing the photodiode chip.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that packaging is useful to protect device with good output pin configuration and fiber pigtailed package is known to give good results to transfer light into photodiode.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shi and Huang as combined and further in view of Liu et al. (CN 112103276 A) hereafter referred to as Liu.
In regard to claim 8 Shi and Huang as combined does not teach further comprising:a thermistor positioned to detect a temperature of the heating element, the thermistor to send temperature measurements to a controller and the controller to control, by at least one hardware processor, the temperature of the heating element based on the temperature measurements.
However see Shi paragraph 0017 “When the environmental temperature decreases to a certain point, e.g., below a threshold temperature, a temperature control loop may be automatically triggered to apply a proper bias voltage on the at least one heater 205, i.e., to activate or turn on the at least one heater 205”.
However this is common in the art see Liu teaches “Preferably, avalanche photoelectric detector of the integrated filter amplifying chip further comprises a temperature control circuit, the temperature control circuit comprises a temperature collecting ADC; processor and refrigerator; the temperature collecting ADC is connected with two ends of the thermistor; the refrigerator driving is connected with the refrigerator; one end of the processor is connected with the temperature collecting ADC; the other end is connected with the refrigerator driving; the temperature control circuit is set on the non-cooling area of the ceramic substrate; and it is also sealed in the shell. in the working process of the detector, adjusting the refrigerating power of the refrigerator according to the temperature change, making the APD work in a stable low temperature environment, and the reverse bias voltage and the gate control signal size are unchanged, so as to ensure low APD dark current noise; high sensitivity state, so the detector can keep stable detection efficiency” “Preferably, the avalanche photoelectric detector further comprises a thermistor; when the APD chip temperature changes, the resistance of the thermistor will change, and feedback to the processor through the temperature collecting ADC; the processor controls the refrigerator to drive according to the resistance value fed back by the temperature collecting ADC; The refrigerator drives and controls the refrigerating power of the refrigerator. namely adjusting different refrigerating power according to different temperature, the working temperature of the APD chip is constant”
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shi to include further comprising:a thermistor positioned to detect a temperature of the heating element, the thermistor to send temperature measurements to a controller and the controller to control, by at least one hardware processor, the temperature of the heating element based on the temperature measurements.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that control circuit elements such as thermistor, processor are standard in the art and are known to provide good results for controlling temperature
Claim(s) 9, 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shi et al. (US 20160155883 A1) hereafter referred to as Shi in view of Huang et al. (CN 109817753 A) hereafter referred to as Huang.
In regard to claim 9 Shi teaches a photodiode module [“FIG. 1 shows a conventional 6-pin TO-header solution for Ge/Si APD. (a) TO-header mounted with Ge/Si APD chip and resistor heater and (b) Ge/Si APD chip”] comprising:
a submount [see Fig. 1 see “6-pin transistor outline (TO)-header”];
an avalanche photodiode [see Fig. 1 see “Ge/Si APD chip”] chip on the submount; and
a heating element [see Fig. 1 see “Resistor heater” “a 30Ω resistor” “When a 3.3V bias voltage is applied on the resistor, the heat generated in the resistor can heat up the TO-header and increase TO temperature by about tens of degrees depending on consumption power”] formed within or on the submount
but does not teach vertically below the avalanche photodiode chip.
Huang teaches a photodiode module [“a 4-quadrant silicon-based PIN photoelectric detector, the structure shown in FIG. 2”] comprising:
a submount [see “the ceramic substrate 3 fixed on the base 4”];
a photodiode chip [“PIN photodiode 1”] on the submount; and
a heating element formed [“the PIN photodiode 1 adhered to the bottom heating element 2, the heating element 2 integrated to inside bearing PIN photodiode 3 of the ceramic substrate 1, as shown in Figure 3, the PIN photodiode 1 and heating the ceramic substrate 3 fixed on the base 4” “In order to reduce the size of the device, the heating element of heating of PIN photodiode integrated into the tray (e.g., ceramic substrate) inside bearing PIN photodiodes”] within or on the submount vertically below the photodiode chip,
see also “A method for improving the PIN photodiode responsivity, bottom heating element, the PIN photodiode bonded by heating is a PIN photodiode to improve the response degree, when heating the PIN photodiode to temperature fluctuation is kept at a fixed range (i.e., the PIN photodiode chip temperature rises to a certain range, the temperature fluctuation is maintained at a relatively small range) stopping heating, ensures the stability of PIN photodiode response” “using closed-loop or open-loop mode feedback and the PIN photodiode temperature control, product usage, the user can select according to the demand for open-loop or closed-loop control method realizing of PIN diode temperature constant”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shi to include a heating element in an insulator like Huang teaches ( see above ceramic is an example insulator), underneath the “Ge/Si APD chip” of Shi i.e. between the APD chip and the “6-pin transistor outline (TO)-header” i.e. to modify Shi to include vertically below the avalanche photodiode chip.
See in the combination of Shi and Huang, see that the ceramic substrate 3 of Huang i.e. the insulating substrate having the heater in the combination of Shi and Huang can itself be called the submount.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is better heating by applying the heater to the bottom of the Ge/Si APD chip.
In regard to claim 11 Shi and Huang as combined does not specifically teach wherein the heating element is smaller in length and width than the avalanche photodiode chip.
However see Huang teaches “In order to reduce the size of the device” see claim 5 “bottom of the PIN photodiode bonded heating element”, see that only the photodiode needs to be heated, thus the maximum size of the heater need not be larger than the photodiode, see Shi Fig. 4 the “heater 405” is shown smaller than the “Ge/Si avalanche photodiode 404”.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein the heating element is smaller in length and width than the photodiode chip”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
In regard to claim 12 Shi and Huang as combined does not specifically teach further comprising:a first heating element contact; anda second heating element contact, wherein the first heating element contact and the second heating element contact are in electrical contact with the heating element and are positioned on the submount.
However see Shi Fig. 2, Fig. 3 see the contacts on the heater 305 “electrically-conductive pads (e.g., aluminum pads) may be formed on top of the at least one heater 205 and Ge/Si avalanche photodiode 204, respectively, after a pad open process” “apply a proper bias voltage on the at least one heater 305, i.e., to activate or turn on the at least one heater 305”, see paragraph 0041 “performing a dielectric etch process to fabricate one or more contacts; performing a salicide process; performing a metal deposition process; and performing a metal etch process”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shi to include further comprising:a first heating element contact; anda second heating element contact, wherein the first heating element contact and the second heating element contact are in electrical contact with the heating element and are positioned on the submount.
The motivation is apply a proper bias voltage on the heater i.e., to activate it and turn it on.
In regard to claim 13 Shi and Huang as combined does not state further comprising:an electrical isolator positioned between the heating element and the avalanche photodiode chip.
However see Huang “the heating element of heating of PIN photodiode integrated into the tray (e.g., ceramic substrate) inside bearing PIN photodiodes” see that ceramic is an insulator.
See Shi “As shown in FIG. 3, Ge/Si avalanche photodiode 304 includes at least one integrated heater formed on a top portion of a Si substrate layer 301 underneath a buried oxide (BOX) layer 302 of a silicon-on-insulator (S01) substrate 310”, see claim 6 “wherein the Ge/Si avalanche photodiode further comprises one or more electrodes, wherein the at least one heater comprises one or more electrodes different than and separate from the one or more electrodes of the Ge/Si avalanche photodiode”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shi to include further comprising:an electrical isolator positioned between the heating element and the avalanche photodiode chip.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to obtain electrical isolation to operate the heater independently and the photodiode independently without affecting each other.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shi and Huang as combined and further in view of Lebby et al. (US 6999644 B1) hereafter referred to as Lebby.
In regard to claim 10 Shi and Huang as combined does not teach further comprising:a fiber pigtailed package enclosing the avalanche photodiode chip.
See Shi teaches packages, see Fig. 1, Fig. 5 the “TO-header 521, a TO-cap 522” together form a package, “FIG. 5 shows a design of a 6-pin TO solution mounted with heater integrated Ge/Si APD in accordance with an embodiment of the present disclosure”, see paragraph 0003 “Avalanche photodiodes (APDs) are widely utilized for fiber-optic communications due to higher sensitivity”.
See the combination of Shi and Huang, see that the ceramic substrate 3 of Huang i.e. the insulating substrate having the heater in the combination of Shi and Huang can itself be called the submount.
See Huang base 4 has a plurality of layers.
See Lebby “Referring additionally to FIGS. 28 and 29, the optoelectric package, including optoelectric module 10 enclosed in housing 80, is illustrated in a discrete pigtail arrangement” “FIGS. 28 and 29 are two isometric views of the optoelectric package of FIG. 24 pigtailed with an optical fiber” see packaging examples “Turning now to FIGS. 18, 19, and 20, another housing 80 is illustrated for enclosing and mounting a discrete optoelectric module. Housing 80 has a substantially rectangular cross-section with a small opening 81 at one end and a larger opening or substantially hollow interior 82 accessible at the other end. A pair of mounting pins 84 extend from the lower surface for surface mounting the complete package. It will of course be understood that other shapes, both interior and exterior, may be devised for specific applications, and other or additional mounting pins or other mounting devices may be devised for specific mounting situations. (28) Turning to FIGS. 21, 22, and 23, an optoelectric module 10, with a multilayer hermetic ceramic package including a connection board (e.g., connection board 64) having outwardly extending leads 65 attached thereto, is provided. Module 10 may be, for example, similar to the optoelectric module described and illustrated in FIGS. 1 and 2. Optical fiber receiving opening 21 in receptacle 20 can best be seen in FIG. 23. (29) Referring additionally to FIGS. 24, 25, 26, and 27, module 10 of FIG. 21 is placed in housing 80 of FIG. 20 so that the end of receptacle 20 extends slightly through opening 81. Also, as can best be seen in FIG. 24 or 26, connection board 64 is positioned to seal opening 82 in housing 80. Alternatively, connection board 64 is sealed in opening 82 by some convenient means, such as epoxy or the like. In a preferred embodiment, module 10 is press fitted directly into housing 80. In some embodiments housing 80 may be lined with metal or completely formed of metal to provide EMI shielding”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shi to include further comprising:a fiber pigtailed package enclosing the avalanche photodiode chip.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that packaging is useful to protect device with good output pin configuration and fiber pigtailed package is known to give good results to transfer light into photodiode.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shi and Huang as combined and further in view of Liu et al. (CN 112103276 A) hereafter referred to as Liu.
In regard to claim 14 Shi and Huang as combined does not teach further comprising: a thermistor positioned to detect a temperature of the heating element, the thermistor to send temperature measurements to a controller and the controller to control the temperature of the heating element based on the temperature measurements.
However see Shi paragraph 0017 “When the environmental temperature decreases to a certain point, e.g., below a threshold temperature, a temperature control loop may be automatically triggered to apply a proper bias voltage on the at least one heater 205, i.e., to activate or turn on the at least one heater 205”.
However this is common in the art see Liu teaches “Preferably, avalanche photoelectric detector of the integrated filter amplifying chip further comprises a temperature control circuit, the temperature control circuit comprises a temperature collecting ADC; processor and refrigerator; the temperature collecting ADC is connected with two ends of the thermistor; the refrigerator driving is connected with the refrigerator; one end of the processor is connected with the temperature collecting ADC; the other end is connected with the refrigerator driving; the temperature control circuit is set on the non-cooling area of the ceramic substrate; and it is also sealed in the shell. in the working process of the detector, adjusting the refrigerating power of the refrigerator according to the temperature change, making the APD work in a stable low temperature environment, and the reverse bias voltage and the gate control signal size are unchanged, so as to ensure low APD dark current noise; high sensitivity state, so the detector can keep stable detection efficiency” “Preferably, the avalanche photoelectric detector further comprises a thermistor; when the APD chip temperature changes, the resistance of the thermistor will change, and feedback to the processor through the temperature collecting ADC; the processor controls the refrigerator to drive according to the resistance value fed back by the temperature collecting ADC; The refrigerator drives and controls the refrigerating power of the refrigerator. namely adjusting different refrigerating power according to different temperature, the working temperature of the APD chip is constant”
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shi to include further comprising: a thermistor positioned to detect a temperature of the heating element, the thermistor to send temperature measurements to a controller and the controller to control the temperature of the heating element based on the temperature measurements.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that control circuit elements such as thermistor, processor are standard in the art and are known to provide good results for controlling temperature
Claim(s) 15-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shi et al. (US 20160155883 A1) hereafter referred to as Shi in view of Huang et al. (CN 109817753 A) hereafter referred to as Huang and further in view of Lebby et al. (US 6999644 B1) hereafter referred to as Lebby.
In regard to claim 15 Shi teaches a photodiode [“FIG. 1 shows a conventional 6-pin TO-header solution for Ge/Si APD. (a) TO-header mounted with Ge/Si APD chip and resistor heater and (b) Ge/Si APD chip”] module comprising:
a photodiode chip [see Fig. 1 see “Ge/Si APD chip”];
a heating element [see Fig. 1 see “Resistor heater” “a 30Ω resistor” “When a 3.3V bias voltage is applied on the resistor, the heat generated in the resistor can heat up the TO-header and increase TO temperature by about tens of degrees depending on consumption power”];
a submount [see Fig. 1 see “6-pin transistor outline (TO)-header”] to support the photodiode chip and the heating element; and
a cap [“TO-cap 522”] surrounding the photodiode chip, the heating element, and the submount,
but does not teach formed vertically below the photodiode chip and that the cap is a fiber pigtailed package enclosing the photodiode chip, the heating element, and the submount.
Huang teaches a photodiode module [“a 4-quadrant silicon-based PIN photoelectric detector, the structure shown in FIG. 2”] comprising:
a submount [see “the ceramic substrate 3 fixed on the base 4”];
a photodiode chip [“PIN photodiode 1”] on the submount; and
a heating element formed [“the PIN photodiode 1 adhered to the bottom heating element 2, the heating element 2 integrated to inside bearing PIN photodiode 3 of the ceramic substrate 1, as shown in Figure 3, the PIN photodiode 1 and heating the ceramic substrate 3 fixed on the base 4” “In order to reduce the size of the device, the heating element of heating of PIN photodiode integrated into the tray (e.g., ceramic substrate) inside bearing PIN photodiodes”] within or on the submount vertically below the photodiode chip,
see also “A method for improving the PIN photodiode responsivity, bottom heating element, the PIN photodiode bonded by heating is a PIN photodiode to improve the response degree, when heating the PIN photodiode to temperature fluctuation is kept at a fixed range (i.e., the PIN photodiode chip temperature rises to a certain range, the temperature fluctuation is maintained at a relatively small range) stopping heating, ensures the stability of PIN photodiode response” “using closed-loop or open-loop mode feedback and the PIN photodiode temperature control, product usage, the user can select according to the demand for open-loop or closed-loop control method realizing of PIN diode temperature constant”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shi to include a heating element in an insulator like Huang teaches ( see above ceramic is an example insulator), underneath the “Ge/Si APD chip” of Shi i.e. between the APD chip and the “6-pin transistor outline (TO)-header” i.e. to modify Shi to include formed vertically below the photodiode chip.
See in the combination of Shi and Huang, see that the ceramic substrate 3 of Huang i.e. the insulating substrate having the heater in the combination of Shi and Huang can itself be called the submount.
The motivation is better heating by applying the heater to the bottom of the Ge/Si APD chip.
Shi and Huang as combined does not specifically teach that the the cap is a fiber pigtailed package enclosing the photodiode chip, the heating element, and the submount.
See Shi teaches packages, see Fig. 1, Fig. 5 the “TO-header 521, a TO-cap 522” together form a package, “FIG. 5 shows a design of a 6-pin TO solution mounted with heater integrated Ge/Si APD in accordance with an embodiment of the present disclosure”, see paragraph 0003 “Avalanche photodiodes (APDs) are widely utilized for fiber-optic communications due to higher sensitivity”.
See the combination of Shi and Huang, see that the ceramic substrate 3 of Huang i.e. the insulating substrate having the heater in the combination of Shi and Huang can itself be called the submount.
See Huang base 4 has a plurality of layers.
See Lebby “Referring additionally to FIGS. 28 and 29, the optoelectric package, including optoelectric module 10 enclosed in housing 80, is illustrated in a discrete pigtail arrangement” “FIGS. 28 and 29 are two isometric views of the optoelectric package of FIG. 24 pigtailed with an optical fiber” see packaging examples “Turning now to FIGS. 18, 19, and 20, another housing 80 is illustrated for enclosing and mounting a discrete optoelectric module. Housing 80 has a substantially rectangular cross-section with a small opening 81 at one end and a larger opening or substantially hollow interior 82 accessible at the other end. A pair of mounting pins 84 extend from the lower surface for surface mounting the complete package. It will of course be understood that other shapes, both interior and exterior, may be devised for specific applications, and other or additional mounting pins or other mounting devices may be devised for specific mounting situations. (28) Turning to FIGS. 21, 22, and 23, an optoelectric module 10, with a multilayer hermetic ceramic package including a connection board (e.g., connection board 64) having outwardly extending leads 65 attached thereto, is provided. Module 10 may be, for example, similar to the optoelectric module described and illustrated in FIGS. 1 and 2. Optical fiber receiving opening 21 in receptacle 20 can best be seen in FIG. 23. (29) Referring additionally to FIGS. 24, 25, 26, and 27, module 10 of FIG. 21 is placed in housing 80 of FIG. 20 so that the end of receptacle 20 extends slightly through opening 81. Also, as can best be seen in FIG. 24 or 26, connection board 64 is positioned to seal opening 82 in housing 80. Alternatively, connection board 64 is sealed in opening 82 by some convenient means, such as epoxy or the like. In a preferred embodiment, module 10 is press fitted directly into housing 80. In some embodiments housing 80 may be lined with metal or completely formed of metal to provide EMI shielding”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shi to include that the the cap is a fiber pigtailed package enclosing the photodiode chip, the heating element, and the submount.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that packaging is useful to protect device with good output pin configuration and fiber pigtailed package is known to give good results to transfer light into photodiode.
In regard to claim 16 Shi Huang and Lebby as combined does not specifically teach wherein the heating element is smaller in length and width than the photodiode chip.
However see Huang teaches “In order to reduce the size of the device” see claim 5 “bottom of the PIN photodiode bonded heating element”, see that only the photodiode needs to be heated, thus the maximum size of the heater need not be larger than the photodiode, see Shi Fig. 4 the “heater 405” is shown smaller than the “Ge/Si avalanche photodiode 404”.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein the heating element is smaller in length and width than the photodiode chip”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 17 Shi Huang and Lebby as combined does not specifically teach further comprising:an electrical isolator positioned between the heating element and the photodiode chip.
However see Huang “the heating element of heating of PIN photodiode integrated into the tray (e.g., ceramic substrate) inside bearing PIN photodiodes” see that ceramic is an insulator.
See Shi “As shown in FIG. 3, Ge/Si avalanche photodiode 304 includes at least one integrated heater formed on a top portion of a Si substrate layer 301 underneath a buried oxide (BOX) layer 302 of a silicon-on-insulator (S01) substrate 310”, see claim 6 “wherein the Ge/Si avalanche photodiode further comprises one or more electrodes, wherein the at least one heater comprises one or more electrodes different than and separate from the one or more electrodes of the Ge/Si avalanche photodiode”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shi to include further comprising:an electrical isolator positioned between the heating element and the photodiode chip.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to obtain electrical isolation to operate the heater independently and the photodiode independently without affecting each other.
In regard to claim 18 Shi Huang and Lebby as combined does not specifically teach further comprising: a first heating element contact; and a second heating element contact, wherein the first heating element contact and the second heating element contact are in electrical contact with the heating element and are positioned on the submount.
However see Shi Fig. 2, Fig. 3 see the contacts on the heater 305 “electrically-conductive pads (e.g., aluminum pads) may be formed on top of the at least one heater 205 and Ge/Si avalanche photodiode 204, respectively, after a pad open process” “apply a proper bias voltage on the at least one heater 305, i.e., to activate or turn on the at least one heater 305”, see paragraph 0041 “performing a dielectric etch process to fabricate one or more contacts; performing a salicide process; performing a metal deposition process; and performing a metal etch process”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shi to include further comprising: a first heating element contact; and a second heating element contact, wherein the first heating element contact and the second heating element contact are in electrical contact with the heating element and are positioned on the submount.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is apply a proper bias voltage on the heater i.e., to activate it and turn it on.
In regard to claim 19 Shi Huang and Lebby as combined teaches [see combination, see Huang “the heating element of heating of PIN photodiode integrated into the tray (e.g., ceramic substrate) inside bearing PIN photodiodes”, See in the combination of Shi and Huang, see that the ceramic substrate 3 of Huang i.e. the insulating substrate having the heater in the combination of Shi and Huang can itself be called the submount] wherein the heating element is formed within a top surface of the submount.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shi Huang and Lebby as combined and further in view of Liu et al. (CN 112103276 A) hereafter referred to as Liu.
In regard to claim 20 Shi Huang and Lebby as combined does not teach further comprising:a thermistor positioned to detect a temperature of the heating element, the thermistor to send temperature measurements to a controller and the controller to control, by at least one hardware processor, the temperature of the heating element based on the temperature measurements.
However see Shi paragraph 0017 “When the environmental temperature decreases to a certain point, e.g., below a threshold temperature, a temperature control loop may be automatically triggered to apply a proper bias voltage on the at least one heater 205, i.e., to activate or turn on the at least one heater 205”.
However this is common in the art see Liu teaches “Preferably, avalanche photoelectric detector of the integrated filter amplifying chip further comprises a temperature control circuit, the temperature control circuit comprises a temperature collecting ADC; processor and refrigerator; the temperature collecting ADC is connected with two ends of the thermistor; the refrigerator driving is connected with the refrigerator; one end of the processor is connected with the temperature collecting ADC; the other end is connected with the refrigerator driving; the temperature control circuit is set on the non-cooling area of the ceramic substrate; and it is also sealed in the shell. in the working process of the detector, adjusting the refrigerating power of the refrigerator according to the temperature change, making the APD work in a stable low temperature environment, and the reverse bias voltage and the gate control signal size are unchanged, so as to ensure low APD dark current noise; high sensitivity state, so the detector can keep stable detection efficiency” “Preferably, the avalanche photoelectric detector further comprises a thermistor; when the APD chip temperature changes, the resistance of the thermistor will change, and feedback to the processor through the temperature collecting ADC; the processor controls the refrigerator to drive according to the resistance value fed back by the temperature collecting ADC; The refrigerator drives and controls the refrigerating power of the refrigerator. namely adjusting different refrigerating power according to different temperature, the working temperature of the APD chip is constant”
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shi to include further comprising:a thermistor positioned to detect a temperature of the heating element, the thermistor to send temperature measurements to a controller and the controller to control, by at least one hardware processor, the temperature of the heating element based on the temperature measurements.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that control circuit elements such as thermistor, processor are standard in the art and are known to provide good results for controlling temperature
Response to Arguments
Applicant's arguments filed 1/9/2026 have been fully considered but they are not persuasive.
Regarding the 112 rejection, the language of reduce a recovery time was removed from the claims, thus the 112 rejection has been removed.
On page 10-13 the Applicant argues that the new limitation of vertically below is not shown by Shi reference.
The Examiner responds that see the amended rejection uses a secondary reference to show this limitation as obvious in combination.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893