Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 9, 20, 21 objected to because of the following informalities:
Claim 9 first line needs to say “further including” . Appropriate correction is required.
Claim 20 appears to be identical to claim 19 except that claim 20 ends in the word “and” and also claim 20 does not end with a period “.” which is required. Appropriate correction is required.
Claim 21 recites STMDS without any definition, see Application PG-PUB paragraph 0008 “semimetal-TMDs-semimetal (STMDS) device”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 8-10, 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Konstantatos et al. (US 20160020352 A1) hereafter referred to as Konstantatos in view of Shen et al. (US 20210359099 A1) hereafter referred to as Shen
In regard to claim 1 Konstantatos teaches [see Fig. 2 see paragraph 0037 “Incident light 9” see paragraph 0042 “FIG. 6 shows the spectral responsivity of a MoS.sub.2-only 19 phototransistor that exhibits a responsivity up to 5 NW, being its spectral sensitivity determined by the bandgap of a 2-layer flake of around 1.8 eV” “While the MoS.sub.2 device absorbs only until a wavelength of −700 nm”] an optical detector comprising:
a first metal electrical [one of “A first electrode 6 (drain electrode) and a second electrode 7 (source electrode) are connected to the top 2DS layer 3 through the conductor layer 4” “conductor layer 4 can be implemented, for example, with Ti, Au, or any other conductor with similar functionalities”] contact portion, comprising a metal;
a second metal electrical [other of “A first electrode 6 (drain electrode) and a second electrode 7 (source electrode) are connected to the top 2DS layer 3 through the conductor layer 4”] contact portion comprising a metal; and
a transition metal dichalcogenide (TMD) layer [“Each 2DS layer 3 is a monolayer of MoS.sub.2 defined by three atomic layers (S—Mo—S)”], comprising a transition metal dichalcogenide, electrically coupled [“electrons 11 circulate through the MoS.sub.2 channel driven by an electric field V.sub.DS applied between the drain electrode 6 and the drain electrode 7”] between the first and second metal electrical contact portions
but does not teach that the first and second metal are semimetal.
See Shen teaches see title, see paragraph 0007, 0056, 0091 “a new phase of bismuth with a layer-like structure can be formed when the deposition of bismuth is implemented on the surface of 2D materials. The work function of such a new phase of bismuth can depend, at least in part, on the morphology of the underlying 2D material substrate, and can be different than that of other phases of bismuth deposited without the underlying 2D materials. In the case of molybdenum disulfide (MoS.sub.2), the work function of the new phase of bismuth decreases about 0.5 eV. As a result, a significantly high density of carriers can be induced in MoS.sub.2 at a metal/semiconductor contact interface by depositing bismuth (Bi) on semiconductor contact areas of such materials. Therefore, an energy-barrier free, degenerate interface for true ohmic contacts can be generated” “methods and devices provided for herein can be applied to a variety of industries, including but not limited to next-generation transistors, high-power electronics, high-frequency devices, memory devices, spintronics, and photonic devices for the semiconductor industry” “FIGS. 2A-2D illustrate the ohmic contact transistor performance enabled by the use of bismuth at the contact area(s) of the transistor 100 of FIG. 1” “the images of FIGS. 2A and 2B allow for a comparison of the transfer and output characteristics of monolayer MoS.sub.2 transistors that use conventional contact techniques such as titanium contacts and those that use bismuth contacts at different temperatures” “an approximately 20-nm of bismuth thin film can be deposited on a continuous monolayer MoS.sub.2 film grown on an SiO.sub.2/Si wafer. An Au capping layer can also be provided, which can be used for e-beam evaporation. A resulting heterostructure of Au—Bi—MoS.sub.2”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Konstantatos to include that the first and second metal are semimetal.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that Bismuth contacts provide better electrical performance.
In regard to claim 2 Konstantatos and Shen as combined teaches wherein the TMD layer includes [see Fig. 2 see portions under 4 and in between] a first portion, a second portion, and a third portion, wherein the third portion of the TDM layer is located between [see Fig. 2 see portion in between 4] the first and second portions of the TDM layer;
wherein the first semimetal electrical contact portion is formed upon the first portion [either portion under 4] of the TDM layer;
wherein the second semimetal electrical contact portion is formed upon the second portion [the other portion under 4] of the TDM layer;
further including: an optical channel [see Fig. 2 see portion in between 4], to allow passage of photons [“Incident light 9”] to the third portion of the TDM layer, that extends between the first and second semimetal electrical contact portions and that terminates [see Fig. 2 ] at the third portion of the TDM layer.
In regard to claim 3 Konstantatos and Shen as combined teaches further including: a conductor layer [see the doped part of substrate 1, “apparatus comprises a substrate 1 fabricated of a heavily doped semiconductor such as Silicon, on top of which is deposited a dielectric layer 2 of silicon oxide. The transport layer of the apparatus is implemented by two 2-dimensional semiconductor (2DS) layers 3”]; and
an insulator layer [“dielectric layer 2 of silicon oxide”] overlaying the conductor layer; wherein the TMD layer is formed upon [see Fig. 2 ] the insulator layer.
In regard to claim 8 Konstantatos and Shen as combined teaches further including: a first metal electrical contact portion [see combination, see Shen “Au capping layer” on Bi , see Konstantatos has electrical connections 6 and 7] that overlays at least a portion of the first semimetal electrical contact portion; and a second metal electrical contact portion [see combination, see Shen “Au capping layer” on Bi , see Konstantatos has electrical connections 6 and 7] that overlays at least a portion of the second semimetal electrical contact portion.
In regard to claim 9 Konstantatos and Shen as combined teaches a conductor layer [see the doped part of substrate 1, “apparatus comprises a substrate 1 fabricated of a heavily doped semiconductor such as Silicon, on top of which is deposited a dielectric layer 2 of silicon oxide. The transport layer of the apparatus is implemented by two 2-dimensional semiconductor (2DS) layers 3”]; and
an insulator layer [“dielectric layer 2 of silicon oxide”] overlaying the conductor layer;
wherein the first electrical [see combination, see Shen “Au capping layer” on Bi , see Konstantatos has electrical connections 6 and 7] contact portion overlays a portion of the insulator layer; and
wherein the second electrical [see combination, see Shen “Au capping layer” on Bi , see Konstantatos has electrical connections 6 and 7] contact portion overlays a portion of the insulator layer;
wherein the TMD layer is formed upon [see Konstantatos Fig. 2 ] the insulator layer;
further including:
a first wetting layer [this is the Au layer, see combination, see Shen “Au capping layer” on Bi , see Konstantatos has electrical connections 6 and 7] extending between the first metal electrical contact portion and the first semimetal electrical contact portion and extending between the first metal electrical contact portion and the insulator layer; and
a second wetting layer [this is the Au layer, see combination, see Shen “Au capping layer” on Bi , see Konstantatos has electrical connections 6 and 7] extending between the second metal electrical contact portion and the second semimetal electrical contact portion and extending between the second metal electrical contact portion and the insulator layer,
however Konstantatos does not mention that 6 and 7 are metal i.e. that first and second electrical are metal, however see that Au is metal, see Konstantatos says “conductor layer 4 can be implemented, for example, with Ti, Au, or any other conductor with similar functionalities”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Konstantatos to include that first and second electrical are metal.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that metal is known to be a good conductor for interconnection.
In regard to claim 10 Konstantatos and Shen as combined teaches further including: a conductor layer [see the doped part of substrate 1, “apparatus comprises a substrate 1 fabricated of a heavily doped semiconductor such as Silicon, on top of which is deposited a dielectric layer 2 of silicon oxide. The transport layer of the apparatus is implemented by two 2-dimensional semiconductor (2DS) layers 3”]; and an insulator layer [“dielectric layer 2 of silicon oxide”] located between the TMD layer and the conductor layer.
In regard to claim 14 Konstantatos and Shen as combined teaches wherein the first semimetal electrical contact portion and the second semimetal electrical contact portion include Bismuth [see combination Shen, Bismuth]; and wherein the TMD layer [“Each 2DS layer 3 is a monolayer of MoS.sub.2 defined by three atomic layers (S—Mo—S)”] includes MoS2.
In regard to claim 15 Konstantatos and Shen as combined teaches wherein each occurrence of the semimetal independently comprises As, In, Sn, Sb, Te, TI, Pb, Po, At, Bi [see combination Shen, Bismuth], or a mixture thereof; and wherein the transition metal dichalcogenide comprises WS2, MoSe2, WSe2, MoTe2, WTe2, MoS2 [“Each 2DS layer 3 is a monolayer of MoS.sub.2 defined by three atomic layers (S—Mo—S)”], or a mixture thereof.
In regard to claim 16 Konstantatos and Shen as combined teaches wherein the TMD layer is photoreceptive in an optical wavelength [see paragraph 0042 “FIG. 6 shows the spectral responsivity of a MoS.sub.2-only 19 phototransistor that exhibits a responsivity up to 5 NW, being its spectral sensitivity determined by the bandgap of a 2-layer flake of around 1.8 eV” “While the MoS.sub.2 device absorbs only until a wavelength of −700 nm”] range of about 250 to 1,000 nm.
Claim(s) 4-7, 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Konstantatos and Shen as combined and further in view of Beechem, III et al. (US 20160172527 A1) hereafter referred to as Beechem
In regard to claim 4 Konstantatos and Shen as combined teaches wherein the insulator layer [“dielectric layer 2 of silicon oxide”] includes a silicon dioxide layer but does not state further including:an undoped silicon layer located between the conductor layer and the insulator layer; wherein the silicon dioxide layer is formed upon the undoped silicon layer.
See Konstantatos teaches “Additional substrate layers 1 can be included to provide support to the whole apparatus, such as silicon substrates” “apparatus comprises a substrate 1 fabricated of a heavily doped semiconductor such as Silicon, on top of which is deposited a dielectric layer 2 of silicon oxide” see Konstantatos says “conductor layer 4 can be implemented, for example, with Ti, Au, or any other conductor with similar functionalities”.
See Beechem teaches implanting a back gate, see paragraph 0025 “a semi-insulating silicon carbide (SiC) substrate 21 can be implanted with conductive ions to form a conductive back gate 22 and via 23 for later connection to a backside metal contact 24”.
See that in the current combination, the via is not being combined, thus the back gate of Konstantatos can be formed by implanting the back of an undoped silicon substrate and making a metal substrate contact on it, leaving the upper portion of silicon undoped.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Konstantatos to include further including:an undoped silicon layer located between the conductor layer and the insulator layer; wherein the silicon dioxide layer is formed upon the undoped silicon layer.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is ease of manufacture and good electrical isolation by implanting a gate area of an undoped silicon substrate to obtain a back gate where desired.
In regard to claim 5 Konstantatos, Shen and Beechem as combined does not specifically teach wherein the undoped silicon layer has a thickness in a range of about 10 nanometers to 100 nanometers.
However see Konstantatos “Substrate layer 1: 0.1 nm-10 mm”.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein the undoped silicon layer has a thickness in a range of about 10 nanometers to 100 nanometers ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 6 Konstantatos, Shen and Beechem as combined teaches wherein the conductor layer includes [see combination Beechem, see Konstantatos “apparatus comprises a substrate 1 fabricated of a heavily doped semiconductor such as Silicon, on top of which is deposited a dielectric layer 2 of silicon oxide”] a doped silicon layer.
In regard to claim 7 Konstantatos, Shen and Beechem as combined [see combination Beechem the back gate of Konstantatos can be formed by implanting the back of an undoped silicon substrate and making a metal substrate contact on it, leaving the upper portion of silicon undoped] teaches wherein the conductor layer includes a metal layer.
In regard to claim 11 Konstantatos and Shen as combined does not state further including: an undoped semiconductor layer located between the conductor layer and the insulator layer.
See Konstantatos teaches “Additional substrate layers 1 can be included to provide support to the whole apparatus, such as silicon substrates” “apparatus comprises a substrate 1 fabricated of a heavily doped semiconductor such as Silicon, on top of which is deposited a dielectric layer 2 of silicon oxide” see Konstantatos says “conductor layer 4 can be implemented, for example, with Ti, Au, or any other conductor with similar functionalities”.
See Beechem teaches implanting a back gate, see paragraph 0025 “a semi-insulating silicon carbide (SiC) substrate 21 can be implanted with conductive ions to form a conductive back gate 22 and via 23 for later connection to a backside metal contact 24”.
See that in the current combination, the via is not being combined, thus the back gate of Konstantatos can be formed by implanting the back of an undoped silicon substrate and making a metal substrate contact on it, leaving the upper portion of silicon undoped.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Konstantatos to include further including: an undoped semiconductor layer located between the conductor layer and the insulator layer.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is ease of manufacture and good electrical isolation by implanting a gate area of an undoped silicon substrate to obtain a back gate where desired.
In regard to claim 12 Konstantatos, Shen and Beechem as combined teaches wherein the conductor layer comprises [see combination Beechem the back gate of Konstantatos can be formed by implanting the back of an undoped silicon substrate and making a metal substrate contact on it, leaving the upper portion of silicon undoped] a doped silicon layer; and wherein the insulator layer [“dielectric layer 2 of silicon oxide”] comprises a silicon dioxide layer; further including: an undoped semiconductor layer [see combination Beechem the back gate of Konstantatos can be formed by implanting the back of an undoped silicon substrate and making a metal substrate contact on it, leaving the upper portion of silicon undoped] located between the conductor layer and the insulator layer.
In regard to claim 13 Konstantatos, Shen and Beechem as combined does not specifically teach wherein the undoped silicon layer has a thickness in a range of about 10 nanometers to 100 nanometers.
However see Konstantatos “Substrate layer 1: 0.1 nm-10 mm”.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein the undoped silicon layer has a thickness in a range of about 10 nanometers to 100 nanometers”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
Claim(s) 17-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Konstantatos et al. (US 20160020352 A1) hereafter referred to as Konstantatos in view of Shen et al. (US 20210359099 A1) hereafter referred to as Shen
In regard to claim 17 Konstantatos teaches [see Fig. 2 see paragraph 0042 “a MoS.sub.2-only 19 phototransistor”] an optical detection method comprising:
receiving optical photon energy at a TMD monolayer [see paragraph 0037 “Incident light 9” “While the MoS.sub.2 device absorbs only until a wavelength of −700 nm”] electrically coupled [“A first electrode 6 (drain electrode) and a second electrode 7 (source electrode) are connected to the top 2DS layer 3 through the conductor layer 4” “conductor layer 4 can be implemented, for example, with Ti, Au, or any other conductor with similar functionalities”] between first and second metal electrical contacts; and
measuring electrical current flow [“electrons 11 circulate through the MoS.sub.2 channel driven by an electric field V.sub.DS applied between the drain electrode 6 and the drain electrode 7”] between the first and second metal electrical contacts, comprising electrons excited by [see paragraph 0042 “FIG. 6 shows the spectral responsivity of a MoS.sub.2-only 19 phototransistor that exhibits a responsivity up to 5 NW, being its spectral sensitivity determined by the bandgap of a 2-layer flake of around 1.8 eV”] optical photon energy received at the TMD layer,
but does not teach that the first and second metal are semimetal.
See Shen teaches see title, see paragraph 0007, 0056, 0091 “a new phase of bismuth with a layer-like structure can be formed when the deposition of bismuth is implemented on the surface of 2D materials. The work function of such a new phase of bismuth can depend, at least in part, on the morphology of the underlying 2D material substrate, and can be different than that of other phases of bismuth deposited without the underlying 2D materials. In the case of molybdenum disulfide (MoS.sub.2), the work function of the new phase of bismuth decreases about 0.5 eV. As a result, a significantly high density of carriers can be induced in MoS.sub.2 at a metal/semiconductor contact interface by depositing bismuth (Bi) on semiconductor contact areas of such materials. Therefore, an energy-barrier free, degenerate interface for true ohmic contacts can be generated” “methods and devices provided for herein can be applied to a variety of industries, including but not limited to next-generation transistors, high-power electronics, high-frequency devices, memory devices, spintronics, and photonic devices for the semiconductor industry” “FIGS. 2A-2D illustrate the ohmic contact transistor performance enabled by the use of bismuth at the contact area(s) of the transistor 100 of FIG. 1” “the images of FIGS. 2A and 2B allow for a comparison of the transfer and output characteristics of monolayer MoS.sub.2 transistors that use conventional contact techniques such as titanium contacts and those that use bismuth contacts at different temperatures” “an approximately 20-nm of bismuth thin film can be deposited on a continuous monolayer MoS.sub.2 film grown on an SiO.sub.2/Si wafer. An Au capping layer can also be provided, which can be used for e-beam evaporation. A resulting heterostructure of Au—Bi—MoS.sub.2”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Konstantatos to include that the first and second metal are semimetal.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that Bismuth contacts provide better electrical performance.
In regard to claim 18 Konstantatos and Shen as combined teaches further including: applying a bias voltage [see Konstantatos Fig. 2 “electrons 11 circulate through the MoS.sub.2 channel driven by an electric field V.sub.DS applied between the drain electrode 6 and the drain electrode 7”] across the first and second semimetal electrical contacts.
In regard to claim 19 Konstantatos and Shen as combined teaches further including: applying a voltage to a back gate [see Konstantatos Fig. 2 “current flow can be controlled electrically by applying an appropriate back-gate voltage (V.sub.G) at the back-gate electrode 8”] that is electrically coupled between the first and second semimetal electrical contacts.
In regard to claim 20 [see claim objection] Konstantatos and Shen as combined teaches further including: applying a voltage to a back gate [see Konstantatos Fig. 2 “current flow can be controlled electrically by applying an appropriate back-gate voltage (V.sub.G) at the back-gate electrode 8”] that is electrically coupled between the first and second semimetal electrical contacts; and
In regard to claim 21 Konstantatos and Shen as combined teaches wherein the STMDS layer is located upon an insulator [see Konstantatos Fig. 2 “dielectric layer 2 of silicon oxide”] layer; further including: preventing current flow between the back gate [it is dielectric, the gate is field-effect] and the insulator layer.
Conclusion
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893