Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1,3, 9 and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhou (20190139973) hereinafter, Zhou.
In regards to claim 1, Zhou teaches a memory device, comprising (abstract):
an alternating stack of insulating layers and electrically conductive layers (fig. 2 42 and 32) [0042-0044])
A memory opening is formed through an alternating stack of insulating layers and sacrificial material layers located over a substrate. Annular recesses are formed around the memory opening by laterally recessing the sacrificial material layers with respect to the insulating layers. Annular metal portions are formed over recessed sidewalls of the sacrificial material layers within each of the annular recesses by a selective deposition process. Annular backside blocking dielectrics are formed selectively on inner sidewalls of the annular metal portions employing a layer of a self-assembly material that covers surfaces of the insulating layers and inhibits deposition of a dielectric material thereupon. A memory stack structure is formed in the memory opening, and the sacrificial material layers are replaced with electrically conductive layers. The annular backside blocking dielectrics provide electrical isolation for the annular metal portions, which function as control gate electrodes.(Abstract)
PNG
media_image1.png
616
782
media_image1.png
Greyscale
a memory opening vertically extending through the alternating stack (fig. 4a (49))
PNG
media_image2.png
616
818
media_image2.png
Greyscale
a memory opening fill structure (fig. 6 (11, 55, 62, and 63 [0096]) located in the memory opening and comprising a memory film (fig. 6 (50)) and a vertical semiconductor channel (fig, 9b (60) [0094]and
a neighboring electrically conductive layer(fig. 5c top 42s)) (“[0044] The sacrificial material layers 42 may comprise an insulating material, a semiconductor material, or a conductive material.”) interference reduction feature provided for a first subset of the electrically conductive layers (fig. 5c gap between 32s) see annotated drawing below)
PNG
media_image3.png
578
672
media_image3.png
Greyscale
wherein a second subset of the electrically conductive layers (fig. 5c alternating (42s at the bottom)) lacks the neighboring electrically conductive layer interference reduction feature.(fig. 5c no gaps in 32)see annotated drawing below)
PNG
media_image4.png
620
624
media_image4.png
Greyscale
In regards to claim 3, Zhou teaches the memory device of claim 1, wherein: the neighboring electrically conductive layer interference reduction feature comprises a lateral outward protrusion of the memory opening fill structure at each level of the electrically conductive layers of the first subset; (fig. 10c and fig. 12D memory film (50) has lateral outward protrusions); and the memory opening fill structure lacks the lateral outward protrusion at each level of the electrically conductive layers of the second subset. (fig. 12d 62 lacks (50)).
In regards to claim 9, Zhou teaches memory device of claim 1, wherein: the neighboring electrically conductive layer interference reduction feature comprises a lateral outward protrusion of the memory opening fill structure located at each level of the insulating layers which are located between the electrically conductive layers of the first subset (fig. 10c and fig. 12D memory film (50) has lateral outward protrusions);
and the memory opening fill structure lacks the lateral outward protrusion at each level of the insulating layers located between the electrically conductive layers of the second subset (fig. 12d 62 lacks (50)).
In regards to claim 10, Zhou teaches memory device of claim 9, wherein: the memory film comprises a continuous charge storage material layer (fig. 10c and 12d (54) [0082] that continuously extends through each of the electrically conductive layers of the alternating stack (fig. 12d (54) [0082]; and the continuous charge storage material layer laterally extends outwards into the lateral outward protrusion (fig. 12d (54) [0082]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou in view of Shigemura et al (2018/0138194) hereinafter, Shigermura.
In regards to claim 2, Zhou teaches the memory device of claim 1, wherein: the electrically conductive layers of the first subset are located above the electrically conductive layers of the second subset (fig. 5c 42s located at top are first subset and lower 42s are second subset);
Zhou fails to teach the electrically conductive layers of the first subset are thinner than the electrically conductive layers of the second subset. Examiner notes [0040,0044,0047].
However, Shigermura teaches of a first subset are thinner than the electrically conductive layers of the second subset.(fig. 57a (42B(42)) is thicker than 42W42)
It would have been obvious to one of ordinary skill in the art to modify the teachings of Zhou to further include a first subset are thinner than the electrically conductive layers of the second subset as taught by Shigermura in order to decrease resistivity [004-005]
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou in view of Alsmeier et al (2012/0001252) hereinafter, Alsmeier.
In regards to claim 4, Zhou fails to teach the memory device of claim 3, wherein the memory film comprises a plurality of discrete charge storage material layers that are vertically spaced apart.
However, Alsmeier teaches wherein the memory film comprises a plurality of discrete charge storage material layers that are vertically spaced apart. (fig. 3 (9a, 9b, and 9c [104, 112-113).
It would have been obvious to one of ordinary skill in the art to modify the teachings of Zhou to further include wherein the memory film comprises a plurality of discrete charge storage material layers that are vertically spaced apart as suggested by Alsmeier in order to reduce parasitic coupling [126].
Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou in view of Kim et al (2017/0062330) hereinafter, Kim
In regards to claim 11, Zhou fails to teach the memory device of claim 1, wherein the neighboring electrically conductive layer interference reduction feature comprises each of the insulating layers located between a respective vertically neighboring pair of the electrically conductive layers of the first subset which have a lower dielectric constant than each of the insulating layers located between a respective vertically neighboring pair of the electrically conductive layers of the second subset.
However, Kim teaches low dielectric constant insulating material in 3d memory abstract, (fig. 5d (DIL1 and DIL2))Kim
It would have been obvious to one of ordinary skill in the art to modify the first subset of Zhou to further include teach wherein the neighboring electrically conductive layer interference reduction feature comprises each of the insulating layers located between a respective vertically neighboring pair of the electrically conductive layers of the first subset which have a lower dielectric constant than each of the insulating layers located between a respective vertically neighboring pair of the electrically conductive layers of the second subset as taught by Lee in order to decrease the height of the stacks without degrading performance and help to reduce parasitic capacitance between vertically stacked electrodes [0082].
Therefore, Zhou in view of Kim teaches wherein the neighboring electrically conductive layer interference reduction feature comprises each of the insulating layers located between a respective vertically neighboring pair of the electrically conductive layers of the first subset which have a lower dielectric constant than each of the insulating layers located (fig. 5d (DIL1 and DIL2))Kim between a respective vertically neighboring pair of the electrically conductive layers of the second subset. (fig. 10c and fig. 12D memory film (50) has lateral outward protrusions)Zhou
In regards to claim 12, Zhou in view of Kim teaches the memory device of claim 11, wherein: each of the insulating layers located between a respective vertically neighboring pair of the electrically conductive layers of the first subset comprises silicon oxide having a first porosity [00200] Kim; and each of the insulating layers located between a respective vertically neighboring pair of the electrically conductive layers of the second subset comprises silicon oxide having a second porosity lower than the first porosity (fig. 6a and 6b ILD1 and ILD2)) Kim.
Allowable Subject Matter
Claims 5-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRANT SITTA whose telephone number is (571)270-1542. The examiner can normally be reached M-F 7:30-4:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at 571-272-6084. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GRANT SITTA/Primary Examiner, Art Unit 2622