DETAILED ACTION
Response to Amendment
Amendment filed on 09 July 2026 has been entered. Claims 1-3 and 5-20 are now pending in the application.
Response to Arguments
Applicant’s arguments, see Pages 6-8, filed 09 July2026, with respect to the rejection(s) of claim(s) 1-3, 5, 7, 9 and 11-19 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yamamoto (US 20140319982).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 7 and 9-20 are rejected under 35 U.S.C. 103 as being unpatentable over Strong (US 20210287979) in view of Yamamoto (US 20140319982).
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Annotated Fig. 7, Strong.
Regarding claim 1, Strong teaches, a method of manufacturing an electronic device (microelectronic package, see Abstract), comprising:
providing a first dielectric layer (dielectric material 705, see annotated Fig. 7 above, para. [0053]) and a second dielectric layer (substrate 707, Fig. 7, substrate 107 may include one or more layers of a dielectric material, para. [0032]), wherein the first dielectric layer has a first surface and a second surface opposite to each other, and the second dielectric layer has a third surface and a fourth surface opposite to each other (see Fig. 7);
forming a first unit (cavities 725, or dielectric features 750 Fig. 7) on the first surface or the second surface of the first dielectric layer; and
combining the first dielectric layer and the second dielectric layer to form a substrate structure, wherein the second surface of the first dielectric layer faces the third surface of the second dielectric layer (see, stack 700, Fig. 7, para. [0053]),
wherein the step of forming the first unit on the first dielectric layer comprises forming a recess (cavities 725, Fig. 7) on the first surface or the second surface of the first dielectric layer, and a method of forming the recess comprises chemical etching (a cavity 725 may be formed through…performing the etching, para. [0053]), laser drilling, or mechanical frilling, wherein the first unit has a bottom surface, a side surface (see cavityies725), wherein first unit has a bottom surface, a side surface (see cavities 725).
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Annotated Figs. 1 and 2, Yamamoto.
Though, Strong teaches a concave dielectric feature 550b in Fig. 5, Strong does not explicitly teach, the arc corner is disposed at a connection between the bottom surface and the side surface. However, Yamamoto teaches, a method of manufacturing an electronic device, including a first dielectric layer (ceramic material S, see annotated Fig. 2), forming a first unit (cavity 6, Figs 1 and 2) on the first surface or the second surface of the first dielectric layer, wherein the first unit has a bottom surface, a side surface and an are corner (see annotated Figs. 1 and 2), the bottom surface is connected to the side surface, and the arc corner is disposed at a connection between the bottom surface and the side surface (the cavity 6 is defined by a bottom surface 7 having a rectangular shape in plan view and having four arcuate corners; four side walls 8 having four arcuate corner surfaces, para. [0055]).
Strong teaches in Fig. 5, para. [0051], forming a first unit 550b, on the first surface of the first dielectric layer 505 having a concave shape and dielectric feature 550a may be a convex protrusion of the dielectric material 505 into a cavity 525. Yamamoto teaches, cavity 6 having bottom surface is connected to the side surface, and the arc corner is disposed at a connection between the bottom surface and the side surface. Therefore, in view of the teachings of Yamamoto, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing of an electronic device of Strong and to include arcuate corner as Yamamoto disclosed in Figs. 1 and 2 so that it enables reducing the thermal stress as Yamamoto disclosed in para. [0004]. Forming an arc corner cavities to mitigate the stress and/ cracks is known in the art. If applicant disagrees, see Jia X., et al., Antenna-Integrated, Die-Embedded Glass Package for 6G Wireless Applications, IEEE 2022. Moreover, there is no indication in the instant invention that any surprising results were derived, or that any special steps were devised in forming the first unit having an arc corner between the bottom surface and the side surface. Such a combination would have been done by one of ordinary skill in the art without any need for experimentation and with reasonable expectations of success.
Regarding claim 2, Strong in view of Yamamoto teaches the recited limitations with respect to claim 1. Strong further teaches, the method of manufacturing according to claim 1, wherein a dielectric loss of the first unit is less than a dielectric loss of the first dielectric layer (cavities 725 may be filled with a low-k dielectric 720, para. [0053], a relatively low dielectric constant k, also referred to as low-k…dielectric material may be air…the dielectric constant k of air may be between approximately 1.0001 and approximately 1.001 para. [0024-0025]).
Regarding claim 3, Strong in view of Yamamoto teaches the recited limitations with respect to claim 2. Strong further teaches, the method of manufacturing according to claim 2, wherein a dielectric loss of the first unit is less than 0.01 (cavities 725 may be filled with a low-k dielectric 720, para. [0053], the dielectric material may be air, which may have a dielectric constant k of approximately 1. More generally, the dielectric constant k of air may be between approximately 1.0001 and approximately 1.00, para. [0025], claim fails to define a dielectric loss of the first unit. Therefore, Strong meets the claimed range, less than 0.01).
Regarding claim 5, Strong in view of Yamamoto teaches the recited limitations with respect to claim 1. Strong further teaches, the method of manufacturing according to claim 1, wherein the step of combining the first dielectric layer and the second dielectric layer comprises: pressing the first dielectric layer and the second dielectric layer together, so that the first dielectric layer contacts the second dielectric layer (see the stack 700, although the dielectric material 105 is depicted as a unitary piece of material, in some embodiments the dielectric material 105 may include two or more different types of dielectric layer, para. [0031]).
Regarding claim 7, Strong in view of Yamamoto teaches the recited limitations with respect to claim 1. Strong further teaches, the method of manufacturing according to claim 1, further comprising: forming a second unit (see annotated Fig. 7 above) on the third surface or the fourth surface of the second dielectric layer, so that the second unit overlaps with the first unit (see Fig. 7).
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Annotated Fig. 7, Strong.
Regarding claim 9, Strong in view of Yamamoto teaches the recited limitations with respect to claim 7. Strong further teaches, the method of manufacturing according to claim 7, wherein the second unit is disposed between the second surface of the first dielectric layer and the third surface of the second dielectric layer (see Fig. 7 above).
Regarding claim 10, modified Strong does not teach the second unit is disposed on the fourth surface of the second dielectric layer. However, Dutta further teaches, the method of manufacturing according to claim 7, wherein the second unit is disposed on the fourth surface of the second dielectric layer (see Fig. 7 below).
Regarding claim 11, Strong in view of Yamamoto teaches the recited limitations with respect to claim 1. Strong further teaches, the method of manufacturing according to claim 1, further comprising: disposing a first metal layer (see annotated Fig. 7 below, also see, signal line 310, Fig. 3) on the first surface of the first dielectric layer in the substrate structure; and disposing a second metal layer (see annotated Fig. 7 above) on the fourth surface of the second dielectric layer in the substrate structure.
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Annotated Fig. 7, Strong.
Regarding claim 12, Strong in view of Yamamoto teaches the recited limitations with respect to claim 11. Strong further teaches, the method of manufacturing according to claim 11, further comprising: disposing a third metal layer (see annotated Fig. 7 below) on the third surface of the second dielectric layer, so that the third metal layer is embedded in the second dielectric layer, wherein the third metal layer has an upper surface, a lower surface, and a side surface, and the upper surface is exposed outside the second dielectric layer (see annotated Fig. 7 below).
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Annotated Fig. 7, Strong.
Regarding claim 13, Strong in view of Yamamoto teaches the recited limitations with respect to claim 12. Strong further teaches, the method of manufacturing according to claim 12, wherein the third metal layer overlaps with the first unit (see the first unit 725 in Fig. 7).
Regarding claim 14, Strong in view of Yamamoto teaches the recited limitations with respect to claim 12. Strong further teaches, the method of manufacturing according to claim 12, further comprising: forming another recess (see annotated Fig. 7 above) on the third surface of the second dielectric layer, so that the another recess exposes the side surface of the third metal layer (see another recess and the third metal layer, Fig. 7); and forming a dielectric material layer in the another recess, wherein a dielectric loss of the dielectric material layer is less than the dielectric loss of the first dielectric layer (cavities 725 may be filled with a low-k dielectric 720, para. [0053]).
Regarding claim 15, Strong in view of Yamamoto teaches the recited limitations with respect to claim 14. Strong further teaches, the method of manufacturing according to claim 14, wherein the dielectric loss of the dielectric material layer is less than 0.01 (cavities 725 may be filled with a low-k dielectric 720, para. [0053], the dielectric material may be air, which may have a dielectric constant k of approximately 1…the dielectric constant k of air may be between approximately 1.0001 and approximately 1.00, para. [0025], claim fails to define a dielectric loss of the first unit. Therefore, Strong meets the claimed range, less than 0.01).
Regarding claim 16, Strong in view of Yamamoto teaches the recited limitations with respect to claim 1. Strong further teaches, the method of manufacturing according to claim 1, wherein the first unit is a gas cavity (dielectric material may be an inert gas, para. [0026]) or a vacuum cavity (dielectric material may be air, which may have a dielectric constant k of approximately 1, para. [0025]).
Regarding claim 17, Strong in view of Yamamoto teaches the recited limitations with respect to claim 1. Strong further teaches, the method of manufacturing according to claim 1, wherein a material of the first unit is gas, liquid, or solid (dielectric material may be an inert gas, para. [0026], cavities 725 may be filled with a low-k dielectric 720, para. [0053]).
Regarding claim 18, Strong in view of Yamamoto teaches the recited limitations with respect to claim 1. Strong further teaches, the method of manufacturing according to claim 1, wherein the first unit is disposed between the first dielectric layer and the second dielectric layer (see the cavity 725, Fig. 7).
Regarding claim 19, Strong in view of Yamamoto teaches the recited limitations with respect to claim 1. Strong further teaches, the method of manufacturing according to claim 1, wherein the first unit is disposed on the first surface of the first dielectric layer (see the cavity 725, Fig. 7).
Regarding claim 20, Strong in view of Yamamoto teaches the recited limitations with respect to claim 1. Strong further teaches, the method of manufacturing according to claim 1, wherein the first unit is disposed on the second surface of the first dielectric layer, and the method of manufacturing further comprises: forming a third unit (see annotated Fig. 8 below) on the first surface of the first dielectric layer, so that the third unit overlaps with the first unit (see the cavity 620, Fig. 6).
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Annotated Fig. 8, Strong.
Claim(s) 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Strong in view of Yamamoto as applied to claim 1 above, and further in view of Dutta (US 20070066126).
Regarding claim 6, Strong does not teach, disposing an adhesive on the second surface of the first dielectric layer. However, Dutta teaches, a method of manufacturing an electronic device (high speed FLEX-PCB 20, Fig. 4), comprising: providing a first dielectric layer (core layer 12, see annotated Fig. 4 below), and a second dielectric layer (core layer 12, Fig. 4); forming a first unit (trench 22) on the first surface or the second surface of the first dielectric layer; and combining the first dielectric layer and the second dielectric layer to form a substrate structure (high speed FLEX-PCB 20, Fig. 4), wherein the step of forming the first unit on the first dielectric layer comprises forming a recess on the first surface or the second surface of the first dielectric layer, and a method of forming the recess comprises chemical etching (trench can also be opened using the wet or dry-etching after using standard photolithography, para. [0071]), laser drilling (trench 22 can be opened inside the sheet material 26 by using the laser drilling or mechanical drilling, para. [0069]), or mechanical frilling, in which,
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Annotated Fig. 4, Datta.
the method of combining the first dielectric layer and the second dielectric layer comprises: disposing an adhesive (adhesive 14, Fig. 4) on the second surface of the first dielectric layer; and connecting the first dielectric layer and the second dielectric layer by using the adhesive (see Fig. 4). Therefore, in view of the teachings of Dutta, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing of an electronic device of Strong and to include an adhesive 14 as Dutta taught in Fig. 4 so that it enables joining the dielectric layers with a material having lower tangent loss.
Regarding claim 8, modified Strong does not teach the recited limitations. However, Dutta further teaches, wherein a width of an overlapping portion of the first unit and the second unit is greater than or equal to 1/3 times a width of the first unit and less than or equal to the width of the first unit (see annotated Fig. 4 below, unless otherwise defined, selecting a desired width is of design choice).
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Annotated Fig. 4, Datta.
Therefore, in view of the teachings of Dutta, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing of an electronic device of Strong and to include an overlapping portion as Dutta taught in Fig. 4 so that it enables joining the dielectric layers having higher bandwidth and lower signal loss.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE K. ABRAHAM whose telephone number is (571)270-1087. The examiner can normally be reached Monday-Friday 8:30-4:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, THOMAS J. HONG can be reached at (571) 272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSE K ABRAHAM/Examiner, Art Unit 3729
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