Prosecution Insights
Last updated: April 19, 2026
Application No. 18/356,221

ADAPTIVE BURST MODE CONTROL

Non-Final OA §102§103
Filed
Jul 21, 2023
Examiner
COMAS TORRES, YAHVEH
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
93%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
64 granted / 74 resolved
+18.5% vs TC avg
Moderate +7% lift
Without
With
+6.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
14 currently pending
Career history
88
Total Applications
across all art units

Statute-Specific Performance

§101
2.1%
-37.9% vs TC avg
§103
52.0%
+12.0% vs TC avg
§102
31.7%
-8.3% vs TC avg
§112
14.3%
-25.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 74 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement filed 10/17/2023 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed (for example applicant fail to provide a copy for the non-patent literature). It has been placed in the application file, but the information referred to therein has not been considered. Election/Restrictions Applicant’s election without traverse of Group II in the reply filed on 11/24/2025 is acknowledged. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 15-17 and 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fahlenkamp US Patent 9768697 (Fahlenkamp) . PNG media_image1.png 524 782 media_image1.png Greyscale [AltContent: arrow][AltContent: textbox (Transitioned to Normal load conditions)][AltContent: oval][AltContent: connector][AltContent: textbox (Suppressing Sleep Period)][AltContent: arrow] PNG media_image2.png 573 424 media_image2.png Greyscale Regarding claim 1, Fahlenkamp discloses a method of operating a pulse width modulation- controlled (PWM-controlled) system, comprising: controlling a switch transistor (i.e., 118) (Fig. 1) using a PWM control signal generated by a PWM control circuit (i.e., 101) (Fig. 1) operating in a burst mode (see fig. 3) corresponding to an underloaded condition (Fahlenkamp discloses burst mode operation when comparing Vfb to two thresholds V1 and V2) (for example see Fig. 3 and column 4 lines 39-43) of the PWM-controlled system, so that burst periods (for example see tonBurst) (Fig. 3) of the PWM control signal alternate with sleep periods (for example see toffBurst) (Fig. 3) of the PWM control signal; determining that the PWM-controlled system has transitioned to a normal load condition in response to a feedback signal (i.e., Vfb) (Fig. 3) exceeding a nominal load threshold (for example see V3) (Fig. 3); and suppressing the sleep periods (i.e., toffBurst) (Fig. 3) of the PWM control signal, while the PWM control circuit (i.e., 101) (Fig. 1) continues to operate in the burst mode (i.e., tonBurst) (Fig. 3), in response to the determining that the PWM-controlled system has transitioned to the normal load condition (for example see Fig. 3). Regarding claim 16, Fahlenkamp, as applied above, discloses transitioning from burst mode (i.e., tonBurst) (Fig. 3) to normal mode after the suppressing begins (see Fig. 3. Regarding claim 17, Fahlenkamp, as applied above, discloses the feedback signal (i.e., fb) (Fig. 3) is responsive to an output current of the PWM-controlled system. Regarding claim 21, Fahlenkamp, discloses a device (i.e., 100) (Fig. 1) comprising: a pulse width modulation (PWM) control circuit (i.e., 101) (Fig. 1) configurable to generate a PWM signal to control a transistor (i.e., 118) (Fig. 1) in a burst mode corresponding to an underloaded condition (For example Vfb between V1 and V2) (Fig. 3), so that burst periods (i.e., tonBurst) (Fig. 3) of the PWM signal alternate with sleep periods (i.e., toffBurst) (Fig. 3) of the PWM signal; and a burst mode logic circuit (for example see 126) (Fig. 1) coupled to the PWM control circuit (i.e., 101) (Fig. 1) and configurable to: determine that the device (i.e., 100) (Fig. 1) has transitioned to a normal load condition (for example see Fig. 3) in response to a feedback signal (i.e., Vfb) (Fig. 3) exceeding a nominal load threshold (i.e., V3) (Fig. 3); and suppress the sleep periods (i.e., toffBurst and Suppressing Sleep Period above) (Fig. 3) of the PWM signal while the PWM control circuit continues to operate in the burst mode, in response to the determining that the device has transitioned to the normal load condition. Regarding claim 22, Fahlenkamp, as applied above, discloses the burst mode logic circuit (i.e., 136) (Fig. 1) configurable to transition from burst mode to normal mode after the suppressing begins (for example see Fig. 3). Regarding claim 23, Fahlenkamp, as applied above, discloses the feedback signal (i.e., Vfb) is responsive to an output current of a power converter circuit including the transistor (i.e., 118) (Fig. 1). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 27-31 are rejected under 35 U.S.C. 103 as being unpatentable over Fahlenkamp US Patent 9768697 (Fahlenkamp) in view of Futamura US Publication 20130207625 (Futamura). Regarding claim 27, Fahlenkamp, discloses a system comprising: a sensor configurable to generate a sensed signal; a power converter circuit including a transistor (i.e., 118) (Fig. 1); and a controller device (i.e., 101) (Fig. 1) configurable to: control the transistor (i.e., 118) (Fig. 1) in a burst mode corresponding to an underloaded condition, so that burst periods (i.e., tonBusrt) (Fig. 3) alternate with sleep periods (i.e., toffBurst) (Fig. 1); and determine that the controller device (i.e., 101) (Fig. 1) has transitioned to a normal load condition in response to the sensed signal exceeding a nominal load threshold (i.e., V3) (Fig. 3); and suppress the sleep periods (i.e., toffBurst) (Fig. 1) while the controller device (i.e., 101) (Fig. 1) continues to operate in the burst mode (i.e., for example see Suppressing Sleep Period) (Fig. 3), in response to the determining that the controller device has transitioned to the normal load condition. Fahlenkamp fails discloses a optocoupler for sensing the state of the circuit through feedback but fails to disclose a current sensor. Futamura, in the same field of endeavor discloses the use of current sensor (i.e., 12) (Fig.1) to sensing the state of a circuit. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optionally provide a current sensor in Fahlenkamp, as taught by Futamura, in order to sense the state of the circuit. Regarding claim 28, Fahlenkamp in view of Futamura, as applied in linking claims, discloses the claimed invention. More particularly Fahlenkamp discloses the controller device (i.e., 101) (Fig. 1) is configurable to transition from burst mode to normal mode after the suppressing begins. Regarding claim 29, Fahlenkamp in view of Futamura, as applied in linking claims, discloses the claimed invention. More particularly Futamara discloses the current sensor (i.e., 12) (Fig.1) is configurable to generate the sensed signal responsive to an output current of the power converter circuit. Regarding claim 30, Fahlenkamp in view of Futamura, as applied in linking claims, discloses a system of wherein the controller device (i.e., 101) (Fig.1) is configurable to transition to operating in a normal mode (i.e., 124) (Fig.1) corresponding to the normal load condition in response to an interrupt service routine determining that a feedback signal (i.e., Vfb)(Fig. 3) indicates the normal load condition (for example see Fig. 6), and wherein the controller device (i.e., 101) (Fig.1) is configurable to determine that the feedback signal indicates the normal load condition is completed after transitioning to the normal load condition. Regarding claim 31, Fahlenkamp in view of Futamura, as applied in linking claims, discloses the claimed invention. More particularly Fahlenkamp discloses wherein the feedback signal (i.e., Vfb) (Fig. 3) indicates an output voltage of the power converter circuit. Allowable Subject Matter Claims 18-20, 24-26 and 32 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 18, Fahlenkamp, as applied above, discloses the feedback signal (.i.e., Vfb) (Fig. 3) is a first feedback signal; the transitioning the PWM control circuit (i.e., 101) (Fig. 1) to operating in a normal mode corresponding to the normal load condition of the PWM-controlled system (for example see column 5, lines 20-23); wherein the transitioning the PWM control circuit is performed in response to an interrupt service routine determining that the feedback signal indicates (for example see Fig. 6) the normal load condition; and wherein the determining that the second feedback signal indicates the normal load condition is completed after the determining that the PWM-controlled system has transitioned to the normal load condition is completed. Fahlenkamp, as applied above, fail to discloses wherein the transitioning the PWM control circuit is performed in response to an interrupt service routine determining that a second feedback signal indicates the normal load condition and wherein the determining that the second feedback signal indicates the normal load condition is completed after the determining that the PWM-controlled system has transitioned to the normal load condition is completed in combination will all recited element of linking claims. Claim 19 depends of claim 18. Claim 24 in combination with linking claims and all recited elements, is allowable for the same reasons as claim 18. Claim 25 depend of claim 24. Regarding claim 20, Fahlenkamp, as applied above, alone or in combination, fail to discloses the controlling performed in response to a burst mode flag, an output of a comparator that performs the determining, and a burst mask. Claim 26, in combination with linking claims and all recited elements, is allowable for the same reasons as claim 20. Claim 32 in combination with linking claims and all recited elements, is allowable for the same reasons as claim 20. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to YAHVEH COMAS TORRES whose telephone number is (571)272-4011. The examiner can normally be reached Mondays - Thursday 830am. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YAHVEH COMAS TORRES/Examiner, Art Unit 2838 /THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Jul 21, 2023
Application Filed
Jun 28, 2024
Response after Non-Final Action
Jul 05, 2024
Response after Non-Final Action
Mar 07, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603564
POWER CONVERTER AND CONTROLLING METHOD THEREOF
2y 5m to grant Granted Apr 14, 2026
Patent 12603504
IN RELATION TO DYNAMIC BRAKING SYSTEMS FOR BIPOLE POWER TRANSMISSION NETWORKS
2y 5m to grant Granted Apr 14, 2026
Patent 12597869
Automatic Boosting Current Adjustment for Zero Voltage Switching in Auxiliary Resonant Commutated Pole Inverter
2y 5m to grant Granted Apr 07, 2026
Patent 12542447
SIMULTANEOUS CHARGING AND POWER EXPORT USING N-LEG CONVERTER
2y 5m to grant Granted Feb 03, 2026
Patent 12542482
Method for Controlling Multiple Power Supplies
2y 5m to grant Granted Feb 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
93%
With Interview (+6.9%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 74 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month