DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/21/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 & 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2018/0189645 A1) and further in view of Sastry et al. (US 2022/0035607 A1).
Re Claim 1 & 10, Chen teaches a method for controlling a processing device to execute an application that runs on a neural network (NN), the processing device including a plurality of processing units arranged in a network-on-chip (NoC) architecture, comprising: (Chen; FIG. 1-10; Background, ¶ [0035]-[0040], [0088]; A processing device executing a application that run a neural network, the processing device including processors/CPUs arranged in a network-on-chip system (architecture).)
obtaining compiler information relating the application and the NoC; (Chen; FIG. 1-10; Background, ¶ [0016], [0031]-[0036]; Complier information/data relating to an application/program/software and the NoC.)
Chen does not explicitly suggest controlling the processing device to employ a first routing scheme to process the application when the compiler information does not meet a predefined requirement; and controlling the processing device to employ a second routing scheme to process the application when the compiler information meets the predefined requirement.
However, in analogous art, Sastry teaches controlling the processing device to employ a first routing scheme to process the application when the compiler information does not meet a predefined requirement; and (Sastry; FIG. 1-33; Background, Summary, ¶ [0152]-[0164], [0182]-[0190], [0216]-[0230], [0243]-[0264], [0283]-[0285]; The embodiment(s) detail comparable methodology such as variable routing protocols when certain requirements are not met.)
controlling the processing device to employ a second routing scheme to process the application when the compiler information meets the predefined requirement. (Sastry; FIG. 1-33; Background, Summary, ¶ [0152]-[0164], [0182]-[0190], [0216]-[0230], [0243]-[0264], [0283]-[0285]; The embodiment(s) detail comparable methodology such as the selection of a variable routing protocol when certain requirements are not met/met in data traffic transmission.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify Chen in view of Sastry to select a routing protocol for the reasons of processing, simulating and generating routing solution for data path in a Network-On-Chip environment. (Sastry Abstract)
Re Claim 2 & 11, Chen-Sastry discloses the method of claim 1, wherein the predefined requirement includes channel congestion occurring in the NoC. (Sastry; FIG. 1-33; Background, Summary, ¶ [0152]-[0164], [0182]-[0190], [0216]-[0230], [0243]-[0264], [0283]-[0285]; Constraints such as congestion of the NoC.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify Chen in view of Sastry to select a routing protocol for the reasons of processing, simulating and generating routing solution for data path in a Network-On-Chip environment. (Sastry Abstract)
Claim(s) 3-4, 8, 12-13, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2018/0189645 A1), in view of Sastry et al. (US 2022/0035607 A1) and further in view of Cowperthwaite et al. (US 2023/0297421 A1).
Re Claim 3 & 12, Chen-Sastry discloses the method of claim 2, yet does not explicitly suggest wherein the compiler information includes bandwidths of channels of the NN and throughput of the NoC.
However, in analogous art, Cowperthwaite teaches wherein the compiler information includes bandwidths of channels of the NN and throughput of the NoC. (Cowperthwaite; FIG. 1-4, 9-11, 16; ¶ [0110]-[0111], [0127], [0248], [0278], [0471], [0477]; The embodiment(s) detail neural networks, bandwidths of communication links/channels and throughput of related NoCs.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify Chen-Sastry in view of Cowperthwaite to include bandwidths and throughput for the reasons of creating a system that provides processing resources to a plurality of clients. (Cowperthwaite Abstract)
Re Claim 4 & 13, Chen-Sastry-Cowperthwaite discloses the method of claim 3, wherein the first routing scheme includes buffer gating control and contention-free switching. (Cowperthwaite; FIG. 1, 34; ¶ [0353], [0385], [0440], [0471]; The system detail routing features, buffer related management/flow control (buffer gating control) and CDMA (contention-free switching).)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify Chen-Sastry in view of Cowperthwaite to include bandwidths and throughput for the reasons of creating a system that provides processing resources to a plurality of clients. (Cowperthwaite Abstract)
Re Claim 8 & 17, Chen-Sastry discloses the method of claim 1, yet does not explicitly suggest wherein the NN includes a deep NN (DNN).
However, in analogous art, Cowperthwaite teaches wherein the NN includes a deep NN (DNN). (Cowperthwaite; FIG. 9-11; ¶ [0106], [0176]; Deep neural network.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify Chen-Sastry in view of Cowperthwaite to include bandwidths and throughput for the reasons of creating a system that provides processing resources to a plurality of clients. (Cowperthwaite Abstract)
Claim(s) 5 & 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2018/0189645 A1), in view of Sastry et al. (US 2022/0035607 A1), in view of Cowperthwaite et al. (US 2023/0297421 A1) and further in view of KUMAR (US 2022/0012177 A1).
Re Claim 5 & 14, Chen-Sastry-Cowperthwaite discloses the method of claim 3, yet does not explicitly suggest wherein the second routing scheme includes an adaptive routing algorithm.
However, in analogous art, KUMAR teaches wherein the second routing scheme includes an adaptive routing algorithm. (KUMAR; FIG. 1; ¶ [0010]; Adaptive routing.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify Chen-Sastry-Cowperthwaite in view of KUMAR to incorporate adaptive routing for the reasons of creating a method of dynamically change the path taken between two points on the network based on the stated of the network. (KUMAR ¶ [0010])
Claim(s) 6-7, 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2018/0189645 A1), in view of Sastry et al. (US 2022/0035607 A1), in view of Cowperthwaite et al. (US 2023/0297421 A1) and further in view of Zhu et al. (US 2021/0374518 A1).
Re Claim 6 & 15, Chen-Sastry-Cowperthwaite discloses the method of claim 3, yet does not explicitly suggest wherein the bandwidths of the channels of the NN depend on partitioning of tensor data of the application input to layers of the NN.
However, in analogous art, Zhu teaches wherein the bandwidths of the channels of the NN depend on partitioning of tensor data of the application input to layers of the NN. (Zhu; FIG. 1-10; Background, ¶ [0059], [0064]-[0067], [0101], [0145], [0330]-[0350], [0472]-[0480]; Bandwidth/throughput of channels/links, tensor related data, application layers of a neural network.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify Chen-Sastry-Cowperthwaite in view of Zhu to partition data for the reasons of speed up inferencing in a neural network. (Zhu Abstract)
Re Claim 7 & 16, Chen-Sastry-Cowperthwaite-Zhu discloses the method of claim 6, wherein the tensor data are partitioned into XY-partition tiles or K-partition tiles. (Zhu; FIG. 1-10; Background, ¶ [0059], [0064]-[0067], [0330]-[0340]; K partition related to tensor related data.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify Chen-Sastry-Cowperthwaite in view of Zhu to partition data for the reasons of speed up inferencing in a neural network. (Zhu Abstract)
Claim(s) 9 &18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2018/0189645 A1), in view of Sastry et al. (US 2022/0035607 A1) and further in view of Zhu et al. (US 2021/0374518 A1).
Re Claim 9 & 18, Chen-Sastry discloses the method of claim 1, yet does not explicitly suggest wherein the processing device is a deep learning accelerator (DLA).
However, in analogous art, Zhu teaches wherein the processing device is a deep learning accelerator (DLA). (Zhu; FIG. 1, 11; ¶ [0151]-[0152]; A deep learning accelerator.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify Chen-Sastry in view of Zhu to partition data for the reasons of speed up inferencing in a neural network. (Zhu Abstract)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER B ROBINSON whose telephone number is (571)270-0702. The examiner can normally be reached M-F 7:00-3:00 EST.
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/CHRISTOPHER B ROBINSON/ Primary Examiner, Art Unit 2443
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