Prosecution Insights
Last updated: April 19, 2026
Application No. 18/356,576

TRANSCONDUCTOR WITH CURRENT LIMITER

Non-Final OA §103§112
Filed
Jul 21, 2023
Examiner
MARANO, NATASHA YOLANDA
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Nokia Solutions and Networks Oy
OA Round
1 (Non-Final)
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant

Examiner Intelligence

Grants only 0% of cases
0%
Career Allow Rate
0 granted / 0 resolved
-68.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
4 currently pending
Career history
4
Total Applications
across all art units

Statute-Specific Performance

§103
33.3%
-6.7% vs TC avg
§102
33.3%
-6.7% vs TC avg
§112
33.3%
-6.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 0 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Foreign Priority is not claimed in this application. Information Disclosure Statement The information disclosure statements (IDS) submitted on 12/08/2023 and 05/17/2024 were filed and entered into the record for application examined in art unit 2843. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification The disclosure is objected to because of the following informalities: In paragraph [0035], line 7, and again in paragraph [0037], line 9, the specification refers to an element 331 in Fig. 3; However, such label does not appear in Fig. 3 and thus renders such a label vague in meaning. In paragraph [0035], line 8, the specification refers to an element 332 in Fig. 3; However, such label does not appear in Fig. 3 and thus renders such a label vague in meaning. In paragraph [0038], line 7, the specification refers to elements “Voffset1 and Voffset2” in Fig. 4; However, such labels do not appear in Fig. 4, or any figures and thus renders such labels vague in meaning. In paragraph [0038], Line 12 and again in line 14, the specification refers to elements 411 and 413 in Fig. 3; However, such labels do not appear in Fig. 3 and thus renders such labels vague in meaning. In paragraph [0043], line 1, the specification refers to three transconductors 320, 331-1, 331-2 in Fig.4; However, these elements are not present in Fig. 4. Instead, the elements are depicted in Fig. 3, which needs to be correspondingly described in the detail description of the specification. In paragraph [0043], line 7, the specification refers to “curves 105 and 106” in Fig.4; However, such labels do not appear in Fig. 4 and thus renders such labels as vague in meaning. Paragraphs [0043] and [0045] are unclear and inconsistent in its references to the drawings. For example, these paragraphs refer Appropriate corrections are required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 13 – 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 13 recites: ” An apparatus, comprising: a limiting amplifier operable to convert a differential input voltage Vin to a differential output current, comprising: a first circuit having a substantially non-zero first trans-conductance Tci for |Vin|≤ Vi; and PNG media_image1.png 6 5 media_image1.png Greyscale a limiter circuit having a second trans-conductance Tc2, wherein: Tc2 is smaller in magnitude than Tci for PNG media_image2.png 9 21 media_image2.png Greyscale |Vin|≤ V2 < Vi, and Tc2 is greater in magnitude than Tci in some range of |Vin| above V2; wherein the limiter circuit is connected so that an output current of the limiter circuit is subtracted from an output current of the first circuit”. Claim 13 recites multiple variables and functional relationships, such as (Vin1, Tc1, Tc2) without clearly identifying the meaning of these parameters and thereby failing to provide clear boundaries for the claimed invention. Thereby, the scope of claim 13 is ambiguous and cannot be readily determined. Accordingly, clarification is needed. Dependent claims 14 – 18 inherit the deficiencies of independent claim 13 and thus are also rejected. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1 – 5, 12 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki (PGPub number US 2,016/9,306,541 B2) in view of Zeller (PGPub number US 2011/7,876,153 B1). Suzuki teaches a transimpedance amplifier having differential outputs (i.e. 10), as shown in Fig. 5. It also illustrates a differential stage (output amplifier 4) configured to convert a differential input signal to a differential output signal producing differential output signal However, Suzuki does not teach a nonlinear current limiting or multi-tanh current limiter connected across the differential output nodes. Zeller teaches a multi-tanh type current limiter connected across differential output nodes, as shown in Fig. 3. It also illustrates first and second tanh-type current limiter cells coupled between differential nodes (Outp, Outn), wherein the limiter output currents are subtracted from the differential signal path. The limiter cells are controlled via control nodes (SV1, SV2), which receive controlled currents through resistive elements, thereby establishing threshold voltages at which nonlinear current limiting behavior occurs. It would have been obvious to one of ordinary skill in the art to replace the differential output stage (4) of Suzuki Fig. 5 with the limiter circuit as taught in Fig. 3 of Zeller as an obvious substitution of art recognized differential amplifier circuits in order to introduce controlled nonlinear current limiting while maintaining the differential transimpedance operation of Suzuki. Such a modification provides predictable control of output current saturation and linear operating range, which is a well-recognized design objective in high-speed receiver circuits. Regarding claim 2, the resultant combination of Suzuki as modified by Zeller teaches the claimed invention except for the multi-tanh type current limiter comprises first and second tanh-type current limiters connected to subtract an output current thereof from an output current of the TIA; and wherein the first and second tanh-type current limiters are biased to be shifted in voltage. Zeller discloses a multi-tanh type current limiter comprising first and second tanh-type current limiters, as shown in Fig.3, including a first limiter cell formed by transistors T5 – T8 biased by SV1 and a second limiter cell formed by transistors T9 – T12 biased by SV2, each supplied by bias currents IBIAS/2. As shown in Fig.3, the limiter cells are connected across the differential output nodes (OUTp, OUTn), such that the limiter cells draw current from the output nodes, thereby subtracting an output current thereof from the output current of the transimpedance amplifier. Furthermore, Zeller also discloses that the first and second tanh-type current limiters are biased to be shifted in voltage of the limiter cells, thereby shifting the tanh response. It would have been further obvious to one of ordinary skill in the art to apply Zeller’s multi-tanh current limiter across the differential outputs of the transimpedance amplifier of the resultant combination from claim 1 in order to provide controlled nonlinear current limiting while preserving linear operation of TIA within a desired signal range, which is a well-recognized design objective in high-speed receiver circuits. Regarding claim 3, the resultant combination of Suzuki as modified by Zeller teaches the claimed invention except for the first and second tanh-type current limiters are biased to be shifted by a voltage. Zeller discloses biasing control of tanh-type limiter cells via control nodes (SV1, SV2) supplied by bias circuitry, which shifts the operating point of the limiter cells and thereby shifts the tanh response in voltage. Incorporating such bias control into the combined system would have been a further obvious modification to adjust limiter turn-on behavior and operating range, providing predictable control of nonlinear response in the transimpedance amplifier. Regarding claim 4, the resultant combination of Suzuki as modified by Zeller teaches the claimed invention except for the multi-tanh type current limiter comprises a multi- tanh doublet. Zeller discloses a multi-tanh type current limiter shown in Fig. 3 comprises first and second tanh-type current limiter cells, including a first limiter cell biased by SV1 and a second limiter cell biased by SV2, each having a substantially identical structure and being coupled across the differential output nodes (OUTp and OUTn). The duplicated and symmetrically arranged tanh-type limiter cells operate together to form a tanh doublet. It would have been further obvious to one of ordinary skill in the art to implement the current limiter of the resultant combination as a multi-tanh doublet by providing two tanh limiter cells in combination as a predictable design choice to shape the nonlinear transfer characteristic and provide controlled current limiting. Regarding claim 5, the result in combination of Suzuki as modified by Zeller teaches the claimed invention except for the multi-tanh type current limiter comprises two non-degenerated transistor pairs. Zeller discloses a multi-tanh type current limiter comprising first and second limiter cells formed by transistor pairs, as shown in Fig. 3., wherein each limiter cell includes a differential transistor pair (T5 – T6 and T9 – T10) whose emitters/sources are directly biased by current sources (IBIAS/2) without any emitter or source degeneration elements. Accordingly, Zeller teaches a multi-tanh type current limiter comprising two non-degenerated transistor pairs. It would have been further obvious to one of ordinary skill in the art to implement the limiter cells using non-degenerated transistor pairs, at taught by Zeller, in order to obtain stronger and more predictable nonlinear current limiting. Regarding claim 12, the resultant combination discloses the claimed invention except for the transimpedance circuit being usable in a coherent optical receiver. However, note that in the background discussion in Suzuki (e.g. see column 2, lines 26 & 27), Suzuki discloses that optical receivers are known to include a transimpedance amplifier therein. Accordingly, it would have been further obvious in view of the references, taken as a whole, to have substituted the specific transimpedance amplifier circuit of the resultant combination in place of the known transimpedance amplifier found in an optical receiver. Such a modification would have been considered an obvious substitution of art recognized transimpedance amplifiers usable in an optical receiver, especially since the generic nature of the transimpedance amplifier in the optical receiver would have suggested that any equivalent transimpedance amplifier, such as the transimpedance amplifier of the resultant combination, would have usable within the optical receiver, thereby suggesting the obviousness of such a further modification Allowable Subject Matter Claims 6 – 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATASHA Y MARANO whose telephone number is (571)272-9512. The examiner can normally be reached Mon - Fri 7:30am - 3:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren-Baltzell can be reached at 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. NATASHA Y. MARANO Examiner Art Unit 2843 /ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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Prosecution Timeline

Jul 21, 2023
Application Filed
Feb 02, 2026
Non-Final Rejection — §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
Grant Probability
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 0 resolved cases by this examiner. Grant probability derived from career allow rate.

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