Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments filed February 16th, 2026 have been entered. Claims 1-20 remain pending in the application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-4, 9, 13-16, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng (US 20230065446 A1).
Regarding claim 1, FIG. 11, FIG. 13 and FIG. 15 of Cheng teach a semiconductor device (paragraph
0003), the semiconductor device comprising:
one or more source and drain regions (82; FIG. 11; paragraph 0063) above a substrate layer (120; FIG. 11; paragraph 0040) each of the one or more source and drain regions (82; FIG. 11, paragraph 0063) having a filleted shape (FIG. 11A), wherein a bottom portion of the filleted shape includes a horizontal bottom surface connecting two sloped surfaces (41; FIG. 11A; paragraph 0058); and
a first dielectric bar (200, 220; FIG. 13; paragraph 0073) between each of the one or more source and drain regions (82; FIG. 13A; paragraph 0074),
wherein the two sloped surfaces on a backside of the semiconductor device are surrounded by a metal contact (75; FIG. 15; paragraph 78).
Regarding claim 2, FIG. 13 of Cheng teaches the semiconductor device of claim 1, further comprising:
a plurality of nanosheet gates (22; FIG. 13; paragraph 0069) extended between the one or more source and drain regions (82; FIG. 13; paragraph 0063);
and a second dielectric bar (200, 220; FIG. 13; paragraph 0073) between each of two nanosheet gates of the plurality of nanosheet gates (22; FIG. 13; paragraph 0055).
Regarding claim 3, FIG. 12 of Cheng teaches the semiconductor device of claim 1. This further comprises an airgap (92; FIG. 12C; paragraph 0068) between two sloped surfaces on a frontside of the semiconductor device (41; FIG. 11A; paragraph 0058).
Regarding claim 4, FIG. 13 of Cheng teaches the semiconductor device of claim 3, wherein the airgap is sealed by the first dielectric bar (200, 220; FIG. 13; paragraph 0073), a shallow trench isolation layer (36; FIG. 13; paragraph 0052), and a gate (200; FIG. 13; paragraph 0073).
Regarding claim 9, Cheng teaches the semiconductor device of claim 1, wherein the metal contact (75; FIG. 15; paragraph 78) is in contact with the first dielectric bar (200, 220; FIG. 15; paragraph 0078).
Regarding claim 13, FIG. 1, FIG. 11, FIG. 13, and FIG. 15 of Cheng teach a method for forming a semiconductor device (paragraph 0003), the method comprising:
forming one or more source and drain regions (82; FIG. 11; paragraph 0063) above a substrate
layer (120; FIG. 11; paragraph 0040) each of the one or more source and drain regions (82; figure 11, paragraph 0063) having a filleted shape (FIG. 11A), wherein a bottom portion of the filleted shape includes a horizontal bottom surface connecting two sloped surfaces (41; FIG. 11A; paragraph 0058);
forming a first dielectric bar (200, 220; FIG. 13; paragraph 0073) between each of the one or more source and drain regions (82; FIG. 13A; paragraph 0074); and
forming a metal contact (75; FIG. 15; paragraph 0078) surrounding THE two sloped surfaces on a backside of the semiconductor device.
Regarding claim 14, FIG. 13 of Cheng teaches the method of claim 13, further comprising:
forming a plurality of nanosheet gates (22; FIG. 13; paragraph 0069) extended between the one or more source and drain regions (82; FIG. 13; paragraph 0063); and
forming a second dielectric bar (200, 220; FIG. 13; paragraph 0073) between each of two nanosheet gates of the plurality of nanosheet gates (22; FIG. 13; paragraph 0055).
Regarding claim 15, FIG. 11 and FIG. 12 of Cheng teaches the method of claim 13. This further comprises an airgap (92; FIG. 12C; paragraph 0068) between two sloped surfaces on a frontside of the semiconductor device (41; FIG. 11A; paragraph 0058).
Regarding claim 16, FIG. 13 of Cheng teaches the method of claim 15, wherein the airgap is sealed by the first dielectric bar (200, 220; FIG. 13; paragraph 0073), a shallow trench isolation layer (36; FIG. 13; paragraph 0052), and a gate (200; FIG. 13; paragraph 0073).
Regarding claim 20, FIG. 11, FIG. 13, and FIG. 15 of Cheng teach a semiconductor device (paragraph 0003). This semiconductor device comprises:
one or more source and drain regions (82; FIG. 11; paragraph 0063) above a substrate layer (120; FIG. 11; paragraph 0040) each of the one or more source and drain regions (82; FIG. 11, paragraph 0063) having a filleted shape (FIG. 11A), wherein a bottom portion of the filleted shape includes a horizontal bottom surface connecting two sloped surfaces (41; FIG. 11A; paragraph 0058);
an airgap (92; FIG. 12C; paragraph 0068) between the two sloped surfaces (Figure 12A) on a frontside of the semiconductor device (41; FIG. 11A; paragraph 0058); and
a first dielectric bar (200, 220; FIG. 13; paragraph 0073) between each of the one or more source and drain regions (82; FIG. 13A; paragraph 0074).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5-8 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Ahn et al. (US 20240421162 A1).
Regarding claim 5, Cheng teaches the semiconductor device as described in claim 1, but does not describe the placeholder beneath the source and drain regions.
FIG. 3A of Ahn et al. teaches that there is a placeholder (106; FIG. 3A; paragraph 0070) located beneath the source and drain regions (130; FIG. 3A; paragraph 0070).
Both Cheng and Ahn et al. are considered analogous to the claimed invention because they are in the same field of semiconductors with source and drain regions. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified to have a placeholder below the source and drain regions. Doing so would keep the source/drain region from being exposed from underneath until the source/drain region is removed (paragraph 0153).
Regarding claim 6, the combination of Cheng in view of Ahn et al. teaches the semiconductor device as described in claim 5. Cheng does not teach
the placeholder is in contact with the horizontal bottom surface; and
the placeholder is not in contact with two sloped surfaces on a frontside of the semiconductor device.
FIG. 3A of Ahn et al. teaches
the placeholder (106; FIG. 3A; paragraph 0070) is in contact with the horizontal bottom surface (FS; FIG. 3A; paragraph 0033); and
the placeholder is not in contact with two sloped surfaces on a frontside of the semiconductor device (FIG. 3A).
Accordingly, it would have been obvious to the person with ordinary skill in the art before the effective filing date of the claimed invention to ascertain that the horizontal surface would keep the place holder on the same side as insulating structures if said structures are intended to be located beneath the source/drain regions (paragraph 0033).
Regarding claim 7, the combination of Cheng in view of Ahn et al. teaches the semiconductor device as described in claim 5. Cheng does not teach:
a first critical dimension of the metal contact is larger than a second critical dimension of the placeholder; and
the first and second critical dimensions are extended in a first direction.
FIG. 3A of Ahn et al. teaches:
a first critical dimension of the metal contact (MPV; FIG. 3A; paragraph 0064) that is larger than a second critical dimension of the placeholder (106; FIG. 3A; paragraph 0070); and
the first and second critical dimensions are extended in a first direction (FIG. 3A).
Accordingly, it would have been obvious to a person with ordinary skill in the art before the effective filing date to determine that the metal contact would need to be longer than the placeholder as the former needs to extend outwards to act as a connector (paragraph 0069).
Regarding claim 8, the combination of Cheng in view of Ahn et al. teaches the semiconductor device as described in claim 5. Cheng does not teach:
a third critical dimension of the metal contact is substantially equal to a fourth critical dimension of the placeholder; and
the third and fourth critical dimensions are extended in a second direction.
FIG. 3A of Ahn et al. teaches:
a third critical dimension of the metal contact (MPV; FIG. 3A; paragraph 0064) is substantially equal to a fourth critical dimension of the placeholder (106; FIG. 3A; paragraph 0070); and
the third and fourth critical dimensions are extended in a second direction (FIG. 3A).
A person of ordinary skill in the art would determine it is necessary for the metal contact to be the same width as the placeholder if it were to take up a reasonable amount of space in the semiconductor device without making contact with the placeholder (paragraph 0073).
Regarding claim 17, Cheng teaches the method for forming a semiconductor device as described in claim 13, but does not describe forming a placeholder located under at least one of the one or more source and drain regions, wherein:
the placeholder is in contact with the horizontal bottom surface; and
the placeholder is not in contact with two sloped surfaces on a frontside of the semiconductor device.
a placeholder (106; FIG. 3A; paragraph 0070) located beneath the source and drain regions (130; figure 3A; paragraph 0070);
the placeholder (106; FIG. 3A; paragraph 0070) is in contact with the horizontal bottom surface (FS; FIG. 3A; paragraph 0033); and
the placeholder is not in contact with two sloped surfaces on a frontside of the semiconductor device (FIG. 3A).
Both Cheng and Ahn et al. are considered analogous to the claimed invention because they are in the same field of semiconductors with source and drain regions. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified to have a placeholder below the source and drain regions. Doing so would keep the source/drain region from being exposed from underneath until the source/drain region is removed (paragraph 0153). As well, it would keep the place holder on the same side as insulating structures if said structures are intended to be located beneath the source/drain regions (paragraph 0033).
Regarding claim 18, the combination of Cheng in view of Ahn et al. teaches the method as described in claim 17. Cheng does not teach:
a first critical dimension of the metal contact is larger than a second critical dimension of the placeholder;
the first and second critical dimensions are extended in a first direction;
a third critical dimension of the metal contact is substantially equal to a fourth critical dimension of the placeholder; and
the third and fourth critical dimensions are extended in a second direction.
Figure 3A of Ahn et al. teaches:
a first critical dimension of the metal contact (MPV; FIG. 3A; paragraph 0064) that is larger than a second critical dimension of the placeholder (106; FIG. 3A; paragraph 0070);
the first and second critical dimensions are extended in a first direction (Figure 3A);
a third critical dimension of the metal contact (MPV; FIG. 3A; paragraph 0064) is substantially equal to a fourth critical dimension of the placeholder (106; FIG. 3A; paragraph 0070); and
the third and fourth critical dimensions are extended in a second direction (FIG. 3A).
Accordingly, it would have been obvious to a person with ordinary skill in the art before the effective filing date to determine that the metal contact would need to be longer than the placeholder as the former needs to extend outwards to act as a connector (paragraph 0069) and that it is necessary for the metal contact to be the same width as the placeholder if it were to take up a reasonable amount of space in the semiconductor device without making contact with the placeholder (paragraph 0073).
Allowable Subject Matter
Claims 10-12, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 10 would be allowable as it discloses a semiconductor device that includes a backside interlayer dielectric (BILD) located under a shallow trench isolation (STI), wherein the BILD includes materials different than the STI, a self-aligned substrate isolation layer, and a gate isolation layer.
Cheng discloses the semiconductor device in claim 1, as well as it further comprising an interlayer dielectric (ILD) that includes a gate isolation layer and has different materials than the shallow trench isolation (STI). Cheng does not disclose that the ILD is specifically a backside interlayer dielectric, that it is located under the STI, nor that it includes a self-aligned substrate isolation layer.
Ahn et al. do not provide any relevant alteration to this given structure.
Huang et al. (US 20220375860 A1) discloses a device with a backside interlayer dielectric located under a shallow trench isolation layer. Huang et al. does not disclose that the semiconductor device includes a substrate isolation layer. Based on the configuration of Huang et al., it would be improper hindsight to modify Cheng so that the interlayer dielectric includes a self-aligned substrate isolation layer.
Claims 11 and 12 would be allowable because they depend on claim 10.
Claim 19 would be allowable as it discloses a semiconductor device that includes a backside interlayer dielectric (BILD) located under a shallow trench isolation (STI), wherein the BILD includes materials different than the STI, a self-aligned substrate isolation layer, and a gate isolation layer.
Cheng discloses the method for the semiconductor device in claim 13, as well as forming an interlayer dielectric (ILD) that includes a gate isolation layer and has different materials than the shallow trench isolation (STI). Cheng does not disclose that the ILD is specifically a backside interlayer dielectric, that it is located under the STI, nor that it includes a self-aligned substrate isolation layer.
Ahn, et al. do not provide any relevant alteration to the this given method of forming this structure.
Huang et al. discloses a device with a backside interlayer dielectric located under a shallow trench isolation layer. Huang et al. do not disclose that the semiconductor device includes a substrate isolation layer. Based on the configuration of Huang et al., it would be improper hindsight to modify Cheng so that the interlayer dielectric includes a self-aligned substrate isolation layer.
Response to Arguments
Applicant' s arguments with respect to claim 19 being listed as both a rejection and allowable subject matter have been considered are acknowledged as a typo which has been corrected.
Applicant's arguments for claims 1, 13, and 20 filed February 26th, 2026 have been fully considered but they are not persuasive.
In response to applicant's argument that claim 1, claim 13, and claim 20's dielectric bar is not equivalent to the dielectric layer of replacement gate 200 of Cheng, as well as how the backside metal plug interacts differently with the source/drain regions in Cheng in comparison with the specifications, the fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985).
Applicant's arguments for claims 1 and 13 filed February 26th, 2026 have been fully considered but they are not persuasive.
In response to applicant's argument that the backside metal plug, the fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985).
Applicant's arguments for claim 20 filed February 26th, 2026 have been fully considered but they are not persuasive.
In response to applicant's argument in that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., Claim 20's airgap specifically being a permanent fixture rather than a temporary aspect) are not recited in the rejected claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kusunoki et al. (US 20210217805 A1) concerns an LED display device made up of semiconductor layers. Sharma (US 20200279850 A1) concerns an eDRAM memory cell connected to a circuit made of semiconductor materials. Wang (US 20230066705 A1) concerns a semiconductor device with conductive features formed from sacrificial self-aligned contact layers and sacrificial metal contact etch stop layers.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A VLCEK whose telephone number is (571)272-9665. The examiner can normally be reached Mon-Fri, 9:00 AM -5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB ALEXANDER VLCEK/Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817