Prosecution Insights
Last updated: May 29, 2026
Application No. 18/357,259

QUANTUM GRAPH TRANSFORMERS

Non-Final OA §102
Filed
Jul 24, 2023
Examiner
WILLIAMS, JEFFERY A
Art Unit
2488
Tech Center
2400 — Computer Networks
Assignee
International Business Machines Corporation
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
770 granted / 922 resolved
+25.5% vs TC avg
Moderate +9% lift
Without
With
+9.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
29 currently pending
Career history
973
Total Applications
across all art units

Statute-Specific Performance

§101
2.6%
-37.4% vs TC avg
§103
76.4%
+36.4% vs TC avg
§102
7.7%
-32.3% vs TC avg
§112
10.9%
-29.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 922 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-5, 9-12, 16-20, and 23-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Naveh et al. (Naveh) (US 2022/0405194). Regarding claims 1 and 9, Naveh discloses a system comprising: a memory that stores computer executable components ([0018] a program is stored in memory and executed); a processor ([0005], a quantum computer) that executes computer executable components stored in the memory ([0018] a program is stored in memory and executed), wherein the computer executable components comprise: a quantum graph transformer ([0063] a quantum program embodied as a quantum circuit) that learns a quantum encoding of a graph ([0094], [0095], a graph of entanglement properties may be generated in which nodes represent qubits and edges represent entanglement between the qubits), wherein the learning comprises: generating a quantum graph state from an encoding quantum circuit ([0063], a quantum program embodied as a quantum circuit) based on qubits representing nodes of the graph ([0094], [0095], a graph of entanglement properties may be generated in which nodes represent qubits and edges represent entanglement between the qubits, [0063], [0096] an entanglement graph represents a state of entanglement of qubits), wherein the quantum graph state serves as quantum representation of the graph ([0094], [0095], a graph of entanglement properties may be generated in which nodes represent qubits and edges represent entanglement between the qubits, [0063], [0096] an entanglement graph represents a state of entanglement of qubits). Regarding claims 2, 10, and 18, Naveh discloses wherein the learning further comprises: generating a final quantum state and graph encodings from a variational quantum circuit ([0117], [0118], the quantum circuit is able to be updated (i.e. variable)) based on the quantum graph state ([0095], a full (final) graph is generated, [0040], [0041], [0102], [0063], a final output state is generated using the quantum circuits, [0107], the resulting graph (final graph) is displayed to a user). Regarding claims 3, 11, and 19, Naveh discloses wherein the encoding quantum circuit comprises Hadamard gates, wherein the Hadamard gates are applied on the qubits ([0063] Hadamard gates are applied to qubits). Regarding claims 4, 12, and 20, Naveh discloses wherein the encoding quantum circuit further comprises a set of controlled-Z gates ([0063] controlled Z gates are applied to qubits) that are applied on pairs of the qubits representing nodes that are connected in the graph ([0093], [0095] gates are applied to pairs of qubits) and produce the quantum graph state ([0063], [0095], an output state is generated by applying gates to entanglement graphs). Regarding claims 5, 16, and 23, Naveh discloses wherein different encoding quantum circuits are utilized for different graphs ([0087], [0095], [0106], the quantum circuit and updated quantum circuits is/are able to be applied to different groups of sub graphs). Regarding claim 17, the limitations of claim 17 are rejected in the analysis of claim 1 (See claim 1 above). The examiner notes, in [0077] of the applicant’s filed specification, the applicant explicitly disclaims the use of transitory signals as a form of computer readable storage media. Regarding claim 24, Naveh discloses a computer-implemented method comprising: building, by a system operatively coupled to a processor, a quantum encoding circuit based on an input graph ([0095], [0107], [0114], a graph is input for synthesizing a quantum program (circuit)); generating, by the system, a quantum graph state from the quantum encoding circuit based on input qubits representing nodes of the input graph ([0094], [0095], a graph of entanglement properties may be generated in which nodes represent qubits and edges represent entanglement between the qubits, [0063], [0096] an entanglement graph represents a state of entanglement of qubits); generating, by the system, a final quantum state and graph encodings from a variational quantum circuit based on the quantum graph state ([0095], a full (final) graph is generated, [0040], [0041], [0102], [0063], a final output state is generated using the quantum circuits, [0107], the resulting graph (final graph) is displayed to a user); and updating, by the system, parameters of the variational quantum circuit based on a function of measurements over the final quantum state and a supervisory signal ([0040]-[0042], [0045], [0079], [0089], the quantum circuit is run until a completion criteria is met and is modified to change the zero value of a cubit in a final or intermediate state based on a difference between a target value (supervisory signal) and a the existing value of the cubit (measurements over a final quantum state). Regarding claim 25, the limitations of claim 25 are rejected in the analysis of claims 1 and 24 (See claims 1 and 24 above). The examiner notes, in [0077] of the applicant’s filed specification, the applicant explicitly disclaims the use of transitory signals as a form of computer readable storage media. Allowable Subject Matter Claims 6-8, 13-15, 21, and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Denchev et al. (Denchev) (US 2019/0164059) ([0050], a quantum graph is generated). Cowtan et al. (Cowtan) (US 2023/0237361) ([0005], a quantum circuit is updated to reduce a difference between a ground reference state and a current state of qubits in the system). Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEFFERY A WILLIAMS whose telephone number is (571)270-7579. The examiner can normally be reached M-F 8:00-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sath Perungavoor can be reached at 571-272-7455. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JEFFERY A WILLIAMS/Primary Examiner, Art Unit 2488
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Prosecution Timeline

Jul 24, 2023
Application Filed
Feb 26, 2026
Non-Final Rejection mailed — §102
May 04, 2026
Applicant Interview (Telephonic)
May 06, 2026
Examiner Interview Summary

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
93%
With Interview (+9.2%)
2y 7m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 922 resolved cases by this examiner. Grant probability derived from career allowance rate.

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